EMTP simul(19)

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226 Power systems electromagnetic transients simulation

t

ttZ

tZ

1 Interpolation

2 Backward Euler step (half step)

3 Trapezoidal step (normal step)

tZ+t/2

t+t tA+t

tZ+

1

2

3

i (t)

Figure 9.8 Interpolating to point of switching

Time

tS

tS+t

iL (t)

vL (t)

Figure 9.9 Jumps in variables

step as the values at tZ+ i.e.

vL(tZ+) = vLtZ +

t

2

iC(tZ+) = iCtZ +

t

2

(9.10)

Using these values at time point tZ+

, the history terms for a normal full step can be

calculated by the trapezoidal rule, and a step taken. This procedure results in a shifted

time grid (i.e. the time points are not equally spaced) as illustrated in Figure 9.8.

PSCAD/EMTDC also interpolates back to the zero crossing, but then takes a full

time step using the trapezoidal rule. It then interpolates back on to t+ t so as to

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Power electronic systems 227

tZ tZ+tt+t

i (t)

t

t

Z

1

2

3

Figure 9.10 Double interpolation method (interpolating back to the switchinginstant)

keep the same time grid, as the post-processing programs expect equally spaced time

points. This method is illustrated in Figure 9.10 and is known as double interpolation

because it uses two interpolation steps.Interpolation has been discussed so far as a method of removing spikes due, for

example, to inductor current chopping. PSCAD/EMTDC also uses interpolation to

remove numerical chatter. Chatter manifests itselfas a symmetrical oscillationaround

the true solution; therefore, interpolating back half a time step will give the correct

resultandsimulation canproceed from this point. Voltageacross inductorsandcurrent

in capacitors both exhibit numerical chatter. Figure 9.11 illustrates a case where the

inductor current becoming zero coincides with a time point (i.e. there is no current

chopping in the inductive circuit). Step 1 is a normal step and step 2 is a half time

step interpolation to the true solution for v(t). Step 3 is a normal step and Step 4 isanother half time step interpolation to get back on to the same time grid.

The two interpolation procedures, to find the switching instant and chatter

removal, are combined into one, as shown in Figure 9.12; this allows the connec-

tion of any number of switching devices in any configuration. If the zero crossing

occurs in the second half of the time step (not shown in the figure) this procedure has

to be slightly modified. A double interpolation is first performed to return on to the

regular time grid (at t+t) and then a half time step interpolation performed afterthe next time step (to t+ 2t) is taken. The extra solution points are kept internal toEMTDC (not written out) so that only equal spaced data points are in the output file.

PSCAD/EMTDC invokes the chatter removal algorithm immediately whenever

there is a switching operation. Moreover the chatter removal detection looks for

oscillation in the slope of the voltages and currents for three timesteps and, if detected,

implements a half time-step interpolation. This detection is needed, as chatter can be

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t t+t t+2t t+3t

t

1

2

3

4

v (t)

Figure 9.11 Chatter removal by interpolation

initiated bystepchanges incurrent injectionorvoltagesources inaddition toswitching

actions.

The use of interpolation to backtrack to a point of discontinuity has also been

adopted in the MicroTran version of EMTP [9]. MicroTran performs two half time

steps forward of the backward Euler rule from the point of discontinuity to properly

initialise the history terms of all components.

The ability to write a FORTRAN dynamic file gives the PSCAD/EMTDC user

great flexibility and power, however these files are written assuming that they are

called at every time step. To maintain compatibility this means that thesources must beinterpolated and extrapolated for half time step points, which can produce significant

errors if the sources are changing abruptly. Figure 9.13 illustrates this problem with

a step input.

Step 1 is a normal step from t+t to t+ 2t, where the user-defined dynamic fileis called to update source values at t+ 2t.

Step 2, a half-step interpolation, is performed by the chatter removal algorithm. As

the user-defined dynamic file is called only at increments the source value at

t+

t/2 has to be interpolated.

Step 3 is a normal time step (from t+t/2 to t+ 3t/2) using the trapezoidal rule.This requires thesourcevalues at t+3t/2, which is obtainedby extrapolationfrom the known values at t+t to t+ 2t.

Step 4 is another half time step interpolation to get back to t+ 2t.

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t

t+t

t+t

t+ 2t

t+ 2t

1

2

3

tZ

t

t

4

5

1

2

3

45

1 Interpolate to zero crossing

2 Normal step forward

3 Interpolate half time step backward

4 Normal step forward

5 Interpolate on to original time grid

i (t)

v (t)

t

Figure 9.12 Combined zero-crossing and chatter removal by interpolation

The purpose of the methods usedso far is toovercome the problem associatedwith

the numerical error in the trapezoidal rule (or any integration rule for that matter).

A better approach is to replace numerical integrator substitution by root-matching

modelling techniques. As shown in Chapter 5, the root-matching technique does not

exhibit chatter, and so a removal process is not required for these components. Root-

matching is always numerically stable and is more efficient numerically than trape-

zoidal integration. Root-matching can only be formulated with branches containing

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t

Input

t

1

2

4

3

Step input

User

dynamics file

called

User

dynamics file

called

t+t t+ 2t t+ 3t

t+ 3t/2

t+t/2

Interpolated

source values

Extrapolated

source values

Figure 9.13 Interpolated/extrapolated source values due to chatter removal

algorithm

two or more elements (i.e. RL, RC , RLC , LC,. . .) but these branches can be inter-

mixed in the same solution with branches solved with other integration techniques.

9.5 HVDC converters

PSCAD/EMTDC provides as a single component a six-pulse valve group, shown

in Figure 9.14(a), with its associate PLO (Phase Locked Oscillator) firing controland sequencing logic. Each valve is modelled as an off/on resistance, with forward

voltagedrop andparallel snubber, as shown in Figure9.14(b). Thecombination of on-

resistance and forward-voltage drop can be viewed as a two-piece linear approxima-

tion to the conduction characteristic. The interpolated switching scheme, described

in section 9.4.1 (Figure 9.10), is used for each valve.

The LDU factorisation scheme used in EMTDC is optimised for the type of

conductance matrix found in power systems in the presence of frequently switched

elements. The block diagonal structure of the conductance matrix, caused by a

travelling-wave transmission line and cable models, is exploited by processing each

associated subsystem separately and sequentially. Within each subsystem, nodes to

which frequently switched elements are attached are ordered last, so that the matrix

refactorisation after switching need only proceed from the switched node to the end.

Nodes involving circuit breakers and faults are not ordered last, however, since they

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Ron Cd

Rd

Roff

Efwd

1 3 5

4 6 2

(a) (b)

abc

+

Figure 9.14 (a) The six-pulse group converter, (b) thyristor and snubber equivalentcircuit

V

Vcos

Vsin

VA

0

1.20

0.80GI

1.0

Reset

at 2

+

++

2 ph

3 ph

VB

VC

Vb

+

+

X

X

S

S

GP

Figure 9.15 Phase-vector phase-locked oscillator

switch only once or twice in the course of a simulation. This means that the matrix

refactorisation time is affected mainly by the total number of switched elements in asubsystem, and not by the total sizeof the subsystem. Sparse matrix indexing methods

are used to process only the non-zero elements in each subsystem. A further speed

improvement, and reduction in algorithmic complexity, are achieved by storing the

conductancematrix for each subsystemin full form, including thezero elements. This

avoids the need for indirect indexing of the conductance matrix elements by means

of pointers.

Although the user has the option of building up a valve group from individual

thyristor components, the use of the complete valve group including sequencing and

firing control logic is a better proposition.

The firing controller implemented is of the phase-vector type, shown in

Figure 9.15, which employs trigonometric identities to operate on an error signal

following the phase of the positive sequence component of the commutating voltage.

The output of the PLO is a ramp, phase shifted to account for the transformer phase

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Interpolated firing

of valve 1

Interpolated firing

of valve 2

Valve

1ram

p

Valve

2ram

p

Valve

3ram

pFiring order

t

Figure 9.16 Firing control for the PSCAD/EMTDC valve group model

minmin

at min

Current order

Current margin

Current errorcharacteristic

Normal operating point

IR drop in d.c. line

Inverter characteristic at

limit

Rectifier characteristic

Figure 9.17 Classic VI converter control characteristic

shift. A firing occurs for valve 1 when the ramp intersects the instantaneous value of

the alpha order from the link controller. Ramps for the other five valves are obtained

by adding increments of 60 degrees to the valve 1 ramp. This process is illustrated in

Figure 9.16.

As for the six-pulse valve group, where the user has the option of constructing it

from discrete component models, HVDC link controls can be modelled by synthesis

from simple control blocks or from specific HVDC control blocks. The d.c. link

controls provided are a gamma or extinction angle control and current control with

voltage-dependent current limits. Power control must be implemented from general-

purpose control blocks. The general extinction angle and current controllers provided

with PSCAD readily enable the implementation of the classic VI characteristic for

a d.c. link, illustrated in Figure 9.17.

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General controller modelling is made possible by the provision of a large number

of control building blocks including integrators with limits, real pole, PI control,

second-order complex pole, differential pole, derivative block, delay, limit, timer

and ramp. The control blocks are interfaced to the electrical circuit by a variety of

metering components and controlled sources.

A comprehensive report on the control arrangements, strategies and parameters

used in existing HVDC schemes has been prepared by CIGRE WG 14-02 [10]. All

these facilities can easily be represented in electromagnetic transient programs.

9.6 Example of HVDC simulation

A useful test system for the simulation of a complete d.c. link is the CIGRE

benchmark model [10] (described in Appendix D). This model integrates simple

a.c. and d.c. systems, filters, link control, bridge models and a linear transformer

model. The benchmark system was entered using the PSCAD/draft software pack-

age, as illustrated in Figure 9.18. The controller modelled in Figure 9.19 is of the

proportional/integral type in both current and extinction angle control.

The test system was first simulated for 1 s to achieve the steady state, whereupon

a snapshot was taken of the system state. Figure 9.20 illustrates selected waveforms

of the response to a five-cycle three-phase fault applied to the inverter commutating

bus. The simulation was started from the snapshot taken at the one second point.

A clear advantage of starting from snapshots is that many transient simulations, forthe purpose of control design, can be initiated from the same steady-state condition.

9.7 FACTS devices

The simulation techniques developed for HVDC systems are also suitable for the

FACTS technology. Two approaches are currently used to that effect: the FACTS

devices are either modelled from a synthesis of individual power electronic compo-

nents or by developing a unified model of the complete FACTS device. The formermethod entails the connection of thyristors or GTOs, phase-locked loop, firing con-

troller and control circuitry into a complicated simulation. By grouping electrical

components and firing control into a single model, the latter method is more efficient,

simpler to use, and more versatile. Two examples of FACTS applications, using

thyristor and turn-off switching devices, are described next.

9.7.1 The static VAr compensator

An early FACTS device, based on conventional thyristor switching technology, is

the SVC (Static Var Compensator), consisting of thyristor switched capacitor (TSC)

banks and a thyristor controlled reactor (TCR). In terms of modelling, the TCR

is the FACTS technology more similar to the six-pulse thyristor bridge. The firing

instants are determined by a firing controller acting in accordance with a delay angle

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1.0E6

0.4

97333

2.5

1.0E6

0.4

97333

2.5

21.66667

KB

ARS GRS

ARD GRD

DCRC

DCMP

DCIC

DCIMP

DCRMP

NAR

NBR

NCR

AMISAMID

A

B

C

A

B

C

A

B

C

A

B

C

CMR

C

MI

MPV

VDCRC

VDCIC

NAI

NBI

NCI

CM

IX

CM

RX

MPVX

CMI

CMR

MPV

VRC

VRB

VRA

VRA

VRB

VRC

A B C

AM

GM K

B

Com

Bus

AO

1

3

5

4

6

2

A B C

AM

GM K

B

Com

Bus

AO

1

3

5

4

6

2

A B C

Com

Bus 4

6

2

1

3

5

A B C

Com

Bus

4

6

2

1

3

5

TIME

GMES

GMID

GMIS

Min

DE

A B C

Tmva=

603

.73

345

.0213

.4557

#1

#2

A B C

A B C

Tmva=

603

.73

345

.0213

.4557

#1

#2

A B C

A B C

Tmva=

591

.79

230

.0

209

.2288

#1

#2

A B C

A B C

Tmva=

591

.79

230

.0

209

.2288

#1

#2

1.0

1.0

1.0

1.0

1.0

1.0

3.737

3.737

3.737

A

B

C

0.7406

0.74060.0365

0.0365

24.81

24.81

24.81

0.0365

0.0365

0.0365

0.74060.0365

A

B

C

74.286.685

74.28

261.87

6.685

15.04

15.04

15.04

74.286.685

1.671

3.342

3.342

FAULTS

LOGIC

FAULT

TIMED

VDCIC

VDCRC

IR1A

IR1B

IR1C

CBA

IR1C

IR1B

IR1A 6.685

6.685

6.685

83.32

0.0136

83.32

0.0136

0.0136

83.32

.1364

261.87

.1364

261.87

.1364

29.76

29.76

29.76

0.151

2160.633

0.151

2160.633

0.151

2160.633

0.7406

0.7406

0.7406

167.213.23

167.213.23

167.213.23

116.38

116.38

116.38

0.0606

0.0606

0.0606

37.03

0.0061

37.03

0.0061

37.03

0.0061

15.04

15.04

15.04

7.522

7.522

7.522

ABC

KB

AO

AM

GM

AM

GM

KB

AO

AOR

AOI

Figure 9.18 CIGRE benchmark model as entered into the PSCAD draft software

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CMRX

CMIX

MPVX

GMES

Minin

1Cycle

0.1

3.1

41590

0.26180

AOR

AOI

CMRS

CMIS

CORD

CERRI

CERRR

CMARG

CERRIM

CNLG

VDCL

MPVS

GMESS

DGEI

GMIN

GERRI

GNLG

BETAIG

BETAIC

BETAR

BETARL

PI

BETAI

G1+sT

G1+sT

G1+sT

Max

DE

D

F+

D

F+

B

D

+

F

B +

D

F+

D

F+

D

F+

IP IP

IP

TIME

Arc

Cos

D

F+

Arc

Cos

Lineariser

1.0

*0.6

36

61977

Figure 9.19 Controller for the PSCAD/EMTDC simulation of the CIGRE bench-mark model

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p

.u.

degs

Alpha order @ rectifier Alpha order @ inverterr

p.u.

p.u.

0

0.5

1

1.5

2

0

3060

90

120

150

1.2

0.8

0.4

0

0.4

0.8

1.2

0

0.5

1

1.5

2

2.5

Rectifier measured current

Inverter phase A Volts

Time (s)

Inverter measured current

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Figure 9.20 Response of the CIGRE model to five-cycle three-phase fault at theinverter bus

passed from an external controller. The end of conduction of a thyristor is unknown

beforehand, and can be viewed as a similar process to the commutation in a six-pulse

converter bridge.

PSCAD contains an in-built SVC model which employs the state variable formu-

lation (but not state variable analysis) [3]. The circuit, illustrated in Figure 9.21,

encompasses the electrical components of a twelve-pulse TCR, phase-shifting

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Vp1 Vp2 Vp3

Ip2 Ip3Ip1

Is1

IL1 Cs

C1

T1

T3

T6

T2 T

4

T5

Rs

Is6 Is5

Is4

TCR

TSC

L/2 L/2

Neutral

Figure 9.21 SVC circuit diagram

transformer banks and up to ten TSC banks. Signals to add or removea TSC bank, and

the TCRfiring delay, must be provided from the external general-purpose control sys-

tem component models. The SVC model includes a phase-locked oscillator and firing

controller model. The TSC bank is represented by a single capacitor, and when a bank

is switched the capacitance value and initial voltage are adjusted accordingly. This

simplification requires that the current-limiting inductor in series with each capacitor

should not be explicitly represented. RC snubbers are included with each thyristor.

The SVC transformer is modelled as nine mutually coupled windings on a com-

mon core, and saturation is represented by an additional current injection obtained

from a flux/magnetising current relationship. The flux is determined by integration

of the terminal voltage.

A total of 21 state variables are required to represent the circuit of Figure 9.21.

These are the three currents in the delta-connected SVC secondary winding, two of

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tx

IL

t

tB

Dt

tA1

Symbol Description

t

Dt

t

Original EMTDC time step

SVC time step

Catch-up time step

t t t

t

Switch-OFF

occurs

Time

tAtA2 tA3

Figure 9.22 Thyristor switch-OFF with variable time step

the currents in the ungrounded star-connected secondary, two capacitor voltages in

each of the two delta-connected TSCs (four variables) and the capacitor voltage on

each of the back-to-back thyristor snubbers (4 3 = 12 state variables).The system matrix must be reformed whenever a thyristor switches. Accurate

determination of the switching instants is obtained by employing an integration step

length which is a submultiple of that employed in the EMTDC main loop. The detec-

tion of switchings proceeds as in Figure 9.22. Initially the step length is the same asthat employed in EMTDC. Upon satisfying an inequality that indicates that a switch-

ing has occurred, the SVC model steps back a time step and integrates with a smaller

time step, until the inequality is satisfied again. At this point the switching is brack-

eted by a smaller interval, and the system matrix for the SVC is reformed with the

new topology. A catch-up step is then taken to resynchronise the SVC model with

EMTDC, and the step length is increased back to the original.

The interface between the EMTDC and SVC models is by Norton and Thevenin

equivalents as shown in Figure 9.23. The EMTDC network sees the SVC as a cur-

rent source in parallel with a linearising resistance Rc. The linearising resistance is

necessary, since the SVC current injection is calculated by the model on the basis of

the terminal voltage at the previous time step. Rc is then an approximation to how

the SVC current injection will vary as a function of the terminal voltage value to be

calculated at the current time step. The total current flowing in this resistance may be

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RC

RC

RC

V

ISVC (t)VC (tt)

V(t)

Outside

network

EMTDC networkSVC model

Figure 9.23 Interfacing between the SVC model and the EMTDC program

large, and unrelated to the absolute value of current flowing into the SVC. A correc-

tion offset current is therefore added to the SVC Norton current source to compensate

for the current flowing in the linearising resistor. This current is calculated using the

terminal voltage from the previous time step. The overall effect is that Rc acts as a

linearising incremental resistance. Because of this Norton source compensation for

Rc, its value need not be particularly accurate, and the transformer zero sequence

leakage reactance is used.

The EMTDC systemis represented in the SVC model by a time-dependent source,

for example the phase A voltage is calculated as

Va = Va + t(Vc Vb)1 (t)2

3(9.11)

which has the effect of reducing errors due to the one time-step delay between the

SVC model and EMTDC.

The firing control of the SVC model is very similar to that implemented in the

HVDC six-pulse bridge model. A firing occurs when the elapsed angle derived from aPLO ramp is equal to the instantaneous firing-angle order obtained from the external

controller model. The phase locked oscillator is of the phase-vector type illustrated

in Figure 9.15. The three-phase to two-phase dq transformation is defined by

V =

2

3

Va

1

3

Vb

1

3

Vc (9.12)

V =

13

(Vb Vc) (9.13)

The SVC controller is implemented using general-purpose control components,

an example being that of Figure 9.24. This controller is based on that installed at

Chateauguay [11]. The signals Ia , Ib, Ic and Va , Vb, Vc are instantaneous current

and voltage at the SVC terminals. These are processed to yield the reactive power

EMTP simul(19)

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