ELX304 Electronic System Design

University of Sunderland

Faculty of Applied Sciences

Department of Computing, Engineering & Technology

ELX304 – Electronic System Design

EXAMINATION

Date: Wednesday 7th September 2011 Time: 9.30-12.30

Instructions to Candidates:

Time allowed - 3 hours

There are 6 questions set. You must attempt 4 questions.

This is a closed book examination – this means you are not permitted to use any text books or study aids in the examination.

You are forbidden to use programmable calculators or dictionaries.

You must answer the required number of questions only. Any additional answers will not be marked.

You should put a cross through any work you do not wish to be marked.

The following examination aids are provided :

- Linear graph paperQ1 Figure Q1 shows the state flow diagram of a synchronous circuit to detect the pattern 1101 in serial clocked data (X). The end of the

sequence can form the beginning of the next sequence and once the pattern is recognized then the output (Z) is immediately set high and held for one clock pulse.

1

1A0

B0

0 C0

1 D1

0

0

E0

0

1

01

ELX304 Electronic System Design

Figure Q1 : Synchronous Pattern Detector

a) Develop its minimized state output table. Should any merges occur remove the alphabetically higher ordered term (i.e if A and B merge replace all ‘B’ terms with ‘A’) (5

marks)

b) State the design rules and indicate which ones are not satisfied by the following assignment :

(5 marks)

c) Develop a J-K flip-flop solution to the problem using theassignment provided in Q1b above. You need not sketch the final design. (10

marks)

d) Using the above state flow diagram sketch how it could be modified to hold the output for two clock pulses when thesequence is detected. (5

marks)Q2 The following state flow diagram is a model of a control system for the robot shown. The circuit inputs are the proximity sensor outputs (S1S2) which are a logic high when an obstacle is detected. The outputs (Z1Z2) are the forward drive signals to the robot’s motors where a logic high represents ‘drive’ and a logic low ‘brake’.

B

-

A C E

10

--D

110100

0

1

Q1Q2

Q3

01,11

10

10

10

11

00

00

01

01 00

B01

C11

D10

A11

00 10

S1 S2

Z1 Z2

Robot (viewed from above)

ELX304 Electronic System Design

a) Identify any operational limitations that are present in the solution shown in figure Q1. (2

marks)

b) An Asynchronous solution to the above problem is to be designed :

i) Obtain its State output table, assuming outputs need only be assigned to stable states for now. (2

marks)

ii) Use an implication table to show that its minimised state output table contains only a single state and from this identify the Boolean logic expressions for the motor drives Z1 and Z2. (6

marks)

c) A new robot control scheme is proposed which has only a single proximity sensor (S) at the front of the robot and avoids an obstacle by continuing to rotate in the same direction until the sensor signal is lost. If the control strategy is to alternate this rotational direction in the sequence left-right-left-right etc…, develop a minimal race-free asynchronous solution. (15

marks)Q3

a) The basic building block of all numeric devices is the full adder. Design the logic required to implement it. (5

marks)

b) The following circuit shows the NAND implementation of an EX-OR gate :

A

B

Z

ELX304 Electronic System Design

i) Show that Z = A B (4 marks)

ii) Show how the sum bit of a full adder can be implemented using EX-OR gates. (2

marks)

iii) Develop a NAND implementation of the carrybit of a full adder. (4

marks)

c) Full adders can be used to implement multi-bit adders.

i) Show the construction of a 4-bit adder (2 marks)

ii) What is the main problem with such implementation’sand discuss one method of improving things? (3

marks)

iii) Describe how multiplication is performed and therefore identify what hardware would need to be added to convert the 4-bit adder into a multiplier of unsigned 4-bit binary numbers. (5

marks)

ELX304 Electronic System Design

Q4 For the logic function

a) Show how the function may be implemented using :

i) NMOS with active depletion transistor pull-up (3 marks)

ii) NMOS in a programmed transistor array (4 marks)

iii) CMOS technology (3 marks)

b) Develop a Shannon’s expansion theorem form of the logic function and sketch its implementation upon a CMOS semi-custom (Double Rail MPGA) design cell. (10

marks)

c) For the CMOS logic array cell shown in figure Q4 sketch :

i) the transistor layout of the cell (3 marks)

ii) If the cell is programmed using metal links what wouldthe minimum size of the contact areas be if MOSISdesign rules were used (2

marks)

Figure Q4 : CMOS Logic Array

Polysilicon

N-channel

P-channelZ1 Z2

Z3 Z4

F1

F2

X1 X2

ELX304 Electronic System Design

Q5 For the CMOS gate shown in Figure Q5 :

a) Sketch the circuit and determine the logic produced (6 marks)

b) Use the MOSIS design rules shown in Table Q5 to determine the height of the cell shown in Figure Q5 assuming that the aspect

ratio of the NMOS gates is 1:1 and the PMOS gates 1:2. Clearly label the rules employed in coming to your solution on the attached

solution page at the back of the examination paper. (12 marks)

c) Why is the aspect ratio of the PMOS gates half thatof the NMOS gates ? (2

marks)

d) Describe the relationship between feature size and the MOSIS design rules and explain what the limitations are to its future reduction. (5 marks)

Figure Q5 : CMOS P-Well Gate

Rules Scale1. P-well

1. Width 4 2. Spacing (Different potential) 10

Metal N-Moat Polysilicon P-Moat

Vdd

Gnd

P-Well

Z

AB

ELX304 Electronic System Design

3. Spacing (Same potential) 6

2. Active1. Width 2 2. Spacing 2 3. P+ active in n-subs to p-well

edge6

4. n+ active in n-subs to p-well edge

5

5. n+ active in p-well to p-well edge

2

6. P+ active in p-well to p-well edge

3. Poly1. Width 2 2. Spacing 2 3. Field Poly to active 4. Poly overlap of active 2 5. Active overlap of Poly 2

4. Contact1. Square contact, exactly 2 * 22. Rectangular contact, exactly 2 * 6 3. Space to different contact 2 4. Poly overplay of contact 5. Space to channel 2 6. Metal overlap of contact 7. Active overlap of contact 8. N+ select overlap of contact 2 9. Subs/well shorting contact,

exactly2 * 6

5. Metal1. Width 2 2. Spacing 3

Table Q5 : CMOS - MOSIS Design Rules (Single Metal P-Well process)Q6

a) The nature of NMOS/CMOS construction lends itself readily to the construction of parallel plate capacitors.

i) Why is this a problem? (2 marks)

ELX304 Electronic System Design

ii) Why are capacitors often used in analogue circuit construction rather than resistors? (2

marks)

b) Single mask capacitors are constructed using ‘ink’ technology in the form shown below :

i) Use the formula for a parallel plate capacitor :

shown above to derive (ignoring fringing affects) an expression for its sheet capacitance, CS .

You are given that (4 marks)

ii) Using the MOSIS design rules of Table Q5 for polysilicon show that under minimum dimensions W = WX . (3

marks)

iii) Why is this method of capacitor construction more accurate than standard multi-mask methods? (1

mark)

Q6 continued overleaf

WX

H

LD

WW

fluxx

ELX304 Electronic System Design

Q6 Continued

c) The above theory shows that the capacitance of single mask devices is proportional to the mean path length, LD. One efficient layout of such devices is the inter-digitated capacitor shown below :

i) Assuming that W = Wx show that the mean internal path length (of the flux) between the two film deposits is :

Where N is the total number fingers, of length Lf, on both film deposits (N = 4 shown) (7

marks)

ii) Why is the above relationship only an approximation? (2 marks)

iii) Sketch the structure of an inter-digitated capacitor where N = 3 and Lf = 4W and evaluate its mean path length and overall dimensions (in terms of W). (4

marks)

Page for Submission of Q5 Solution( If used please remove and attach securely to exam booklet )

Metal N-Moat Polysilicon P-Moat

Vdd

Gnd

P-Well

Z

AB

Lf

W

Wx

Wx

Lf