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Bansilal Ramnath Agarwal Charitable Trust’s Vishwakarma Institute of Technology, Pune – 411 037 Department of Electronics Engineering Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 1 Bansilal Ramnath Agarwal Charitable Trust’s Vishwakarma Institute of Technology (An Autonomous Institute affiliated to University of Pune) Structure & Syllabus of B.E. (Electronics) Pattern ‘D11’ Effective from Academic Year 2011-12 Prepared by: - Board of Studies in Mechanical Engineering Approved by: - Academic Board, Vishwakarma Institute of Technology, Pune Signed by, Chairman – BOS Chairman – Academic Board

Transcript of elexd11m8(1)

Page 1: elexd11m8(1)

Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 1

Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology (An Autonomous Institute affiliated to University of Pune)

Structure & Syllabus of

B.E. (Electronics) Pattern ‘D11’

Effective from Academic Year 2011-12 Prepared by: - Board of Studies in Mechanical Engineering

Approved by: - Academic Board, Vishwakarma Institute of Technology, Pune

Signed by,

Chairman – BOS Chairman – Academic Board

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 2

Content Sr. No Title Page No.

1 Program Educational Objectives 4

2 Module VII 5

3 Course Structure 6

4 Course Syllabi for courses - Module VII

Theory Course

4.1 EC40106 Embedded System Design 8 4.2 EC40107 VLSI Design 10 Elective I 12 4.3 EC42115 Wireless Communication 13 4.4 EC42116 Artificial Intelligence 15 4.5 EC42117 Biomedical Electronics 17 Elective II 19 4.6 EC42118 Mobile Computing* 20 4.7 EC42119 Advanced Digital Signal Processing** 22 4.8 EC42120 CMOS Analog and Digital Design*** 24 Tutorial 4.9 EC40205 Embedded System Design 26 Elective I 4.10 EC42209 Wireless Communication 27 4.11 EC42210 Artificial Intelligence 28 4.12 EC42211 Biomedical Electronics 29 Laboratory 4.13 EC40302 VLSI Design 30 Laboratory - Elective II 4.14 EC42307 Mobile Computing* 31 4.15 EC42308 Advanced Digital Signal Processing** 32 4.16 EC42309 CMOS Analog and Digital Design*** 33 Project and Seminar 4.17 EC47305 Seminar 34 4.18 EC47303 Project Stage-I 35 Module VIII 36

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 3

5 Course Syllabi for courses - Module VIII 37

6 Theory Course

6.1 EC41102 Electronic Automation (MD) 39 6.2 EC40108 Electronic System Design and Modeling 41 Elective III 43 6.3 EC42121 Audio Video Engineering 44 6.4 EC42122 Advanced Power Electronics 46 6.5 EC42123 Machine Vision 48 Elective IV (Module) 50 6.6 EC42124 Telecommunication Network Management * 51 6.7 EC42125 Digital Image Processing** 53 6.8 EC42126 VLSI System Design*** 55 Tutorial 6.9 EC41201 Electronic Automation (MD) 57 Tutorial Elective III 6.10 EC42212 Audio Video Engineering 58 6.11 EC42213 Advanced Power Electronics 59 6.12 EC42214 Machine Vision 60 Laboratory 6.13 EC40303 Electronic System Design and Modeling 61 6.14 EC42310 Telecommunication Network Management * 62 6.15 EC42311 Digital Image Processing** 63 6.16 EC42312 VLSI System Design*** 64 Project and Seminar 6.17 EC47304 Project Stage-II 657 ACADEMIC INFORMATION 66

* Only for communication Module

** Only for Signal Processing Module

*** Only for Microelectronics Module.

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 4

Program Educational Objectives (PEO)

(Electronics Engineering)

PEO No. Description of the Objective

1 Apply knowledge in Mathematics, Science and Engineering to solve

Electronics Engineering problems.

2 Ability to analyze and interpret data out of experimental findings.

3 Ability to understand professional & ethical responsibilities and

preparation to be a part of multidisciplinary team.

4 Ability to communicate effectively.

5 Knowledge of contemporary issues.

6 Ability to use the techniques, skills and modern Engineering tools

necessary for Engineering practice.

7 Provide students with a solid foundation in Electronics Engineering,

preparing them for career and professional growth.

8 To provide Engineering design experience, enabling students to explore

relationship between theory and practices.

9 Challenge traditional thinking and invent new approaches to solve

technical problems.

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 36

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 37

BE MODULE VIII

Structure, B.E. (Module VIII) FF653, Issue No. 3, Rev 1, dt 02/04/2011 Subject

No.

Subject Code

Subject Name Teaching Scheme (Hrs/week) Credits

Lect. Tutorial Practical

S5 EC41102 Electronic Automation (MD)

3 0 0 3

S6 EC40108 Electronic System Design and Modeling 3 0 0 3

S7 EC421XX Elective III 3 0 0 3

S8 EC421XX Elective IV (Module 3 0 0 3

T3 EC41201 Electronic Automation (MD) 0 1 0 1

T4 EC422XX Elective III 0 1 0 1 P3 EC40303 Electronic System Design and Modeling 0 0 2 1 P4 EC423XX Elective IV (Module) 0 0 2 1

PS3 EC47304 Project Stage-II 0 0 8 6

Total 12 2 12 22

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 38

List of Elective3

Subject

No. Subject Name Subject Code Teaching Scheme (Hrs. per week) Credits

Lecture Tutorial Practical S6 Audio Video

Engineering EC42121 3 0 0 3

S6 Advanced Power Electronics

EC42122 3 0 0 3

S6 Machine Vision EC42123 3 0 0 3 T4 Audio Video

Engineering EC42212 0 1 0 1

T4 Advanced Power Electronics

EC42213 0 1 0 1

T4 Machine Vision EC42214 0 1 0 1

List of Elective 4

Subject No.

Subject Name Subject Code Teaching Scheme (Hrs. per week) Credits Lecture Tutorial Practical

S8 Telecommunication Network Management

*

EC42124 3 0 0 3

S8 Digital Image Processing**

EC42125 3 0 0 3

S8 VLSI System Design***

EC42126 3 0 0 3

P4 Telecommunication Network Management

*

EC42310 0 0 2 1

P4 Digital Image Processing**

EC42311 0 0 2 1

P4 VLSI System Design***

EC42312 0 0 2 1

* Only for Communication module

** Only for Signal Processing module

*** Only for Microelectronics module

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 39

FF No. : 654

Credits: 03 Teaching Scheme: - Theory 3 Hrs/Week Prerequisites: Basics of control system, Op-Amp, and PLC

Objectives: To understand - Hierarchy of automation - Automation tools - Controller principles - Mapping with PEO : 1,2,3,6,7,8,9

Unit I

(6 Hrs)

Unit Name: Introduction to Industrial Automation

A. Introduction and Architecture of automation, Types, pyramid of automation, advantages and disadvantages, Advanced functions, Approach to automation, Manual labor, and control levels.

B. Industrial Safety legislations and regulations, Safety by design.

Unit II

(8 Hrs)

Unit Name: Automation Tools

A. PLC- Architecture, Justification for use of PLC, Communication networking of PLC, Ladder programming. HMI- Functions, alarming modes, type of display-graphic, trend, group, detail. DCCS-advantages of decentralized control system, architecture, hierarchy, SCADA- Architecture, functions of key elements of SCADA, applications. B. Intelligent sensors in industrial and process automation, MEMS. Communication networking protocols in automation. Unit III (10 Hrs)Unit Name: Controller Principles

A. Control system parameters, on-off, two position, and multi-position controllers, Proportional, Derivative, and Integral controllers, PI, PD, PID controllers, analog representation of composite controller, Stability concepts, Controller tuning, Controller

EC 41102::Electronic Automation

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 40

configurations, Fuzzy controller in control applications- concepts, membership functions, fuzzy inference, defuzzfication methods, Fuzzy controller in automation. B. Interacting and non-interacting PID controller. Unit IV (8 Hrs)Unit Name: Digital Controllers

A. Introduction of digital controllers, Models of A/D and D/A converters, Types of digital controller- recursive, non-recursive, Realization of digital PID controller- digital temperature control system, non-interacting velocity algorithm, digital position control system. B. Study of Model based controller, adaptive controller

Unit V (8 Hrs)Unit Name: Automation Applications

A. Building automation system- Building management system, HVAC control, wireless networking, Building control network. Railway signaling- Detection of trains, need of signaling, release of locking, Implementation of railway signaling, PES in railway signaling. High speed rail signaling system, Automotive Electronics- navigation/driver guide system, ECU, vehicle communication standards, safety. B. Networking protocols in BAS and vehicles. Outcome: Students will be able to

- Design controller for automation application - Design industrial automation system

Text Books

1. C. D. Johnson - Process Control Instrumentation 2. M. Gopal - Digital Control and state variable methods

Reference Books

1. Ogata - Modern Control Systems 2. Bela Liptak -Handbook of Process Control

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 41

FF No. : 654

Credits: 03 Teaching Scheme: - Theory 3 Hrs/Week Prerequisites: Students having basic knowledge of analog & digital electronics Objectives: To understand

• Important considerations in developing a particular electronic product. • Modeling – Hardware & software • Integration of hardware & software • Mapping with PEO : 2,3,6,7,8,9

Unit I (8 Hrs) Analysis Of Electronics System

A. Product development stages & constraints. System specifications. Study of techno-commercial feasibility of specifications. Functional requirements, Environmental constraints. Ergonomic & aesthetic design considerations. Thermal management, Enclosure design B. Commercial, industrial & military standards;

Unit II

(8 Hrs)

Hardware Modeling

A. Modeling of switching power device, analog device, small signal amplifier, digital device, gates, current swings, charging-discharging constraints, timing issues in hardware circuits, voltage swing analysis, noise consideration while modeling.

B. modeling of an op-amp Unit III (8 Hrs)Noise

A. Noise & Interference, noise reduction & interference eliminating methods, grounding & shielding techniques, ground loops; EMI, EMC, ESD concepts.

B. Design rules for analog & digital PCBs.

EC 40108 :: ELECTRONICS SYSTEM DESIGN & MODELING

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 42

Unit IV (8 Hrs)Reliability

A. Introduction, Considerations, reliability & quality, definition & related terms like MTBF, MTTR etc. availability, maintainability, bath tub curve, assessment of reliability, reliability expression, fail safe & redundancy techniques, concepts of failure analysis, System reliability improvement. B. repairable & non-repairable systems

Unit V (8 Hrs)Software – Hardware Integration

A. Object oriented design, software design methodology, Design information flow, Entity relationship diagram, Design process considerations, data flow diagram, control flow diagram. Verification techniques, testing at block diagram level, circuit level, selection of components, ICs, cost estimation

B. PCB layout, PCB designing issues & constraints, operating instructions. Case studies.

Text Books 1. Henry Ott ,Noise reduction techniques in electronics circuits:, Wiley 2. E. Balguruswamy , Reliability Engineering: 3. Roger S. Pressman, Software Engineering:, McGraw Hill 4. Kim Fowler, Electronics Instrument Design, Oxford

Reference Books 1. Paul Horowitz. Hill , The Art of Electronics:, Cambridge 2. E F.F.Mazda , Electronics Engineers Reference Book, Butterworth Publication

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 43

List of Elective3

Sr. No. Subject Name Subject Code

01 Audio Video Engineering EC42121 02 Advanced Power Electronics EC42122 03 Machine Vision EC42123

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 44

FF No. : 654

Credits: 03 Teaching Scheme: - Theory 3 Hrs/Week Prerequisites: Communication Engineering & Digital Communication.

Objectives: To study

• Concepts of Color Television (CTV) Transmitter and Receiver.

• Working Principle of Digital Television (DTV) and High Definition Television (HDTV).

• Compression Techniques.

• Direct to Home (DTH) Receiver, Digital Video Disc (DVD) player, Digital Satellite Radio (DSR).

• Mapping with PEO : 1,2,5,6,7,8,9

Unit I (6 Hrs)

Unit Name : Basics of Television

A) Scanning process, Composite Video Signal, Horizontal Blank and Sync standard, Vertical Blank and Sync standard, Vestigial Sideband Transmission, TV Channels and Bands, CCIR-B standards, Negative modulation, Inter-carrier Sound System.

B) Construction & working principle of CCD camera. Unit II (7 Hrs)Unit Name : TV Transmission and Reception

A) High Level modulated TV Transmitter , IF modulated TV Transmitter, Transmitting Antenna, Receiving Yagi Antenna, Block Diagram of Monochrome Receiver, Pattern Generator, Wobbuloscope .

B) Basic satellite theory ( Transponder), Cathode Ray Tube.

Unit III (9 Hrs)Unit Name : Color TV Systems

EC42121:: AUDIO VIDEO ENGINEERING

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 45

A) Color fundamentals, Mixing of colors, Color perception, Color Characteristics, Chromaticity diagram, Color TV camera, Frequency Interleaving Principle, Color Bandwidth, Chroma Signal Generation, Color Burst, Simple PAL & PAL-D System, PAL Encoder, PAL Decoder, CTV Receiver Block Diagram, Monochrome and Color Picture Tubes, NTSC, PAL, SECAM systems.

B) Chromaticity diagram, SAW filter. Unit IV (9 Hrs)Unit Name : Digital Television

A) Merits of DTV, Digitization formats, Source Coding : Compression of Video Signal (JPEG&MPEG), Scrambling and Conditional Access, Channel Coding, Modulation by Digital Signal, Reception of Digital TV Signal, Digital TV Receiver block diagram, LCD and Plasma Displays, Types of digital TV ( SDTV, EDTV, HDTV), DTH system.

B) Closed Circuit Television (CCTV), Cable Television (CATV).

Unit V (9 Hrs)Unit Name : Recording And Reproduction

A) A. Principle of MPEG Audio compression, MPEG audio layer III ( MPIII

format), MPEG-1 audio encoder & decoder, Methods of Recording and

Reproduction : Magnetic Recording, Optical Recording, CD/DVD/MP3 Player,

Digital Satellite Radio.

B) Construction & working principle of camcorder.

Text Books 1. R.R.Gulathi, “Monochrome & color television”, New Age International. 2. Herve Benoit, “Digital Television”, Focal Press.

Reference Books 1. Bernard Grobb & Charles E., “Basic TV and Video Systems”, McGraw Hill. 2. Ranjan Parekh, “ Principles of multimedia”, Tata Mc-GrawHill 3. R.G. Gupta, “Audio Video Systems”, Technical Education.

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 46

FF No. : 654

Credits: 03 Teaching Scheme: - Theory 3 Hrs/Week Prerequisites: Basics of Power devices, Basics of Power Conversion systems,

Basics of AC/DC Motors, Fourier series for analytical approach Objectives:

• To explain the necessity of power factor improvement & techniques. • To study the use of converters & inverters for speed control of motors. • To study harmonic control techniques in power conversion. • To discuss various measurement techniques in power electronics. • Mapping with PEO : 1,2,3,6,7,8,9

Unit I (8 Hrs) 3 Phase AC/DC Converters

A. Operation and Analysis of 3 phase Semi/ Full Converter with R and R-L load, Effect of Source Impedance(Ls) on Single phase converter, Single phase and Three Phase Dual Converters (Ideal and Practical), Control schemes for non circulating type dual converter, Analysis of circulating current type dual converter. B. Calculation of converter output with Ls, Microprocessor based firing scheme for dual Converter converter. Unit II (8 Hrs)

3 Phase Inverters

A. 3 Phase Transistorized Voltage Source Inverter(VSI)- 120° and 180° mode of operation and analysis, PWM Inverters- Techniques and comparison, Voltage Control and Harmonic Reduction in inverters, Introduction to Current Source Inverter. B. Space Vector Modulation, Multilevel inverters

Unit III (8 Hrs)PF Improvement and Instrumentation

A. Series and Parallel Operation of Power Devices- String Efficiency, Derating, Triggering requirements, Need of equalizing Network. Power Factor Improvement Techniques-PAC, Forced Commutation (SAC, EAC), Sequence Control of Series Connected Converters.Sensing and measurement of Sinusoidal and non-sinusoidal Voltage and Current, Speed, Power Factor etc.

EC42122:: ADVANCED POWER ELECTRONICS

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 47

B. Protection and Cooling of power switching devices Unit IV (8 Hrs)DC Motor Drives

A. Motor Performance Parameters, 1phase and 3phase converter drives for separately-excited and series DC motors for continuous and discontinuous operation, Braking techniques for DC and AC (IM) motors.

B. Suitability/ Selection of a drive based on process requirements (Matching of load, Motor, and converter), Brushless dc motor and drive.

Unit V (8 Hrs)AC Motor Drives and Power Quality

A. Motor Performance, Speed Control techniques of 1ph/3ph Induction Motor (Stator Voltage, Frequency, V/F, Rotor resistance), Protection Circuit for AC/DC Motor drives- Over/Under voltage and current, Phase failure, Field failure, soft start-stop, Effect of non-sinusoidal supply on motor performance.

Power Quality- Types of Power line disturbances, Sources and Measurement of power line disturbances, Preventive Techniques. B. Slip Power Recovery control of Induction motors, Energy Audit

Text Books 1. M D Singh & Khanchandani,“Power Electronics”, Tata McGraw Hill, IInd edition

M. H. Rashid, “Power Electronics”, 3 edition, Pearson Education, 2004

Reference Books 1. Mohan, Undeland & Robbins, “Power Electronics”, 3 edition, John Wiley, 2003

2. Dubey, Doralda, Joshi & Sinha, “Thyristorised Power Controllers”, New Age

International, 1986

3. P. C. Sen, “Thyristor DC Drives“, John Wiley, 1981

4. B. K. Bose, “Modern Power Electronics & AC Drives”, Pearson Education, 2002

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 48

FF No. : 654

Credits: 03 Teaching Scheme: - Theory 3 Hrs/Week Prerequisites: Nil

Objectives:

• To recognize role of machine vision

• To understand point, morphological operators

• To identify optimization technique and fuzzy system

• To understand image restoration

• To know various machine vision applications .

• Mapping with PEO : 1,2,3,6,7,8,9

Unit I (7 Hrs) Introduction to machine vision

A. Role of machine vision, applications, relation to natural vision, difficulties in machine vision

B. basic properties of image

Unit II (8 Hrs)Operations on image

A. Point operators, Morphological operators, Neighborhood operators

B. Frequency domain filtering

Unit III (8 Hrs)Object Recognition

A. Knowledge representation, statistical pattern representations, synthetic and neural nets, Recognition as graph matching, optimization technique and fuzzy system, template matching, feature matching, , models for object recognition.

B. texture matching

EC42123 :: MACHINE VISION

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 49

Unit IV (9 Hrs)Image Understanding and restoration

A. Control strategies, active control model, point distribution models, pattern recognition method, Hidden Markov models. MMSE restoration, least square error restoration, constrained LS restoration, , restoration homomorphism filtering

B. restoration by singular value decomposition, restoration by max a posterior estimation

Unit V (8 Hrs)Applications

A. Fingerprint matching, Face recognition, medical imaging, motion detection, intelligent B. Iris Recognition, case studies of different applications

Text Books 1.Image processing analysis and machine vision, Milan Sonka, Vaclav Hlavac, Roger Boyle, 2nd edition, Thomson Learning

2.Machine Vision, Galbiati,

Reference Books 1.IEEE / Elsevier Journal Papers on Machine Vision

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 50

List of Elective 4

Subject No. Subject Name Subject Code

S8 Telecommunication Network Management *

EC42124

S8 Digital Image Processing**

EC42125

S8 VLSI System Design***

EC42126

* Only for Communication module

** Only for Signal Processing module

*** Only for Microelectronics module

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 51

FF No. : 654

Credits: 03 Teaching Scheme: - Theory 3 Hrs/Week Prerequisites:

Objectives: • The existing telecommunication networks • Broadband Technologies • ISDN • SS7 Protocol • Optical Networks • Quality issues and Network management • Mapping with PEO : 1,2,3,6,7,8,9

Unit I (8 Hrs) Introduction To Telecommunication Networks

A. Switching Technologies: circuit switching, Routing for Circuit switched Networks, packet switching, Multirate circuit switching, Frame Relay, Cell Relay. Broad Band Access Technologies: DSL, ADSL, Cable Modems, WLL, Leased Lines, Optical and Wireless. B. Communication media.

Unit II (9 Hrs)Integrated Services Digital Networks (ISDN)

A. ISDN Overview, Principles, standards, ISDN Interfaces and functions, Protocol architecture, Internetworking. Signaling System Number7(SS7): SS7 Architecture, Signaling at data link level, link level, Network level, and signaling at connection control part. B. ISDN User part.

Unit III (7 Hrs)Optical Networks

A. Introduction, Principles of optical networks, Optical network components, Standards, Optical interface layers, concepts of multiplexing and synchronization. DWDM Networks: Introduction, architecture, Optical packet switching/ Routing.

EC 42124 :: Telecommunication Networks And Management

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 52

B. Optical routers, switches Unit IV (8 Hrs)Telecommunication Network Planning

A. Introduction , Principles of telecommunication network planning, traffic planning, Tariff planning, congestion control planning. B. congestion control and QOS.

Unit V (8 Hrs)Telecommunication Network Management

A. Telecom network operation and maintenance, Traffic management, management of transport network, configuration management, Fault management . B. Network design tools

Text Books 1. William Stallings, ‘ISDN and Broadband ISDN with Frame Relay and ATM’,

Prentice Hall . 2. Network Management: Principles and Practice - Mani Subramanian, Addison

Wesley, Pearson Education Asia publication.

Reference Books 1. W. Gorlaski, ‘Optical Networking and WDM’, TMH 2. Lakshmi Raman, ‘Fundamentals of Telecommunication Network Management’, IEEE press, PHI

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 53

FF No. : 654

Credits: 03 Teaching Scheme: - Theory 3 Hrs/Week Prerequisites: Digital Signal Processing.

Objectives: • To familiarize the student with the basic concepts about image, its formation, human

visual system and its limitations • To understand various image enhancement approaches • To apply the basic morphology principles • To understand image segmentation • To learn basic ideas of image compression • To prepare the background for student to apply principles learnt to practical cases • Mapping with PEO : 1,2,3,6,7,8,9

Unit I (8 Hrs) Digital Image Fundamentals and Image Enhancement

A) Elements of visual perception, Image sampling & Quantization, colour fundamentals, colour models, pseudo colour image processing. Basic grey level transformations, histogram processing, enhancement using arithmetic and logic operators, spatial filtering – smoothing and sharpening filters. Smoothing and sharpening

B) frequency domain filters

Unit II (6 Hrs)Morphological Image Processing

A) Neighbourhood concepts, adjacency and distance measures, dilation & erosion, opening & closing operations, basic morphological operations such as region filling, thinning, thickening, skeletons, pruning for binary and gray scale images.

B) Morphological operations for gray scale images.

Unit III (8 Hrs)

EC42125:: DIGITAL IMAGE PROCESSING

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 54

Image Segmentation

A) Detection of discontinuities, edge linking and boundary detection, thresholding, region based segmentation, use of watersheds, image representation- chain codes, boundary descriptors & regional descriptors

B) Other segmentation techniques

Unit IV (10 Hrs)Image Transforms

A) Coding, interpixel and image redundancy; 2-D Discrete Fourier Transform, Discrete Cosine Transform – its application in Baseline JPEG , Walsh Hadamard Transform, Fast Walsh Transform, sub band coding Haar Transform – it’s application as a Wavelet, multi resolution expansions, 1-D Wavelet Transform, Fast Wavelet Transform; Introduction to Gabor Transform, Introduction to Radon Transform,

B) Multycategory generalization

Unit V (8 Hrs)Image Processing Applications

A) Applications of transforms in fingerprinting, Medical applications, Morphological applications. Study of IEEE reference papers covering basic ideas of Transforms and their applications

B) Other applications of image processing

Text Books 1. Digital Image Processing, Gonzalez, Woods, PHI , 2nd edition

2. Digital Image Processing, Pratt W.K., John Wiley, 2001

Reference Books 1. Fundamentals of Digital Image Processing, Jain A.K., PHI, 1997 2. Image Processing , Analysis & Machine Vision, Milan Sonka, Thomson Publication .

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 55

FF No. : 654

Credits: 03 Teaching Scheme: - Theory 3 Hrs/Week Prerequisites: knowledge of digital system Objectives:

• The aim of the course is to provide a clear understanding of the concepts that support two dominant themes in system design viz. decomposition and assembly.

• To study Decomposition of a System into simpler subsystems: mechanisms and algorithms for breaking a system into simpler interconnected components.

• To study Memory sub-systems in System Design: different memory technologies, organizations and architecture that have been used in System Design.

• To learn Transmission of information between components of a system: the problem of interconnect design for reliable and fast communication in a system.

• To study Interconnection Networks in Systems • Mapping with PEO : 2,3,6,7,8,9

Unit I: Decomposition of a system into data and control paths ( 7 Hrs )

A: (a) Mealy/Moore state machines

(b) register-transfer-level descriptions

(c) Implementation using a single clock positive-edge-triggered paradigm .

B: State Reduction Techniques.

Unit II : Decomposition of the control path ( 8 Hrs )

A: (a) additive decomposition, state machine re-use

(b) multiplicative decomposition, control synchronization.

B: control deadlocks

Unit III : Parallelism and system decomposition ( 8 Hrs )

EC42126 :: VLSI SYSTEM DESIGN

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 56

A: (a) Pipelines: control-flow and data-flow pipelines.

(b) Communication between sub-systems

(c) Queuing models of systems and performance modeling.

B : Deadlock revisited

Unit IV : Memory Sub-systems

A: ( 8 Hrs ) a) Memory architecture

b) Shared memory data hazards and consistency, mutual exclusion

B: Mutual Exclusion.

Unit V : Interconnect Issues ( 9 Hrs )

A: (a) signal interconnect models: lumped, distributed, transmission-line

(b) Delay and crosstalk

(c) Signaling

(d) Power and clock distribution

(e) level-triggered circuits

B : Asynchronous System

Text Books 1. J. M. Rabaey, Digital Integrated Circuits, A Design Perspective Prentice-Hall India, New Delhi, 1997

Reference Books

1. W. J. Dally, J. W. Poulton, Digital Systems Engineering, Cambridge University Press, 1998 2. H. G. Cragon, Memory Systems and Pipelined Processors, Narosa, 1996

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 57

FF No. : 654

Credits: 01 Tutorial: - 1 Hr/Week

Mapping with PEO : 1,3,6,7,8,9

List of tutorials:

• Discontinuous controllers

• Discontinuous controllers

• Continuous controllers

• Continuous controllers

• PLC programming

• PLC programming

• State variables

• State variable

• Stability analysis

• Stability analysis

• Design of classical controller

• Design of intelligent controller

EC 41201:: Electronic Automation

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 58

FF No. : 654

Credits: 01 Teaching Scheme: - Tutorial 1 Hr/Week Prerequisites: Communication Engineering & Digital Communication.

Objectives: To Study

• Equipment like Pattern Generator, Wobbuloscope which can be used for Color TV servicing

• To study different sections in Color TV receiver

• To study TV transmitter, TV studio, DTV, HDTV, DTH, DVD player and DSR block schematics

• Mapping with PEO : 1,2,5,6,7,8

List:

1. Study of Video signal generation. 2. VIF amplifier response using Wobbuloscope 3. Voltage and Waveform Analysis of Color TV. 4. Video amplifier response testing 5. Sync separator 6. Video Compressing Technique. 7. Design of an Yagi antenna 8. Color spaces 9. Remote control circuit 10. Public address system 11. TV connectors 12. Video bandwidth calculation 13. Concept of IF & its choice 14. Design of a video detector 15. Horizontal output stage 16. Trouble shooting in a TV receiver

EC42212::AUDIO VIDEO ENGINEERING

Page 28: elexd11m8(1)

Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 59

Credits: 01 Teaching Scheme: - Tutorial 1 Hrs/Week Prerequisites: Basics of Power devices, Basics of Power Conversion systems,

Basics of AC/DC Motors, Fourier series for analytical approach

Objectives: • To verify operations of power converter systems for different types of loads • To gain hands on experience on different AC / DC motor drives & it’s protection

Systems • Use of simulation software for analysis of power systems. • Mapping with PEO : 2,3,6,7,8,9

List of Tutorial

1. Study of 3 Φ VSI (180º or 120º) 2. Study of Chopper fed / Converter fed DC Drive. 3. Study of speed Control of AC Drive 4. Power factor improvement technique (SAC or EAC or PWM) 5. Study of VVVF 3 phase IM Drive. 6. Sensing and Protection circuits for AC and DC Drives 7. Simulations of 3 phase LCC (HCB or FCB or dual Converter). 8. Simulation of 3 phase VSI (180º or 120º) / Simulation of DC/AC drive. 9. Design of one power electronic control circuit.

Text Books 1 M D Singh & Khanchandani,“Power Electronics”, Tata McGraw Hill, IInd edition

2 M. H. Rashid, “Power Electronics”, 3 edition, Pearson Education, 2004

Reference Books

1 Mohan, Undeland & Robbins, “Power Electronics”, 3 edition, John Wiley, 2003

2 Dubey, Doralda, Joshi & Sinha, “Thyristorised Power Controllers”, New Age

International, 1986

FF No. : 654

EC42213 : Advanced power Electronics

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 60

FF No. : 654

EC42214 :: MACHINE VISION Credits: 01 Teaching Scheme: - Tutorial 1 Hrs/Week Prerequisites: Nil

Objectives:

• To recognize role of machine vision

• To understand point, morphological operators

• To identify optimization technique and fuzzy system

• To understand image restoration

• To know various machine vision applications

• Mapping with PEO : 1,2,3,6,7,8,9

List

1. Study of various file formats

2. Simulation of morphological operators

3. Comparison of Template matching and feature matching

4. Simulation of HMM model

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 61

FF No. : 654

EC 40303 :: ELECTRONICS SYSTEM DESIGN & MODELING

Credits: 1 Teaching Scheme: - - Laboratory 2 Hr/Week Prerequisites: Students having basic knowledge of analog and digital electronics. Objectives: To understand

• Important considerations in developing a particular electronic product. • Modeling – Hardware & software • Integration of hardware & software • Mapping with PEO : 2,3,6,7,8,9

List of Contents

Part A.

1. Modeling of hardware circuit: Analog circuit. 2. Assembling of the circuit & its testing. 3. Analysis of assembled circuit. (AC analysis, DC analysis, Monte Carlo

Analysis etc) Part B

4. Modeling of hardware circuit: Digital circuit. 5. Assembling of the circuit & its testing 6. Analysis of assembled circuit. (AC analysis, DC analysis, Monte Carlo

Analysis etc) Part C

7. Environmental testing of a circuit. (Temperature effects) 8. Case study. System design, Analysis of its constraints, observations &

conclusions. Part D

9. Mini-Project

Page 31: elexd11m8(1)

Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 62

FF No. : 654

Credits: 01 Teaching Scheme: - Laboratory 2 Hrs/Week Prerequisites: Knowledge of Computer networking, Broad band Technologies, Fiber Optics Objectives: Configuration of various Telecommunication devices Configuration of various Broad Band devices Implementation of Optical Networks Mapping with PEO : 1,2,3,6,7,8,9

List of Practicals

1. Establishing Broad Band connectivity between two or more computers using ADSL Router.

2. To configure the cable modem and establish high speed internet communication using Cable modem

3. To establish high speed data transfer between computers using ISDN connection 4. To establish point to point and point to multi point connections in ISDN. 5. To implement peer to peer networking using Fiber optic Networking 6. To study analyse telecommunication network performance. 7. To study the traffic management and implement congestion control algorithms. 8. To study the SS7 protocol and implement routing algorithms. 9. Course project based on the syllabus.

Text Books 1. William Stallings, ‘ISDN and Broadband ISDN with Frame Relay and ATM’,

Prentice Hall .

Reference Books

1. W. Gorlaski, ‘Optical Networking and WDM’, TMH 2. Lakshmi Raman, ‘Fundamentals of Telecommunication Network Management’, IEEE press, PHI

EC 42310:: TELECOMMUNICATION NETWORKS AND MANAGEMENT

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 63

FF No. : 654

EC42311 :: Digital Image Processing Credits: 01 Teaching Scheme: - Laboratory 2 Hrs/Week Prerequisites: Nil Objectives:

• To familiarize the student with the basic concepts about image file formats • To understand various image enhancement approaches • To apply the basic morphology principles • To understand image segmentation • Mapping with PEO : 1,2,3,6,7,8,9

List of Practical

1. Study of BMP file format 2. Conversion of 24 bit color image to 8 bit , 4 bit, 1 bit image 3. Image negation, power Law correction 4. Histogram mapping & equalisation, stretching 5. Image smoothing , sharpening 6. Edge detection – use of Sobel, Prewitt and Roberts operators 7. Morphological operations on binary images 8. Morphological operations on Gray scale images 9. Pseudo coloring 10. Chain coding 11. Image statistics 12. DCT/IDCT computation 13. Transform application assignment.

Text Books 1. Digital Image Processing, Gonzalez, Woods, PHI , 2nd edition

2. Digital Image Processing, Pratt W.K., John Wiley, 2001

Reference Books 1. Fundamentals of Digital Image Processing, Jain A.K., PHI, 1997 2. Image Processing, Analysis & Machine Vision, Milan Sonka, Thomson Publication .

Page 33: elexd11m8(1)

Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 64

FF No: 654

EC42312 ::VLSI SYSTEM DESIGN Objectives:

• To decompose a System into simpler subsystems • To find out data and control path • To assemble the decomposed system • To design and implement a dual port memory • To simulate a wire • Mapping with PEO : 2,3,6,7,8,9

List of Practicals

1. Design sequence recognizer for detecting three successive 1s using Moore Machine

2. Design Pipelined adder

3. Design right shift only barrel shifter.

4. Design FIFO.

5. Design sequential binary multiplier

6. Design SRAM with controller

7. Design carry look ahead adder

8. Design a synchronizer circuit when the width of the asynchronous input pulse is greater than the period of the clock

9. Design a synchronizer circuit when the width of the asynchronous input pulse is less than the period of the clock

10. Design UART transmitter ASM chart

Text Books

1. Plummer, Deal , Griffin , Introduction to semiconductor fabrication , Prentice Hall publication – 2001. ISBN No 0130224049

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 65

FF No. : 654

Credits: 6 Teaching Scheme: - Lab 8 Hrs/Week Prerequisites: Knowledge of Basic engineering subjects.

Objectives: • To select and work on real life application in the field of Electronics and

Telecommunication. • To support students’ learning and engagement with principles of undergraduate

education. • To apply and enhance the knowledge acquired in the related field.

Mapping with PEO : 1 to 9 Guidelines for students

1. The project work will be carried by a group of students. Optimum group size is three students. However, if project complexity demands a maximum group size of four students, the coordinating committee should be convinced about such complexity and scope of the work

2. Topic of the project work should be in the field of Electronics and Telecommunication related to real life application OR investigation of the latest development OR Microcontroller based application OR Software development project with the justification for techniques used/implemented.

3. Interdisciplinary projects should be taken up only with the justification for techniques used and the coordinating committee should be convinced about such complexity and scope of the work

4. The abstract of the project should be submitted before the evaluation of. Project work during first semester.

5. A certified copy of project work carried out in the first semester is required to be presented to internal guide at the time of evaluation.

6. Group should maintain a logbook of activities in a year. It should have entries related to the work done, problems faced, solutions evolved, etc., duly signed by internal and external guides.

7. Final project report must be submitted in the prescribed format only. No variation in the format will be accepted. One guide will be assigned maximum three project groups.

Upon completion of this course student will be able to : Apply various aspects of the curriculum which support students’ increasing mastery of competencies in technicality.

EC 47304::Project (stage II)

Page 35: elexd11m8(1)

Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 66

A

CAD

EM

IC

INFO

RMA

TIO

N

Page 36: elexd11m8(1)

Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 67

A) Mid Semester Examination

1. Students reporting in morning slot will have examination in morning slot. Those in

evening slot will have examination in evening slot.

2. 20 multiple choice based questions to be attempted in 30 minutes x no. of theory

courses i.e. 100 questions in 150 minutes for F.E., 80 questions in 120 minutes for

S.E., T.E.,B.E.,M.E., 20 questions in 30 minutes for Honors, Minor, Fast Track, etc.

3. A scrambled mix of questions will be generated through software.

4. Mid Semester Examination will be based on Unit II & Unit III.

5. There will be one mark for each correct answer and (-) 0.25 marks for every wrong

answer.

6. For a typical 3 hour Mid Semester Examination, first 15 minutes would be used for

student attendance, record keeping, seat allocation, log in procedure if any, etc. Next

150 minutes for actual examination. A timer indicating time remaining to be provided

by ERP. 15 minutes for processing & results.

7. A visual alarm / flash would be given 10 minutes before completion of 150 minutes as

a warning. For auto generation of every theory course result out of 20 and dispatch of

the marks on student mobile and mail ID as well as parent mail ID.

8. No repeat examination under any circumstances.

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 68

B) Seminar – Conduct, Evaluation, etc.

Seminar– (T.E.- Semester I)

1. Review – I: during Mid Semester Examination (Compulsory) as per the Academic

Calendar.

2. Review – II : The last week of November (Optional)

3. For poor performing students identified by the examination panel, a second review to

be taken. Review II optional for other students. For Review II, deduction of 10 marks

will take place.

4. Seminar is an individual activity with separate topic and presentation.

5. Duration of presentation – 20 minutes

Question and answer session – 10 minutes

Seminar Evaluation Scheme :

1. Attendance during Semester – 10 marks

2. Attendance during Seminar presentation self & peer – 10 marks

3. Relevance of Seminar topic – 10 marks

4. Timely Abstract submission – 10 marks

5. Literature review – 10 marks

6. Technical contents – 10 marks

7. Presentation – 25 marks

8. Question & answer Session – 15 marks

---------------

100 marks

=========

Page 38: elexd11m8(1)

Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 69

C) Equivalence

For the courses belonging to 2008 structure counseling sessions for failure students will be

arranged. The Head of Department will appoint faculty identified as subject experts as

counselors. The previous examination scheme i.e.

Class Test – 10 marks

T.A. through Home assignment – 10 marks

A written paper MSE – 30 marks

A written paper ESE – 50 marks

Will be followed. The entire processing based on 2008 structure related coding scheme will

be followed. Counseling + Administration + Examination charges will be the basis for fees

considered for such students.

Page 39: elexd11m8(1)

Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 70

D) Extra Credits

A student planning to take extra credits may be considered under following categories :

(a) A student carrying a backlog and re-registering for the previous course – Re-registration

charges as applicable. Consideration of all courses registered for during that Semester of

Academic Year for SPI calculation.

(b) Student planning to take extra courses as a fast track opportunity – Administration,

processing and examination charges will be considered. In any case the student has to

pay the college fees for four years. This fast track facility would enable the student to

undergo an industrial training, an exchange programme, research contribution in I.I.T.

under scheme such as KVPY without any academic compromises for credit transfer. The

phasewise development and completion of project activity cannot be considered at an

accelerated pace under fast track scheme. The registration under fast track is subject to

having a CPI 8.0 or above and no backlog for consideration of registration to an

additional course.

(c) Students opting for earning extra credits by selection of courses in addition to the

courses prescribed by respective BOS which are single Semester activities and not the

part of Honors / Minor scheme. Such students will be expected to pay charges equivalent

to re-registration (proportionate credit based payment). The registration for such courses

is subject to permission given by the Chairman BOS of the Board in the purview of

which the subject is identified. Such permissions will be given based on meeting with

prerequisite subject.

1. In any case (a), (b) or (c) the candidate cannot register for more than 8 credits.

2. A suitable reflection of completion of the said course will be made in the candidate’s

Grade statement.

For part (c) a separate grade & GPA will be calculated. That GPA will not be clubbed

with the other regular courses for SPI, CPI calculation.

Page 40: elexd11m8(1)

Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 71

E) Home Assignment

A Home Assignment Calendar for Semester is prepared as under:

Week No. Activity

1 No Home Assignments

2 No Home Assignments

3 No Home Assignments

4 S1 / S2 – HA1

5 S3 / S4 / S5* - HA1

6 S1 / S2 – HA2

7 S3 / S4 / S5* - HA2

8 S1 / S2 – HA3

9 S3 / S4 / S5* - HA3

10 S1 / S2 – HA4

11 S3 / S4 / S5* - HA4

12 S1 / S2 – HA5

13 S3 / S4 / S5* - HA5

14 No Home Assignments

15 No Home Assignments

16 No Home Assignments

The Home Assignments will be based on the self study component i.e. part B of every theory

course syllabus. The Saturday or last working day will be the default deadline for submission

of Home Assignment of that week. For example by the Saturday ending Week No. 9, Home

Assignment No. 3 for subject S3/ S4/ S5 (if applicable) must be submitted.

1. *S5 can be OE1 / OE2 / OE3 / Honors/ Minor / Re-registration category (a) /

Category (b) / Category (c).

2. For subjects S1, S2, S3, S4 & S5 (if any), the composition of the Teacher Assessment

marks will be as follows :

Page 41: elexd11m8(1)

Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 72

S1,S2 with Tutorial S3,S4,S5 without

Tutorial

Home Assignment 30 marks 30 marks

Tutorial 30 marks

Test 30 marks 30 marks

Attendance :

(a) > 90%

(b) 75% to 90%

(c) <75%

10 marks

5 marks

0 marks

10 marks

5 marks

0 marks

100 marks converted to

15 marks

70 marks converted to 15

marks

Explanation :

1. Tutorials to be conducted with continuous assessment throughout the Semester. Final

assessment out of 30 marks for Tutorial.

2. Class Test to be conducted during a regular theory class within the time period

mentioned in the Academic Calendar.

3. Class Test marks are to be entered immediately as mentioned in Academic Calendar.

4. Attendance percentage to be calculated at the end of Semester after completing all

lectures as per the lesson plan.

Page 42: elexd11m8(1)

Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 73

F) Mini Project

Teaching Scheme: Theory – 0 ; Tutorial – 0 ; Laboratory – 2 Hrs / week

For F.E., S.E. & T.E. students in every Semester a Mini Project be carried out. The

objectives behind the Mini Project are:

1. Scope for creativity

2. Hands on experience

3. Academic occupancy

Mini Project will be based on all subjects of that Semester except GP.

1. The Semester Mini Project will be for a group of 3 to 5 students. Head of

Department to appoint Mini Project Guides. 1 credit will be awarded to the

candidate after the viva voce and project demonstration at the End of Semester.

2. Group formation, discussion with faculty advisor, formation of the Semester Mini

Project statement, resource requirement, if any should be carried out in the earlier

part of the Semester. The students are expected to utilize the laboratory resources

before or after their contact hours as per the prescribed module.

The Assessment Scheme will be:

(a) Continuous Assessment 50 marks

(b) End Semester 50 marks

---------------

100 marks

==========

Page 43: elexd11m8(1)

Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 74

G) Project Stage I Evaluation

The project activity is broken in 3 stages:

The Project Stage I will be in T.E Semester II irrespective of student module. The evaluation

of Project Stage I will be as follows:

Group formation & attendance / reporting to guide 20 marks

Topic finalization / Statement 20 marks

Literature Survey 20 marks

Abstract 20 marks

Presentation 20 marks

Project Stage II and Project Stage III evaluations will be based on Department specific

norms.

Page 44: elexd11m8(1)

Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 75

H) Composition for Selection of 5 Credits for Honors / Minor Course

(Applicable for B11 and A11 Patterns)

(A) Comprehensive Viva Voce – Compulsory at the end of Semester VIII – 1 Credit

(B) Elective Component

a. Laboratory courses – Maximum Credits - 2

(for award of 1 Credit the lab course would have a teaching scheme of 2 Hrs. / week and a

plan of 12 practicals). The credit to be awarded as per the ISA and ESA guidelines for the

compulsory lab courses.

b. Research publication – Maximum Credits – 1

(Research Publication in a Magazine / Transaction / Journal as decided by the honors / minor

co-ordinator)

c. Seminar - Maximum Credits – 1

(Seminar to be given on a topic consistent with the scope of the Honors or Minor. The topic

Selection is to be approved by the honors / minor co-ordinator. The assessment and

evaluation scheme would as per the guidelines used for Technical Seminar at UG level by

respective Dept.)

d. Honors / Minors Project – Maximum Credits – 2

(Project Topic and Scope, its progress and final assessment consistent with the scope of the

Honors or Minor. The topic Selection is to be approved by the honors / minor co-ordinator.

The assessment would as per the guidelines and evaluation scheme used for Project Work at

UG level by respective Dept.)

e. Industrial Training – Maximum credits – 4

(An Industrial Training in an Industry identified by the student, approved by the honors /

minor co-ordinator & Head of Department. The assessment would as per the guidelines and

evaluation scheme used for Industrial Training at UG level by respective Dept.)

Note :

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Bansilal Ramnath Agarwal Charitable Trust’s

Vishwakarma Institute of Technology, Pune – 411 037

Department of Electronics Engineering

Structure & Syllabus of B.E. (Electronics) Program – Pattern ‘A11’, Issue No.3, Rev No.1 dated 2/4/2011 76

a. 4 Credits would be awarded to the students for a complete 12 Week Industrial Training and

meeting with the assessment and evaluation requirements

b. Provision can be made for the students unable to procure a 12 week Industrial Training. A 4

week or 8 week Industrial Training may also be offered. 2 credits will be awarded for 8

week Industrial Training and 1 Credit would be awarded to the students for a 4 Week

Industrial Training, meeting with the assessment and evaluation requirements

c.No Industrial Training less than 4 weeks be considered for award of 1 Credit

d. No cumulative addition of Industrial Training period would be considered for award of

credits

The student is expected to earn 1 Credit from Part (A) and remaining 4 Credits from

Part (B)