Eletronica LCD
Transcript of Eletronica LCD
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EDITED BY BILL TRAVIS& ANNEWATSON SWAGER
EDN DESIGN IDEAS
As FPGA capabilities increase and time to market decreases,FPGAs gain more acceptance for implementing both data
and control paths. Thus, they find wide use as controllers
an d d atapath glue logic for fast-page DRAMs. Synch ron ous
DRAMs (SDRAMs), whose control signals use a clock input
as referen ce, are a natu ral target for FPGA-based con trollers.
SDRAMs operate at frequencies of 100 MHz an d h igher (in
con trast with fast-page DRAMs, for wh ich a 60 -MHz mem o-
ry-system clock was con sidered h igh). Figu re 1 shows a way
to im plem en t FPGA-based SDRAM con tro llers. Figure 2
sho ws th e timin g for a Xilin x XC4010 E-2 device. You can
apply the method to FPGAs from other vendors, as well as
to h igh-frequen cy systems oth er th an SDRAMs.
When you use FPGAs, delays to get on and off chip add
up q uickly: clock pin to in ternal clock buffer for th e intern alclock-distribution n et (5.4 nsec) an d int ernal clock to outp ut
flip-flop (4.5 nsec minimum). The sum of these delays
exclud es an FPGA from app lication wit h SDRAMs using a 10-
nsec clock period, considering a 3-nsec setup time for the
address, con trol, and data-out signals. Figu re 1 shows how
to u se a PLL with an FPGA an d h ow to im plemen t clock an d
control-path signals to make FPGA-based SDRAM con-
trollers that operate at 100 MHz and beyond. The SDRAM
address, data, and control signals use the memory-system
clock, MCLK, as reference and the FB signal from an FPGA
output pin as feedback.
Because the PLL loop uses no dividers, MCLK and XCLK
h ave th e same frequen cy. Wh en th e PLL locks, the XCLK sn al precedes MCLK by a tim e equal to t h e sum of th e cloc
buffer delay (from XCLK to ICLK) and the combinatori
ou tp ut -buffer delay (from ICLK to t h e PLL feedback pin ). T
address, con trol, and data-out signals obtain th eir clock s
n als from ICLK. Because th e delay from ICLK to t h e clock
out pu t pin (7.0 nsec for th e slew-rate-lim ited out pu t) is clo
to bu t h igher th an th e delay from ICLK to th e FB outpu t p
(4.8 nsec for a fast ou tpu t), the clocked ou tpu t app ears ea
in t h e CLK period.
The required SDRA setup time is thus easily fulfilled in
100-MHz system : (10(7.04.8))>3 n sec. Note th at ch an g
in temperature, IC processes, and voltage have little infl
ence on performance, because the XCLK clock-generati
circuit is a closed-loop system. Mo reover, th e ou tpu t bu fof the FB pin an d th e control and data pins h ave the sam
clock in pu t as does th e inpu t pin , and all circuit blocks resi
on the same die. Tests designed to check the data-inp
setup-and-hold times used a clocked input flip-flop (in t
same I/O b lock as the d ata-outpu t flip-flop), wh ich receiv
its clock from an intern al version of MCLK. This configu
t ion avoids excess ive hold- t ime requi rements for t
SDRAM. (Editors note: An EDN contributing editor warns th
the 7.04.8 nsec reflects maximum specified times for t
XC4010E-2 and yields an acceptable margin for an SDRAM wi
1.5-nsec minimum hold time. However, an FPGA running
typical specs may present a m arginal situation.) Tests usin g t
AV9170-01 PLL from ICS show satisfactory performance
106.25 MH z. (DI#2165) e
To Vote For This Design, Circle No. 415
PLLFB
REFVCO
XCLK
FPGAFB
ICLK
CLKBUF
CLKBUF
SDRAM
CONTROL
ADDR
DATA
CLK
MCLK
DOUT
DIN
DELAY
FIGURE1
MCLK
XCLK
ICLK
FB
CONTROL/ADDRESS/DATA OUT
(1)
(2)
(3) (4)
(1) XCLK TO ICLK INTERNAL CLOCK-BUFFER DELAY: 5.4 nSEC.
(2) ICLK TO FB COMBINATORIAL FAST OUTPUT-BUFFER DELAY: 4.8 nSEC.
(3) ICLK TO SLEW-RATE-LIMITED OUTPUT DELAY: 7.0 nSEC.
(4) ACHIEVED CONTROL/ADDRESS/DATA-OUT SETUPTIME TO SDRAM: MCLK PERIOD MIMUS 2.2 nSEC. FIGURE2
PLL implements FPGA-based SDRAM controllerEDDY DEBAERE, BARCO GRAPHICS, GHENT, BELGIUM
The use of a PLL wit h an FPGA eliminates the setup-tim e prob-lems inherent in an FPGA-only configuration, allowing you todesign SDRAM controllers for clock frequencies of 100 MHzand beyond.
The timing for a Xilinx XC4010E-2 device shows 7.04.8=2nsec, an acceptable figure for an SDRAM wit h 1.5 -nsec mimum hold time.
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EDN DESIGN IDEAS
Sometimes, you need to distinguish between two voltages,using some h ysteresis in t h e decision . Wh en th e levels of the
com pared signals vary over a wide range (for exam ple, a few
orders of magnitu de), the h ysteresis width shou ld vary sim-
ilarly to ensure a constant ratio between hysteresis width
an d sign al level. You cou ld encou n ter such a situation , for
example, when you n eed to decide which o f two transmis-
sion chan n els con veys a higher qu ality signal (one with a
h igher level). You n eed th e hysteresis to avoid perm anen t
changes in the decision when the signal levels are close to
each other. In this case, the best way to choose the greater
voltage is to m ake the decision by taking th e ratio of the sig-
nals instead of comparing them directly. Figure 1 shows a
circuit with signal-variant hysteresis.
Amp lifiers IC1A and IC1B with associated resistors anddiodes, R
1, R
2, D
1, and D
2, operate as logarith m ic converters,
producing ou tput voltages
where VT=kT/q25 mV at room temperature, and I
Sis the
saturation current of th e p-n jun ction . The d erivation of the
equation assum es that R1=R
2=R. Next , voltages V
O1and V
O2
combine in the sum min g amplifier, IC1C . Using th e assumtion that R3=R
5and R
4=R
6and th at the diodes are match e
th e outpu t voltage from IC1C
is
The voltage is thu s proportional to th e ratio of th e inp
voltages. The last amplifier in the circuit, IC1D
, is a stand a
inverting comparator with hysteresis centered around ze
and th e th resho ld levels:
The voltage swing at th e outp ut o f the circuit (V+O4
, V+O
is a fun ction o f the limiter com prisin g resistor R9
and diod
D3
t o D8. The output vol tage , V
changes state when VO3
>V+H
(outp
goes low) or VO3
<
+
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EDN DESIGN IDEAS
Alphanumeric LCD modules can provide an attractive dis-
play for a pro ject, but th eir parallel I/O lin es requ ire a largenumber of outputs from a C. For exam ple, a direct LCD
interface would consume all of the I/O pins of a small C,
such as the eight-pin PIC12C508 from Microchip Techn olo-
gy (Ch an dler, AZ).
However, the circuit in Figure 1a implements a clocked
serial in pu t for an LCD mod ule and allows a C to comm u-
n icate with th e LCD over just t wo signal lines. You can fit
th e circuit onto a small pc board and m oun t th e board direct-
ly behind the LCD module. The connection between the
board an d LCD m odu le com prises just four wires, in cluding
VCC
and groun d.
A 74LS164 serial-to-parallel shift register forms the
h eart of the circui t and com m un icates with th e LCD mo d-
ule in 4-bit m ode. The shift registers out pu ts directly driveth e LCD m odu les data inp uts, DB7 th rough DB4, as well
as RS, th e cont rol/data select inp ut. The o n ly signal th at is
n ot a d irect outpu t from the shift register is the LCD m od-
ules enable p in, wh ich is Pin 6. R4
a nd D1
derive th e enable
inpu t and ensure that th e enable signal remains low unti l
valid data is present at all other outputs. R1
is a current-
limiting resistor for an LED backlight if the LCD m odu le
has one , and R2
a nd R3
set th e contrast level of the m od-
ule. You can replace R2
a nd R3
with a p otent iom eter if an
adjustable contrast level is desirable.
Th e C m ust first clock in at least seven zeros for th e fiwrite (Figure 1b). Th is series of zeros guaran tees that out p
QG
of IC1
is low and will remain so for the next six clo
cycles. This low level en sures that th e enable inp ut (Pin 6
th e LCD m odu le) remain s low because of diode D1. The s
ial-in pu t stream th en m ust con sist of a on e, followed by R
and finally DB7
through DB4. With the data input low,
addition al clock pulse sh ifts in a zero and lin es up all of t
outputs to the LCD module with the correct shift-regis
pins. The first clocked-in one now appears at QG, whi
reverse-biases D1. The enable continues to remain lo
because the data input to the circuit is low, and this situ
tion pulls the enable low through R4. The data input th
must go high for at least 450 nsec without a clock pulse
provide th e enable pu lse for the LCD mod ule. Th is proceincludin g clocking in at least six zeros, is then repeated f
th e next 4-bit write.
For further information, including m inimum cycle tim
and 4-bit-mo de comm un ication, consult the techn ical do
umentat ion provided by an LCD module manufactur
such as Opt rex (Plymou th , MI). (DI #2177) e
To Vote For This Design, Circle No. 417
1
3
5
2
4
6
12
14
LCD HEADER
A
QB
QC
QD
QE
QF
QG
B
CLK
CLR
VCCR1
R21
2
R3
150
LED
BACKLIGHT
1N4148
D1
R4
1
2
8
9
VCC
100 pF
100 pF
0.1 F74LS164
SERIAL DATA
SERIAL CLK
TWO-SIGNAL
WIRE
CONNECTION
VCC
CLOCK
DATA
ALWAYS
"1"ALWAYS
"0"RS DB7 DB6 DB5 DB4
10k
33
4.7k
4
5
6
10
11
12
RESET SHIFT REGISTER CLOCK DATA IN STROBE LCD
MODULE
11
13
(a)
(b)
FIGURE1
EDMASTE, JEM DESIGNS, PICKERING, ON, CANADA
Using a 74 LS164 shift register and 4-bit comm unication, a C can control an LCD module using just two lines: serial data aclock ( a). The C must first clock a series of zeros to the circuit, followed by a one, RS, and DB
7through DB
4(b).
Simple LC D interface takes two wires
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EDN DESIGN IDEAS
A num ber of soph isticated ICs for step-
per-motor control are now available.However , the advanced fea tures of
these chipsself-clocking, high-cur-
rent drive, and full-step, h alf-step, an d
direction controlare often unneces-
sary or remain unused. For a design
that n eeds to control only the n um ber
of steps, drive speed, and direction , you
can make a very simple and inexpen-
sive driver using two low-level logic
chips (Figure 1). The cost of this con-
troller is less th an $1; the cost of ded icated m otor-cont rol ICs
starts at aroun d $5. The d rawback is a slight in crease in board
space.
Going back to th e basics, you can con trol a stan dard step-per-m otor d rive, wheth er bipolar or unipo lar, usin g a four-
step sequen ce (Table 1 a). By replacin g the on an d off states
with ones and zeros, respectively (Table 1b) , Column B
becomes the logical inverse of Column A, and Column D
becomes th e logical in verse of Colum n C. Th us, the corre-
sponding state diagram (Figure 2 ) comprises just 2 bits.
Clockwise rotation results from using a logical one t o m ove
sequen tially from state one to state four and back to state
on e. Likewise, cou n terclockwise rotation results from using
a logical zero to move through the states in the reverse
order.
You can th en p rodu ce the present-state/next-state assig
ment (Table 2) and th e next-state maps (Figu re 3). Th en,
inspection, the logical choice is to loop the state maps o
for D flip-flops, which produces the following two logequations:
DA=((DIR)(C))+((DIR) (C));
DB=((DIR) (A))+((DIR) (A)).
Equation 1 is an exclusive NOR, and Equation 2 is
exclusive OR. To save space, you can use a single qu ad XO
chip to implement both equations. A dual D flip-flop co
pletes th e logic driver, as Figu re 1 shows. Using rising-edg
triggered D flip-flops helps keep the design simple whi
eliminating mode-change faults.
The circuit derives the four outputs from the Q and
Two logic-level ICs can implem ent simple and inexpensive contr ol of a stepper-mot or dr iver.
NOTES:
IC1=74LS36;
IC2=74LS74.
VCC PRE
IC2A
IC2BIC1C
IC1B
IC1D
IC1A
CLK
QD
Q
CLR
CLR PRE
CLK
QD
Q
A
B
8
2
1
3
31
2
6
5
C
D8
9
4
13 10
7
7
9
5V
STEP
DIR
GND
5
46
14
14
GROUND
13
12
1211
11
10
FIGURE1
DAVIDELLIS, ELLISLINDAUER, PULLMAN, WA
Inexpensive logic controls stepper motor
TABLE1STEPPER-MOTOR-DRIVE SEQUENCE
State A B C D
1 ON OFF ON OF
2 ON OFF OFF ON
3 OFF ON OFF ON
4 OFF ON ON OFFCCW CW
(a) (b)
State A B C D
1 1 0 1 0
2 1 0 0 1
3 0 1 0 1
4 0 1 1 0
(
(
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EDN DESIGN IDEAS
ou tpu ts of D flip-flop s IC2A
and IC2B
in Figure 1 . IC1A
XORs
th e Q ou tpu t of flip-flop IC2B
with the DIR input , and the
circuit tran sform s the out put into an XNOR by using IC1B
as a cont rolled inverter. IC1B
th en d rives the D inpu t of flip-
flop IC2A
. Sim ilarly, IC1C
XORs the Q ou tpu t of IC2A
with th e
DIR inpu t. Th e outp ut o f IC1C
drives XO R IC1D
, which acts
as a noninverting buffer. The output of IC1D
drives the D
input of IC2B
. Using XOR gate IC1D
as a buffer keeps the
propagation delays to th e D inpu ts of the flip-flops equal,
wh ich h elps the circuit avoid an y race con dition s. The STEP
signal is the step-rate inpu t, which drives th e clock inpu ts
of both flip-flops.The last design task is to add the appropriate-sized tran-
sistors to d rive th e stepper m otor. In th e case of the u n ipo-
lar motor, output signals A, B, C, and D can directly drive
th e transistors. To d rive a bipolar m otor, you can use th e A
and C outp uts to drive one-half of two H-bridges and th e B
and D outpu ts to drive the oth er corresponding h alf of the
H-bridges. This design is possible because the B output
th e inverse of A, and D is th e inverse of C. (DI #2176)
e
To Vote For This Design, Circle No. 418
The state diagram for the stepper-motor controller compris-es just 2 bits.
The next-state maps correspond to two simple logic equtions.
1
2
4
3
0
0
0 0 11
1
1FIGURE2
DIR
DIR
DA
DB
0 0 1 1
1 1 0 0
1 0 0 1
0 1 1 0
00 01 11 10
00 01 11 10
AC
AC
FIGURE3
Present state Next state
A C DIR A C
0 0 0 1 0
0 0 1 0 1
0 1 0 0 0
0 1 1 1 1
1 0 0 1 1
1 0 1 0 0
1 1 0 0 1
1 1 1 1 0
TABLE2PRESENT-STATE/NEXT-STATEASSIGNMENT TABLE
New personal digital assistants, pagers, and other battery-
po wered system s operate at or b elow 2.7V, but p ower-on
resets with th resh olds below 2.6V are not com m on ly avail-
able. You can resolve th is prob lem u sing a circuit th at com -
bines a 1.2V reference and a micropower regulator (Figure
1a). IC1
integrates these two functions in a tiny SOT-143
package. A power-on-reset function must become active
before the supp ly voltage reaches its no m inal value, and IC1
op erates properly for supp ly voltages above 1.21V.
The R1/R
2divider and int ernal 1.204V reference establi
a threshold that determines when the circuit asserts
active-low at th e outp ut. For the values in th e figure , th
threshold is 2.25V (Figu re 1b ). IC1
has an op en-drain ou
put , so R3
and C1
control th e length of th e active-low pul
RESET. In this case, the pulse length, or reset interval,
approximately 54 msec, which is sufficient reset time f
Low-voltage reset operates below 2.7VBOBKELLY, MAXIM INTEGRATED PRODUCTS, SUNNYVALE, CA
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EDN DESIGN IDEAS
A 1.2V reference and micropower regulator in IC1
(a) provide an active-low reset pulse of approximat ely 54 msec at pow er-or when V
CCdips below 2.25V ( b).
++
1.204V
REF
GND
VCC 2
1
OUT 4
MAX836
IC1IN 3
VCC
R1
R3390k
0.1 FR2
931k
1%
NOTES: OUTPUT IS VALID FOR VCC>1.21V.
RESET THRESHOLD IS ~2.25V.
RESET PULSE IS ~54 mSEC.
1.07M
1%
CG(OPTIONAL)
C10.2 F
RESET
(a) (b)
TIME
54 mSEC
2.25V2.5V
VCC
RESET
RHYST(OPTIONAL)
VCC
FIGURE1
most Cs and oth er digital circuits.
Low p ower consum ption distinguishes this circuit. Th e
IC typically draws only 5 A, and the R1/R
2divider draws
slight ly more than 1 A in a 2.7V application . Pullup resis-
tor R3
consumes power only when the supply vol tage
droops ou t of tolerance, so th e power loss is minim al in no r-
mal operation.To preven t erratic behav ior, IC1
offers approximat ely 6 m V
of built-in hysteresis. For more hysteresis, you can add a
large-value resistor, RHYST
, between th e ICs in put an d ou tput;
to reject sh ort tran sient s, IC1
has an inherent glitch imm
nity of 35 sec with 1 00 m V of overdrive. The inp ut capa
itance works with R1
and R2
to provide some lowpass-fil
act ion. For further immunity from transients, which
un n ecessary unless th e power bus is n oisy, you can form
addition al lowpass filter by addin g a sm all-value capacit
CG, to th e input pin. (DI #2174)e
To Vote For This Design, Circle No. 419
The circuit in Figure 1 is an easy-to-make attention-getter
an d ru n s for a week or longer on two AA cells. In September,
I used th is circuit for a sch ool fun draiser, an d it h elped m e
generate mo re than $100. My dad showed m e a circuit in
EDN that did the same thing, but it uses more parts (see
Alternating LED flasher uses minimal parts, EDN, Nov 20,
1997, pg 104).
The main element of this circuit is LED1, a Radio Shack
276-036 b linkin g red LED. D1 can be almo st any silicon diode.The forward bias of D
1brings th e turn -on voltage of LED
2up
to 2.5V. R1
is a current-limit resistor for LED1, and this resis-
tor also redu ces th e curren t of LED1
for lon ger battery life.
LED2
is a Radio Shack 276-041 red LED. Wh en you apply
power, LED1
turns on and drops the voltage across LED2
to
1V. When LED1
tu rn s off, th e voltage across LED2
equa ls 3V,
an d LED2
turns on . (DI #2172) e
To Vote For This Design, Circle No. 420
R182
D1
BLINKER
LED1RADIO SHACK
276-036
LED2RADIO SHACK
276-041
5VFIGURE1
Alternating LED blinker uses four partsANDY MENG, CINCINNATI, OH
This blinking-LED circuit, designed by a seventh grader, usonly four parts.
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EDN DESIGN IDEAS
Spice generates PSK and FSK signalsDEBRA HORVITZ, GALAHADSYSTEMS, LAGUNA HILLS, CA
LISTING1ISSPICE4SUBCIRCUITFORPSKSOURCE
Creating generators for am plitude-, fre-quency-, and phase-modulated signals
can greatly simplify communication-
sys tem s imula t ion. Al though Spice
includes a basic set of waveform gener-
ators, it includes n o bu ilt-in suppo rt for
m an y types of signals. You m ust create
th ese signals from comb ination s of ele-
m ent s, and you can create variation s of
th ese built-in generators using Spice 2-
dependent sources. However, using
depen den t sources to generate com plex
waveforms can require fairly complex
Spice subcircuits.
Fortu n ately, the n on linear, arbitrarydependent sourcethe B elementin
Berkeley Spice 3 an d IsSpice4 (Int usoft,
San Pedro, CA) provides a quantum
leap in capability over Spice 2-depen-
dent sources. The B element is more
versatile an d easier to use. For exam ple,
Listin g 1 is the IsSpice4 sub circuit for a
parameterized phase-shift-keying (PSK) source; Listing 2 is
the subcircuit of a parameterized frequency-shift-keying
(FSK) source. Figu re 1 shows the resultant outpu t signals of
each subcircuit gen erator.
The PSK subcircuit p rod uces a coh eren t bin ary PSK signal
according to the following equations:
wh ere EB is the tran smitted en ergy per bit, TB is the bit d ura-
tion, and f is the transmission frequency equal to NC/TB.
(NC is an integer constan t, and t h e period is 2TB; th us, th e
duty cycle equals 50%.) In Listing 1 , the input voltage
source, VSIG, produces the polar form of the input signal.
Usin g the B1 elemen t, th e subcircuit mu ltiplies this in pu t by
the local oscillator voltage, VLO1, to produce the PSK out-
put signal.
The subcircuit, FSK, produces a coherent binary FSK sig-
nal according to the following equations:
where f1
is th e high-bit transm ission frequ ency, an d f2
is t
low-bit tran smission frequ ency. Th e frequency, f1, is equ al
NC+1/TB. The frequency, f2, is equal to NC+2/TB. For si
plicity, two pulse generators, VSIG and VSIGN, produce t
input signal, m(t), and the inverse of the message sign
M(t), respectively. Again, using the B1 element, the subc
cuit code multiplies these signals by the appropriate fr
qu ency gen erator: VLO1 for logic h igh an d VLO2 for log
low. The sum of th e resultan t signals produces th e FSK ou
pu t signal. (DI #2173) e
LISTING2SUBCIRCUIT FORFSKSOURCE
FIGURE1
PSK SIGNAL
(2V/DIV)
TIME (SEC))
FSK SIGNAL
(2V/DIV)
0
0
50 150 250 350 450
22s (t) ft),2 EB
TB= sin(
212s t ft EB
TB( ) sin( ),=
2s (t) f t),12 EB
TB 1= sin(
2s (t) f t).22 EB
TB 2= sin(
The behavioral and m athem atical capabilit ies of Spice 3 and IsSpice 4 make it eato create PSK and FSK signals.
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EDN DESIGN IDEAS
Because of the low frequencies involved, accurately mea-
suring line-frequency variations is complicated. When you
use an ordinary frequency coun ter with a 1-sec gate time,
the reading would be 59, 60, or 61 Hz. To obtain 0.01-Hzaccuracy, you m ust in crease th e gate time to 100 sec, a scale
th at m ost frequen cy count ers do n ot o ffer. Moreover, read-
ing updates are slow with this scale choice. One way to
imp rove reading accuracy witho ut sacrificing up date tim e is
to use a frequency multiplier. For instance, a frequency
coun ter with a 1 -sec gate tim e could pro vide 0.01-Hz accu-
racy if you m ultiply th e lin e frequ ency by 100. Tradition al-
ly, you would configure the multiplier by using a VCO, a
PLL, a frequen cy divider, an d a low pass filter. Figu re 1 shows
anoth er method, using on ly one componen t , to mu lt iply
the line frequency.
The PIC12C508 is an eigh t-pin, low-cost C. It has a built-
in 4-MHz oscillator an d a reset circuit; it th us n eeds no exter-
nal components. One of the Cs un iqu e features is its soft-ware-based clock-frequency cal ibrat ion. The control ler
dedicates on e register, OSCCAL, to th e calibration fun ction.
The up per 4 b its of OSCCAL accom m odate 1 6 steps of cali-
bration. Each step changes the clock frequency approxi-
mately 1.6%. The m aximu m change is approximately 25%.
The line signal routes to the Cs GP3 pin. W hen the con -
troller detects a low-to-high change in GP3, the program
generates 100 pulses on GP5 and ign ores the cond ition of
GP3 (Listing 1). It th en rechecks the status of GP3. A high
value for GP3 means that the pulse generation is too slow;
OSCCAL then increases by one step. If GP3 is low, then a
coun ter operates un til GP3 goes h igh.
The number in the counter represents the delay (t
between th e last pulse and th e next line-signal chan ge. T
C comp ares tW
with a fixed n um ber. If tW
is larger than th
n um ber, indicating th at th e clock frequency is too h igh , t
value in OSCCAL decreases by on e step to slow d own . Ifis smaller than the fixed number, the value in OSCCA
increases by on e step to speed up. Thu s, th e autom atic cloc
frequency adjustment continuously sends a signal at 1
times the line frequency. Note that, because of the calibr
tion range, this approach has a limited input-frequen
range. However, it accommodates line-frequency measur
m ents from 58 to 62 Hz. You can d own load th e assemb
code from EDNs Web site, www.edn m ag.com . At th e reg
tered-user area, go in to th e Software Center to down load t
file from DI-SIG, #2182 . (DI #2182) e
To Vote For This Design, Circle No. 422
Frequency multiplier improves line readingsYONGPINGXIA , TELDATA INC, LOSANGELES, CA
An inexpensive C, using no external components, allows yto measure line frequency wit h 0 .01-Hz accuracy.
LISTING1PIC12C508CODE FOR LINE-FREQUENCY MEASUREMENT
PIC12C508
VDD
GP5
GP4
GP3
VSS
GP0
GP1
GP2
OUTPUT
INPUT
5V
8
7
6
5
1
2
3
4 OUTPUT
INPUT
100 1001 2 1 23 4
tW
FIGURE1
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EDN DESIGN IDEAS
In analog-circuit design, most calculations you make needn ot be very precise. If you n eed an LED-curren t calculation
or a coupling-capacitor value, for example, 5% or even
10% accuracy is usually adeq uate. Its sometim es incon ve-
n ient to m ake these calculations with a pocket calculator. Fexamp le, fin din g th e cutoff frequen cy of a 3.3-k/47-pF n e
work requires approximately 20 key presses. The circul
slide rule using the patterns in Figu res 1 through 4 simp
Circular slide rule provides quick resultsJACEKPAWLOWSKI, PW INMEL, ZIELONA GORA, POLAND
This wheel, using transparent mat erial, gives current values of 1 nA to 1 00A.
FIGURE1
V
R
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EDN DESIGN IDEAS
This wheel, an opaque background, gives voltage, current, power, and dissipation-factor percentages. The inner rows gistandar d EIA resistance values.
fies such calculations. The slide rule uses on e large, op aque,
dou ble-sided wh eel and two sm aller, transparen t wh eels.
You can m ake the op aqu e wheel by gluin g back-to-back
the p attern s in Figu res 2 an d 4 . For th e transparen t wh eels,
you sim ply photo copy the patterns in Figu res 1 an d 3 onto
overhead -transparency foils. To attach th e wh eels, you c
use a rivet or a screw and n ut. Using side A (Figures 1 an
2), you can calculate resistance (V/I), power (VI), and pe
centage products (=X, where is a percentage). X can
voltage, curren t, po wer, or resistan ce. Side A also gives sta
FIGURE2
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EDN DESIGN IDEAS
This wheel, copied ont o t ransparency material, gives capacit ance values from 1 pF to 10 mF (10 ,000 F).
dard EIA values for resistan ce.
On side B (Figu res 3
an d4)
, you can calculate the folloing formulas:
= RC,
F1
2 RCC =
,
XC fC=1
2,
FRES LC=
1
2,
Tf
=1
.
FRES LC=
1
2,
FIGURE3
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EDN DESIGN IDEAS
This wheel, the opaque backing for the wheel in Figure 2, relates resistance, frequencies, and time constants to the capatance values on t he wheel in Figure 3.
An y quan tity can b e the un known . For example, you can
calculate
You can m odify the slide rule to in corporate th e formu
you u se most often . Th e design o f the slide rule uses Aut
CAD LT. (DI #2 137 ) e
To Vote For This Design, Circle No. 423
L 2RES
2(F ) C=
1
4,
C 2RES
2(F ) L=
1
4.
FIGURE4