Electronics Ielectronics-2.weebly.com/uploads/1/3/0/5/13056901/fet_lectures.pdf · Electronics I...

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Electronics ILecture 28

Introduction to Field Effect Transistors (FET’s)

Muhammad TilalDepartment of Electrical Engineering

CIIT Attock Campus

COMSATS (Rev. 1.0)

The COMSATS logo and “COMSATS” is the property of CIIT, Pakistan and subject to the copyrights and ownership of COMSATS. Duplication & distribution of this work for Non Academic or Commercial use without prior permission is prohibited.The theme of this presentation is an inspiration from the one used in S2 Department of Chalmers University of Technology, Gothenburg, Sweden.

Last Time

• BJT Design Operations.

– Fixed Bias Configuration.

– Emitter Stabilized Bias Configuration.

– Voltage Divider Bias Configuration.

• Concepts– Determination of Collector Resistance, RC.

– Determination of Emitter Resistance, RE.

– Determination of Base Resistance, RC/R1/R2.

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Session Overview


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Topic Introduction to FET’s.

ConceptsBJT vs FET, FET Types, FET Construction, FETOperation, Pinch off.

RecommendedReading

Sections ?? Of [1]

KeywordsFET, BJT, Current Controlled, Voltage controlled,JFET, MOSFET, Gate, Source, Drain, Pinch off.

BJT Vs FET (1)

• BJT is a current controlled device– Base current (IB) controls the collector current

(IC).– This implies IC is a direct function of IB.

• FET is a voltage controlled device.– Gate to Source voltage (VGS) controls the

current I.– This implies I is a direct function of VGS.

• BJT is a bipolar device– Both electrons and holes constitute the current.

• FET is a uni-polar device.– Only electrons (n- channel) or only holes(p-

channel) constitute the current.


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Bipolar Unipolar

Thomas L. Floyd, Electronic Devices (Conventional Current Version), 7th Edition, Pearson Education Inc, ISBN: 978- 81- 7758- 643- 5.

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BJT Vs FET (2)

BJT• Low Input Impedance.

• More sensitive to the changes in the applied signal.– Change in output with input change

is greater.

• Less temperature stability.

• Larger in size

FET

• High Input Impedance.

– Important for linear ac amp design.

• Less sensitive to the changes in the applied signal.

• More temperature stable.

– Better suited in temperature sensitive applications.

• Smaller in size.– Better for IC manufacturing.


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Classification of FET’s


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• FET: Field Effect Transistor.• MOSFET: Metal Oxide Semiconductor Field Effect Transistor.• JFET: Junction Field Effect Transistor.

FET

MOSFET

Enhancement Type

Depletion Type

JFET

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JFET Structure

• Figure shows an n channel JFET.– Upper end is Drain.

– Lower end is Source.

– The p type regions are connectedtogether and called as Gate.

• For p channel JFET, the terminalsremain same but the n and p typematerials replace each other.


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JFET Structural Diagram

JFET Schematic Diagram


Basic Operation

• VDD provides – Drain to source voltage.– Current from drain to source.

• VGS sets – The reverse bias voltage between the

gate and the source.

• In JFET operation– The gate- source pn junction is always

reverse biased.– This reverse biasing produces a depletion

region along the pn junction.– This depletion region extends to n

channel and channel width & resistanceare increased.


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Thomas L. Floyd, Electronic Devices (Conventional Current Version), 7th Edition, Pearson Education Inc, ISBN: 978- 81- 7758- 643- 5.0

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Operating Conditions for JFET

• Three basic operating conditions for a JFET– VGS= 0, VDS at some positive value.

– VGS < 0, VDS at some positive value.

– Voltage controlled resistor.

• For n– channel JFET – VGS may never be positive.

• For p- channel JFET – VGS may never be negative.


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JFET Characteristics and Parameters

• When VGS = 0V and VDD is increased from 0 to more positive value

– The depletion region between p- gate andn- channel increases as electrons from n-channel combine with holes from p- gate.

– Increasing the depletion region decreasesthe size of the n- channel which increasesthe resistance of the n- channel.

– Even though n- channel resistance isincreasing, the current ID from source todrain from n- channel is increasing becauseVDS is increasing.


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Robert L. Boylestad, Electronic Devices and Circuit Theory,8th Edition, Pearson Education Inc, ISBN: 81-7808-590-9.

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Pinch Off

• If VGS= 0 and VDS is further increased tomore positive voltage, then thedepletion zone becomes so large that itpinches off the n- channel.

• The current ID should drop to 0A but itshows an opposite behavior- IDincrease with increasing VDS.


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Saturation

• At pinch off point– Any further increase in VGS does not

produce an increase in ID. VDS at pinchoff is denoted as Vp.

– ID is at saturation or maximum anddenoted as IDSS.

– The ohmic value of the channel ismaximum.


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VGS < 0V


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• As VGS becomes more negative– Depletion region increases.

– The JFET experiences pinch off voltage at alower voltage.

– ID decreases (ID<IDSS) even though VDS isincreased.

– Eventually ID reaches 0A. VGS at this pointis called VP or VGS (off).

– At high levels of VDS, the JFET reaches abreakdown situation. ID increasesuncontrollably if VDS > VDSmax.


VGS < 0V


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Voltage Controlled Resistor


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• The region to the left of thepinch off is called Ohmicregion.

• The JFET can be used as avariable resistor where VGS

controls the drain-sourceresistance (rd) . AS VGS

becomes more negative, rd

increases


References

[1] Thomas L. Floyd, Electronic Devices (Conventional Current Version), 7th

Edition, Pearson Education Inc, ISBN: 978- 81- 7758- 643- 5.

[2] Robert L. Boylestad, Electronic Devices and Circuit Theory, 8th Edition,Pearson Education Inc, ISBN: 81-7808-590-9.


COMSATS

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Electronics ILecture 29

JFET’s Transfer Characteristics

Muhammad TilalDepartment of Electrical Engineering

CIIT Attock Campus

COMSATS (Rev. 1.0)

The COMSATS logo and “COMSATS” is the property of CIIT, Pakistan and subject to the copyrights and ownership of COMSATS. Duplication & distribution of this work for Non Academic or Commercial use without prior permission is prohibited.The theme of this presentation is an inspiration from the one used in S2 Department of Chalmers University of Technology, Gothenburg, Sweden.

Last Time

• Introduction to FETs.

– Comparison with BJT.

– Classification of FETs.

– Structure of JFET’s.

– Operation of JFET.


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Session Overview


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Topic JFET Transfer Characteristics and DC Biasing.

ConceptsShockley’s Equation, Transfer Curve, Application ofShockley’s Equation, FET DC Biasing.

RecommendedReading

Section(s) ?? of [1]Section(s) ?? of [2]

Keywords JFET, Shockley, Gate, Source, Drain, Pinch off, VGS.

Transfer Characteristics

• For BJTs IB and IC are related by β– IC = β IB.

– It is a linear relationship where β is constant.

• For JFET the transfer characteristics of input to output is not alinear and straightforward function.

• In JFET, VGS and ID are related by


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Where ID = Drain current.IDSS = Maximum drain current.VGS= Gate to source voltage.Vp = Pinch off voltage.

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Transfer Curve

• There are two approaches to be applied for the DC analysis.– Graphical.– Mathematical.

• Graphical approach is more direct and easier in terms of application.

• For graphical approach, two plots are required– Device characteristics plot.– Network equation plot.

‘The transfer characteristics defined by Shockley’s equation are unaffected by the network in which the device is

employed’.


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Transfer Curve


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Shockley’s Equation (Application)


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• The transfer curve can be obtained directly from Shockley’sequation

Shorthand Method (Shockley’s Eq)


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• The transfer curve can be obtained directly from Shockley’sequation

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Example


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• Example 5-1 (Boylestad):

Sketch the transfer curve defined by IDSS = 12 mA and Vp = -6V.

Example


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Sketch the transfer curve for a p channel device with IDSS = 4

mA and Vp = 3V.

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DC Biasing (Fixed Bias Confg)


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Fixed Bias Configuration


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Fixed Bias Configuration


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Shockley Equation Plot


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Graphical Solution


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Example


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Determine VGSQ, IDQ, VDS, VD, VG, VS for the given network.


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References

[1] Thomas L. Floyd, Electronic Devices (Conventional Current Version), 7th

Edition, Pearson Education Inc, ISBN: 978- 81- 7758- 643- 5.

[2] Robert L. Boylestad, Electronic Devices and Circuit Theory, 8th Edition, Pearson Education Inc, ISBN: 81-7808-590-9.


COMSATS

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