Electronic Circuits_Lab Manual

8/9/2019 Electronic Circuits_Lab Manual

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Laboratory Manual Workshop on SPICE and VHDL / Verilog

Pradeep H K, Dept. of ISE, Ajay Betur P, Dept. of ECE, J N N college of Engineering, Shivamogga 0

ELECTRONIC CIRCUITS AND LOGIC DESIGN LABORATORY

[06CSEL - 38 / 06ISEL 38]

? SEMESTER B.E. [CSE / ISE]

ELECTRONIC CIRCUITS LABORATORY MANUAL

ALONG WITH SIMULATION MODELS

DEPARTMENT OF ELECTRONICS &COMMUNICATION

JAWAHARLAL NEHRU NATIONAL COLLEGE OF

ENGINEERING

SHIVAMOGGA - 577204


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Experiment No 1.CLIPPING & CLAMPING CIRCUITS

Aim: To design and test the diode clipping (single or double ended) circuit for peak clippingand peak detection.

Components/Apparatus required:

1) Diodes - 1N4007 - 2 Nos.2) Resistor - l0K O3) Power supply (0 - 30V) - 2 Nos.4) AFO5) CRO

Theory:

These circuits are used to clip off portions of the voltages above and below certain levelsas per the requirements. So the circuits used to clip off unwanted portions of the waveform

without distorting remaining part of the waveform are called as clipping circuits. These areclassified into (a) Series clippers, in which the diode is connected in series with the load. (b)

Shunt clippers, in which diode is connected parallel to the load.

Design Procedure:

1. Diode shunt clipping above VRor Positive peak clipping:Let the output voltage be clipped to say + 2V.

Vo(max) = + 2 V.From circuit diagram of Fig. l(a),

Vo (max)=V?+ VR

Where V?= 0.6V for Si diode, is cutin voltage.VR=Vo (max) V?= 2 - 0.6 =1.4 V

The value of resistor R is chosen to be R= (RfRr) .Where Rf = diode forward resistance=10 O and Rr= diode reverse resistance=10 M O

R = (10 x 10 x 106) =10 KO

2. Diode shunt clipping below VR or Negative peak clipping:

Let negative peak voltage to be clipped at say -2VVo(min)=-2 V; Vo(min) = -2V =VRV?and R= R= (RfRr) =10 KO.VR= -2 + 0.6= -1.4V

3. Diode series clipping above V R or Positive peak clipping.

Let the output voltage be clipped at +2 V.

Vo(max) =VR= 2V and R= (RfRr) =10 KO.

4. Diode series clipping below VRor Negative peak clipping:

Let output voltage be clipped at -2V...Vo(min) = VR= -2 V and R = 10 KO.

5. Clipping at two independent levels or Slicer circuit:

To obtain a slice of input voltage between 2V and 4V levels at its output. Let VR1>VR2

v

v


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Vo(max) = 4V = VR1+V?; VR1 = 4 - 0.6 = 3.4VAlso Vo(min) = 2 V= VR2 - V?

VR2= 2 + 0.6 = 2.6 V and R=10 K O.6. Double ended clipper to generate a symmetrical square wave or squarer:

To generate a symmetrical square wave of VRvolts. When Vi= Vmsin ? tVo(max) = 2V = VR1+ V?VR1= 2 - 0.6 = l.4V and Vo(min) = VR2 - V?

VR2= Vo(min) + V?= -2 + 0.6 = -1.4V and R=10 KO.

7. Clipping circuit to clip the center portion and transmit the extremities of sinusoidal

signal: Refer Fig. 7 (a)To clip a sinusoidal wave between +2 V and -3V levelVo= VR1+ 0.6VVR1= 2 - 0.6 = 1.4VSimilarly Vo= -3V = VR2- 0.6 V

VR2 = -3 + 0.6 = -2.4V and R = 10 KO

Procedure:

1) The circuits are wired up for all the cases as shown in Fig. l(a), 2(a), 3(a), 4(a), 5(a),6(a) and 7(a). A sinusoidal signal of 1 KHz and amplitude of 12 Vp-p (peak amplitude

should be greater than clipping level) is applied as input Vifrom AFO.

2) Observe output waveform on the CRO and verify it with the given output waveforms.

3) Apply Vi and Vo to the X and Y channels of CRO and observe the transfercharacteristics of the circuit.

Results:

Output waveforms and transfer characteristics are verified.

CLAMPING CIRCUITS

Aim:To design and test the clamping circuits for positive and negative clamping.

Components /Apparatus required:1) Diode - IN 40072) Capacitor - 0.1 F3) Resistor - 100 KO4) AFO

5) CRO6) Power supply (0-30 V)

Theory:Some times it is necessary to add a DC level to the AC o/p signal. The circuits, which are

used to add a dc level as per the requirement, to the ac o/p signal, are called as clamping circuits.The capacitor, diode and resistance are the basic elements of a clamping circuit. The two types

are: (a) Positive Voltage Clamping, (b) Negative Voltage Clamping.


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Design Procedure:

1) Positive Voltage clamping:

a) Positive voltage clamping without reference:Given f = 1 KHz,

...T = 1 ms

Choose RC >> T, Let RC = 10 T = 10 ms

Let R = RfRr= 100KORC =10 ms; 100 KO x C =10 ms or C =0.1 F

This is same for all clamping circuits.Vo=Vi+ Vm. When Vi= 0, Vo= VmVi=Vm, Vo=2Vm; Vi= -Vm,Vo=0

b) Positive voltage clamping with positive reference:

Let Vo(min) = 2 VAnd Vo(min) = VR- V?

...VR= 2V + 0.6 = 2.6V

c) Positive voltage clamping with negative reference:

Vo(min) = 2 V; Vo(min) = VR- V?...VR= Vo(min) + V?

VR = -2V + 0.6= - l.4V

2) Negative Voltage clamping:a) Negative voltage clamping without reference:

Vo= Vi - VmWhen Vi= 0, Vo= -VmVi= Vm, Vo= 0

Vi = - Vm, Vo= -2Vm

b) Negative voltage clamping with positive reference:Vo(max) = 2V

= VR + V?...VR= 2V - 0.6 V = 1.4 V

c) Negative voltage clamping with negative reference:Vo(max) = - 2V

= VR+ V?...VR= - 2V - 0.6 = -2.6 V

Procedure:

1. The circuits are wired up for all the cases as shown in Fig. l(a1), 1 (b1), 1 (c1), 2(a1),2(b1) and 2(c1). A sinusoidal signal of 1 KHz and amplitude of 10 Vp-p is applied asinput Vifrom AFO.

2. Observe the output waveforms on the CRO and verify it with the given waveforms.

Result:The output waveforms are verified.

v


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Clipping - Shunt

Vr1.46V

R1

10kohm

D11N4007GP

A BT

G

XSC1

V26V 1kHz 0Deg

Diode Shunt Clipping above Vr (or)Positive Peak Clipping

Output:


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Transfer Characteristics

Clipping Series

Vr2V

Vi6V 1000Hz 0Deg R110kohm

D1

1N4007GP

A BT

G

XSC1

Diode Series Clipping above Vr (or)

Positive Peak Clipping


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Output:



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Double ended clipping

VR1

1.4V VR2

1.4V

Vi

6V 1000Hz 0Deg

R1

10kohm

D1

1N4007GP

D2

1N4007GP

A BT

G

XSC1

Double ended clipper to generatea symmetrical square wave

2

4

0

1

5

Output:


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Clipping at two independent levels

VR1

3.4V

VR2

2.6V

Vi6V 1000Hz 0Deg

R1

10kohm

D11N4007GP

D21N4007GP

A BT

G

XSC1

Clipping at two independent levels (or)Slicer Circuit


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Output

Transfer characteristics


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Clamping without reference

Vi5V 1000Hz 0Deg R1

100kohm

C1

100nF

D11N4007GP A B

T

G

XSC1

Positive Voltage Clampingwithout reference

Output


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Clamping circuit with positive reference

Vi5V 1000Hz 0Deg

R1100kohm

C1

100nF

D11N4007GP A B

T

G

XSC1

VR2.6V

Positive voltage clamping withpositive reference

Output


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Clamping with negative reference

Vi5V 1000Hz 0Deg

R1100kohm

C1

100nF

D11N4007GP

A BT

G

XSC1

VR1.4V

Positive voltage clapming withnegative refernece

Output


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Experiment No. 2RC COUPLED AMPLIFIER

Aim: To design single stage RC Coupled BJT amplifier and to determine the gain, frequencyresponse, input-output impedance.

Components/ Apparatus required:

1) Transistor - BC 107B2) Resistors3) Capacitors4) AFO5) CRO6) Power supply

Theory:An RC coupled amplifier has moderately low input resistance (1 KO to 2 KO) and its

output resistance is moderately large (50 KO). It produces a phase reversal of input signal i.e.,input and output signals are 1800out of phase with each other. The circuit diagram in Fig. 1

shows a single stage RC Coupled amplifier using an NPN transistor. Here, base is the drivenelement. The input signal is injected to the base-emitter junction and the output signal is taken

across the collector-emitter circuit. VB forward biases the emitter-base junction. VCC reversebiases the collector-base junction.

Design Procedure:Select transistor BC107B having the following specifications: IE=IC=2 mA, =215, VCE=5V

Selection of RE:

VCC= 10V; VE= VCC / 10; VE= 10/10 = 1.0 V

VE= IERE; RE= VE/IE; RE=1.0 / (2 x 10-3)

RE= 0.500 KO;Select RE= 500 O

Selection of RC:VCE= VCC/ 2; VCE= 10/ 2 = 5V, by apply Kirchoffs Voltage Law to output

loop,VCC= ICRC+ VCE+ VE

RC= (VCC VCE VE) / ICRC= (10 5 1) / (2 x 10

-3)

RC= 2 KO;Select RC = 2.2 KO

Selection of R1and R2:VB= VBE+ VE; VB= 1.7V;VB= (VCCx R2) / (R1 + R2)

1.7=10 x R2 / (R1 + R2); R2 / (R1+R2) = 1.7 / 10;10R2= 1.7 R1+ 1.7 R2; R1= 4.8 x R2;

Choose R2= 4.7 KO; R1= 4.8 x 4.7K;R1= 22.56 KO;Choose R1= 22 KO


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Selection of bypass capacitor CE:

Let XCE= RE /10; At f = 100Hz, 1/ (2pfCE) = RE / 10CE= 59F;choose CE= 50F.

Selection of coupling capacitors:Select CC1= CC2= 0.47F

Procedure to find the Frequency Response:

1) Connections are made as shown in the Fig 1.

2) Find MSHC (Maximum Signal Handling Capacity is the maximum input at which theoutput is undistorted) of the circuit.

3) Select the input voltage Viof AFO such that Vi= MSHC.

4) Select the frequency of AFO around 10 Hz and note down the output voltage Vo.

5) Vary the frequency of AFO in steps till 100 KHz and note down VOin each step. Keepthe input voltage of AFO constant as selected in step 3.

6) Plot the graph of gain in db v/s frequency.

Procedure to measure input impedance Zi:

1) Connect the circuit as shown in Fig 3.

2) Set the potentiometer (10 KO) resistance Riconnected at the input to zero.

3) Select the amplitude of the AFO as in Step 3 of procedure of finding the frequencyresponse. Set the frequency of AFO at a mid band frequency, say 10 KHz.

4) Measure the output amplitude (say Va).

5) Increase the potentiometer resistance till the output voltage is Va/ 2. Then, thecorresponding resistance value Riis the input impedance Zi.

Procedure to measure input impedance Zo:

1) Connect the circuit as shown in Fig 4.

2) Set the potentiometer (10 KO) resistance Roconnected at the output to zero.

3) Select the amplitude of the AFO as in Step 3 of procedure of finding the frequencyresponse. Set the frequency of AFO at a mid band frequency, say 10 KHz.

4) Measure the output amplitude (say Vb).

5) Increase the potentiometer value till the output voltage is Vb/ 2. Then, thecorresponding resistance value R0is the output impedance Zo.


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Results:

Band width : _________ Hz

Input Impedance : _________ O

Output Impedance : _________ O

OBSERVATION

Figure 2. Frequency response

Figure 3. Circuit to find input impedance

Figure 4. Circuit to find output impedance

Gain in db

0

3db

f1 f2

Band Width

RCcoupled

amplifier

circuit

~ Vo(CRO)

RC

coupledamplifier

circuit

~ Vo (CRO)Ro


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Tabular ColumnMHRC = Vi=

Sl. No. Frequency in Hz Voin Volts Vo/ Vi Gain in db= 20

log (Vo/Vi)

Table 1.

Circuit diagram

Common Emitter Amplifier

R122kohm

R24.7kohm

Rc2.2kohm

C1

0.47uF

C2

0.47uF

Ce

47uF

Q12N2222A

outin

XBP1

R322Mohm

A BT

G

XSC1

V11mV 1000Hz 0Deg

V210V

Re470ohm

CE Amplifier

3

1

0

5

7

0

8

0

6

e

bc

BC107

notc

e - Emitterb - Base

c - Collector


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Output

AC Analysis (Output voltage v/s frequency, Phase v/s

frequency)


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Frequency response


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Experiment No 3.

MOSFET CHARACTERISTICS

Aim: To determine the drain characteristics & trans-conductance characteristics of anenhancement mode MOSFET and to implement a CMOS inverter using p-spice.

Components/ Apparatus Required:1) MOSFET2) Power supply (0-30V)3) CRO

Theory:1. The Metal Oxide Semiconductor Filed Effect Transistor (MOSFET) are majority

carrier devices.

2. MOSFET has three terminals: Gate (G), Drain (D), Source (S).

3.

Voltage is applied between Gate to Source to turn On the MOSFET. When theMOSFET is turned On, the current flows from Drain to Source.

4. The MOSFET can be turned Off by removing he Gate to Source voltage. Thus Gate

has full control over the conduction of the MOSFET.

5. The turn on & turn off times of MOSFET are very small. Hence they operate at very

high frequencies.

6. MOSFETs are mainly used for low power applications.

7. MOSFETs have very simple drive circuits.

8. MOSFET do not require commutation circuits.

Procedure:1. Rig up the circuit as shown in Fig. 1.

2. Adjust the value of VGS=0V, and vary VDS and note down the corresponding ID.

Repeat the same for different values of VGS. Plot the graph b/w VDSand ID. This gives

the output characteristics. Refer Fig. 2.

3. Keep VDS=5V. Vary VGSand note down the corresponding ID. Plot the graph of VGS

v/s ID. Repeat the same for different values of VDS. This plot is the input

characteristics of MOSFET. Refer Fig. 3.

4. From the plots find the following parameters.

Drain Resistance rd=? VDS/ ?IDfor constant VGS

Mutual conductance gm= ? ID/ ?VGS for constant VDS

Amplification factor ()= gmrd


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Results:Static characteristics of MOSFET is obtained.

Amplification factor of MOSFET is calculated

IRF740 Device Specifications:1. VDSS Drain to Source breakdown voltage : 400 Volts

2.

Rds(on) On state Resistance : 0.55 ohms

3. ID Continuous drain Current @ 250 C : 10 Amps

4. ID Continuous drain Current @ 1000 C : 6.3 Amps

5. Pdmaxmaximum Power dissipation @ 250 C : 125 Watts

Circuit Diagram:


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Tabular Column

Output Characteristics

VGS= 0V VGS= 0.5 V

VDS

V ID

mA VDS

V ID

mA

Input Characteristics

VDS= 0V VDS= 10 V

VGSV IDmA VGSV IDmA

To implement a CMOS inverter using a simulation package& verify its truth table

For n-MOSFET For p-MOSFET

nMOSFET: IRF530 pMOSFET: IRF9530

Case : To220(F) Case: To220(F)

Ptot : 750 watt Ptot : 750 watt

VDS : 100V VDS : - 100VVDG : 100V VDG : - 100V

VGS(th) : +4V VGS(th) : - 4V

IGSS : 500nA IGSS : - 500nA

IDSS : 1mA IDSS : - 1mA

gfs(ms): 3000 gfs(ms): 2000

ID(max): 10A ID(max): -7A

G

D

S

G

D

S


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CMOS inverter

M1MOS_3TDP_VIRTUAL

M2MOS_3TEN_VIRTUAL

5VVDD

V11000Hz 5V

QC T

1

F

XLA1

CMOS Inverter

Output


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Experiment No 4.SCHMITT TRIGGER

Aim: a) To design Schmitt Trigger for the given specifications

Components/ Apparatus Required:

1) OP-AMP - A74l2) Resistors lKO, 12KO or 10 KO3) Power supply (0 - 30V), ( l2V)4) AFO5) CRO

Theory:

There are the circuits which compare the input signal with reference signal, out of two

inputs, one is kept at reference voltage and a linear signal is applied to the other terminal. Ateach time the Vicrosses reference voltage, output will change from one level to other level

Vi< Vref, Vo= + Vsat

Vi> Vref, Vo= - Vsat

The input voltage Vi triggers the output Vo, every time it exceeds certain voltage levelscalled the Upper threshold voltage (UTP) and Lower threshold voltage (LTP). The thresholdvoltages are obtained by using voltage divider R1- R2, Where voltage across R2is fed back to the(+) input. When Vo= +Vsat, the voltage across R2is called UTP and When Vo= -Vsat, the voltage

across R2is LTP.

Design Procedure:Design a Schmitt Trigger for upper threshold voltage UTP = 3V and lower threshold

voltage LTP = 1V and V sat = 12V

UTP = {R1 / (R1+R2)}VR+ (R2 / (R1+R2)}Vsat (1)

And LTP = {R1 / (R1 + R2)}VR- {R2 / (R1 + R2)} x Vsat (2)

...UTP +L TP = 2R1 / (R1 + R2)VRor 4V = 2R1/(R1+R2)VR (3)

Similarly UTP - LTP = 2R2/ (R1= R2) x Vsator 2V =2R2/ (Rl+R2) x Vsat (4)

Or 1V =R2(12V) /R1+R2 OR R1+R2=12R2 OR R1=11R2 (5)

Substitute (5) in (3)

...4V =2VR/(11 R2+R2) x 11R2 Or 2 = 11R2(VR) /12R2 or VR = 2.18V

...Choose R2=l KO, R1=11R2=11KO, Select 10KO or 12KO

A74lVref

Vi

+

--

+Vsat

-Vsat


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Procedure:1. Connections are made as shown in the Fig 4.2. Apply sinusoidal signal of 10Vpp at 1KHz as an input from AFO.3. Observe the output rectangular waveform on the CRO (DC mode) and measure UTP

and LTP and peak values of output.

4. Use X - Y mode to observe the transfer characteristics or hysterisis curve on CRO.

Measure UTP and L TP and compare it with the designed values.(X - Channel-Vi, Y - Channel-Vo)

Result:

Theoretical UTP : ______________

Practical UTP : ______________

Theoretical LTP : ______________

Practical LTP : ______________

OBEVATIONS:

Circuit Diagram

A

7

4

l

NC NC

1 8

2

3

4

7

6

5

INV I/P

NON INV I/P

- VS

+ VS

O/P

Offset null

Pin details of A741.

A74lVref

Vi

+

--

+12V

-12v

3

2 4

7

6

Symbol of A741.


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Schmitt Trigger

U1

741

3

2

4

7

6

51

BAL1BAL2

VS+

VS- R111kohm

R21.0kohm

V112V

V2

1V 1000Hz 0Deg

V312V

A BT

G

XSC1

outin

XBP1

Schmitt Trigger

0

2

0

3

0

0

5

7

1

Output


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Transfer characteristics

\


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Experiment No 5.

Relaxation Oscillator using Op - Amp

Aim: To design and implement a rectangular waveform generator (Op-Amp Relaxationoscillator) for given frequency.

Components/ Apparatus Required:1) Op-Amp A7412) Resistors R1=R2=100KO, R3=10KO (Variable Pot)3) Capacitor C= 0.01F4) Power supply (5V)3) CRO

Theory:Below figure shows the Op-Amp relaxation Oscillator. In relaxation oscillator non-

inverting i/p is biased at voltage (V/2) where V is the output voltage. The inverting i/p, chases

this value from below and when it reaches it, o/p voltage changes from one saturation level to the

opposite one. The o/p is a square wave, with a frequency of 1/ (2R3C) and duty cycle of 50% ifthe saturation levels are symmetrical.

Procedure:1. Circuit connections are made as shown n the figure.

2. Observe the o/p at pin no. 6 of Op-Amp.

3. Output waveforms are square waves.

4. Measure the frequency of the square wave and compare with the designed value.

5. Change R3 to 2R3 and once again measure the frequency of the output square wave.

6. Compare the present and past frequencies.

Design Procedure:1. R1and R2can be of any value ranging from 1KO 1 MO and in this design let us

choose R1=R2= 100KO.

2. Let us also assume C = 0.01F

3. With reference to above mentioned theory, o/p of the Op-Amp is square wave with

frequency,f = 1/(2R3C).

4. Now let us assume frequencyf= 5 KHz.

Then R3= 1/ (2 x f x C)

= 1/ (2 x 5 x 103x 0.01 x 10-6)

R3 = 10 KO

Result:From this experiment we can observe that when the resistor value (R3) is doubled,

frequency becomesf /2.

Circuit diagram:


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Relaxation Oscillator using Op-Amp

U1

741

3

2

4

7

6

51

BAL1

BAL2

VS+

VS-

V15V

V25V

A BT

G

XSC1

R1

100kohm

R2100kohm

C1

10nF

R3

10kohm

Relaxation Oscillator using Op-Amp

Output


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Experiment No 6.

ASTABLE MULTIVIBRATOR USING IC555 TIMER

Aim: to design and implement an astable multivibrator circuit using 555 timer for givenfrequency and duty cycle.

Components/ Apparatus Required:1) IC 5552) Resistors: RA=RB=7.5KO3) Capacitors C= 0.1F and Bypass Capacitor C=0.01F4) Power supply (5V)5) CRO

Theory:Popular analog-digital integrated circuit is the versatile 555 tier. The IC is made of

combination of linear comparators and digital flip-flops as described (in figure (a)). The entire

circuit is usually housed in an eight pin package as specified in fig. A series connection of theeresistors sets the reference voltage levels to the two comparators as 2Vcc/3 and Vcc/3, the outputthese comparators setting or resetting the flip-flop unit. The output of the flip-flop circuits is thenbrought out through an amplifier stage. The flip-flop circuit also operates a transistor inside the

IC, the transistor collector usually begin driven low to discharge a timing capacitor.

Astable Operation:

One popular application of the 555 timer IC is as an Astable Multivibrator or clock unit.The following analysis of the operation of the 555 as an astable circuit includes details of the

different parts of the unit and how the various inputs and outputs are used. Figure (a) shows an

astable circuit built using an external resistor and capacitor to set the timing interval of the outputsignal.

Capacitor C charges toward Vccthrough external resistors RAand RB. Referring to figure

(a), we see that the capacitor voltage rises until it goes above 2Vcc/3. This voltage is the thresholdvoltage at pin 6, which drives comparator 1 to trigger the flip-flop so that the output at pin 3 goeslow. In addition, the discharge transistor is driven on, causing the output at pin 7 to discharge the

capacitor through resistor RB. The capacitor voltage then decreases until it drops below thetrigger level (Vcc/3). The flip-flop is triggered so that the output goes back high and the discharge

transistor is turned off, so that the capacitor can again charge through resistors RAand RBtowardVcc.

Calculation of the time intervals during which the output is high and low can be made using therelations

Thigh 0.7 (RA+RB) C Eq (1)

Tlow 0.7 RBC Eq (2)


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The total period is

T= period = Thigh + Tlow Eq (3)

The frequency of the astable circuit is then calculated using

f = 1 1.44___

T (RA+2RB)C

Duty cycle:

The ratio of High output period to the total time (sum of High time and Low time) iscalled as duty cycle.

Duty Cycle = (Thigh/ T) x 100

Design Procedure:

We know that capacity voltage raises until [2VCC/ 3] and remaining is discharging period

[i.e. [VCC/3]]

Now let us considerT= 1.575 msec f = 1 / T = 1.44/ (RA+ 2RB) C = 635 Hz

Now let us assume that Thighis = 1.05 msec

Tlow = T- Thigh= 1.575 msec 1.05 msec= 0.525 msec

And let us also assume C=0.1 F

Then Tlow = 0.7 RBC=> RB = Tlow / 0.7 C = 7.5KO

Similarly Thigh = (0.7 (RA+RB) C

=> RA = (Thigh- 0.7RBC) / 0.7C= 7.5KO

T= Thigh+ Tlow= 1.05 ms + 0.525 ms= 1.575 ms

f = 1 = 1 ~ 635 Hz

T 1.575 x 10

-3

Result:

The given waveforms and duty cycles are verified.


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Circuit Diagram:

Astable multivibrator using 555 timer

U1

1

DIS

7OUT

3

RST

4

8

THR

6

CON

5

TRI

2

GND

VCC

LM555H

R17.5kohm

R27.5kohm

C1100nF

C2

10nF

A BT

G

XSC1

5VVCC

Astable Multivibrator using 555 timer

Output


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Experiment No 7.

Voltage Regulator using IC7805

Aim: To design and implement a Voltage regulator Using IC7805.

Components/ Apparatus Required:1) IC7805 1 No.2) Resistors 10KO - 1 No.3) Capacitor C1= 0.01F, C2= 250F4) Transformer - Power supply5) CRO

Theory:The series 78XXXX regulators provide fixed regulated voltages from 5V to 24V. An

unregulated i/p voltage Vi is filtered by a capacitor C1 and connected to the ICs IN terminal.

The ICs OUT terminal provides a regulated +5V, which is filtered by capacitor C2 (for high

frequency noise) third IC terminal is connected to ground (GND). Whereas the i/p voltage may

vary over some permissible voltage range and o/p load may vary over some acceptable range ,the o/p voltage remains constant with in voltage specified variation limits.

Procedure:1. Circuit connections are made as shown n the figure.

2. Observe the o/p voltage at pin no. 2(OUTPUT pin) of IC 7805.

3. Output is a regulated +5V.

4. Calculate the o/p ripple for different values of load current by varying value of C 2, by

making using the formula

r = (Vr(rms) / Vdc) x 100

5.

then once again change the load resistor RLin order to get different load current andone again calculate the ripple factor by making use of the above formula.

Result:Output is a regulated +5V.


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Circuit diagram:

Electronic Circuits_Lab Manual

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