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Electrocardiogram (ECG) application operation – Part A
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Transcript of Electrocardiogram (ECG) application operation – Part A
Electrocardiogram (ECG) application operation – Part A
Performed By: Ran GelerMor Levy
Instructor: Moshe Porian
Project Duration: 2 Semesters
Spring 2012
MidTerm Presentation
ContentsIntroTop ArchitectureOverviewData FlowComponentsSimulationsProblems in developing processConclusionsWhat’s nextSchedule
IntroThe heart is a muscular organ
that beats in rhythm to pump blood through the body
By analyzing the heart behavior and especially the electrical impulses we can help identify heart diseases and special circumstance that require
close monitoring
Medical TermsECGLead
◦Bipolar leads ◦Unipolar leads ◦Precordial Leads
Project Overview
Project GoalsPortable ECG device based on
FPGAIntegrating Multi Platforms
elements◦ECG DB with FPGA
Interactive GUI with debugger abilities
Methodic project
Top Architecture
OverviewAcquaintances with other
projects components◦SPI, Wishbone, RX/TX path, FIFO,
FlashImplemented ECG controller
◦ECG FSM◦Assimilation of SPI core & FIFO
Examination of the Implemented components
Top Architecture – Data Flow
Top Architecture – FrequencyFrequency requirements for modules
FPGA:
Main frequency: 100MHz
Rx / Tx Modules
@ frequency of 115,200Hz
ADS1928R:
Main frequency: 2.048MHz
SPI-Data Out freq’: >110KHz
MATLAB GUI:Rx / Tx Via UART interface
@frequency of
115,200Hz
Flash Memory:
Main frequency: 100MHz
Core microarchitecture
512Bytes
Data Rate: 100MHz
Data Rate :
>110KHz
Core Architecture ECG FSMFIFOCommand & Aux RegsWishbone Master & SlaveSPI Core
ECG FSMControls the flow of data between
the host and the DBThree Main chain of actions:
◦Read Data◦Read Registers◦Write Registers
ECG FSM - Graph
FIFO at ECG Controller
1st Command
2nd Command
Additional Data
Operation Commands (ex: RDATAC, Rreg, Wreg, Standby, Reset, ect’..)Optional: Second Byte for (Rreg, Wreg) and sample interval for RDATAC command.Data for commands
• FIFO Size: 512 Bytes.• Stores Instruction and Sampled data.• Data structure on Instruction case:
SPIThe SPI Interface frequency:
At 24bit resolution per 8 Electrodes and 500 Samples per Sec:
Active at low. i.e. CS = ‘0’
( 4 ) ( 24)SCLK DR CLK BITS CHANNELSt t t N N
110clockt KHz
1/DRt Sample Rate
Flash Component
FLASH
Flash Controller FlashFSM
RAM
Reset en
WBS
Flash Component
256Byte
Flash Component - FlashOne sample(24bit res. per 8 Electrodes)=
27Byte.Lets assume sample rate of 500
SPSFlash size = 4MBTherefore we can sample for
5min.
Flash Component – Flash client
Technical Demands:•Common FLASH Interface protocol (CFI)•Wishbone Interface•Performs Read, Write, Reset and Erase transactions•Initiative read on power-on•Contains a timeout algorithm•Generic: adaptable to different FLASH sizes and clock frequencies.
BUS
Wishbone
CFI
ADS1298R ECG DBTexas Instruments CardArrived to the High Speed Digital
Systems Lab
ADS1298R ECG DBFuture acquisitions of probes and
electrodesConnection of the DB
to the FPGA
Test MethodologiesOperation of the ECG Controller:
◦Checking that states change are at time◦Checking control signals & data signals
between units◦Non existing commands
NOTE: When a transaction is executed the wishbone “stall” signal is raised to ‘High’, So other requests will remain pending at the Rx Wishbone Master.
ECG Controller TB Data FlowWe have implemented a special closed
component for Testing.
ADS1298R ECG DB
Simulations – Read modeECG Controller Unit actionsReading samples from DB –
RDATAC command
25Bytes Bytes 15
SPI Received data
Simulations – Read registers
FSM St.
SPI MOSI
SPI MISO
FIFO DIN FIFO DOUT
• Read n nnnn registers starting at address r rrrr (001r rrrr, 000n nnnn)
• RReg cmd(0x2C): read 5 register from address 12.
Simulations – Read registersWishbone protocol
BUS Req.
Send data
END trans.
Simulations – Write registers
FSM St.
SPI MOSI
• Write n nnnn registers starting at address r rrrr (001r rrrr, 000n nnnn)
• WReg cmd(0x49): write 5 register from address 9
Simulations – Write registersReceived Data at Remote SPI
Slave
SPI MOSI
SPI Data out
Simulations - DBEntering Standby & then
Wakeup
Standby 0x04 Wakeup 0x02
Return to idle
• Wake-up from standby mode (0x02).• Enter standby mode (0x04).
Problems in developing processLack of VHDL writing techniques
Understanding imported components
Absences of decisiveness on one developing method
ConclusionsWe learned a lot about the
developing process & the importance of good planning a head
What’s NextCombining RX\TX path, ECG
controller and Flash component into Main VHDL component
Connecting the DB to the FPGABuilding test environment for
testing the Data flow from the electrodes throw the DB & FPGA to the MATLAB
Building the GUI
Schedule – Semester A remain work
Further simulation and final code release
Synthesis and P&R by Quartus
Semester A -Final Presentation
6.1
13.1
20.1
Schedule – Semester B
Ti ADS1928R DB and DE2 Board connection
Acquisition of electrodes
Building GUI using Matlab
Test
&
Debug
3w
3w
2w
Schedule – Semester B Cont.
Proj
ect
book
co
mpl
eti
on
Semester B -Final Presentation
2w
1w