ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn...

21
ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021 1 Instructor: Daniel Llamocca Unit 6 – Synchronous Sequential Circuits FUNDAMENTAL CIRCUITS ASYNCHRONOUS CIRCUITS: LATCHES SR LATCH: +1 + SR LATCH WITH ENABLE: +1 + + D LATCH WITH ENABLE: This is essentially an SR Latch with enable, where = (), = . The D Latch always has an enable input. +1 + S' R' Q Q R S E SRQ t+1 00 Q t 01 0 10 11 0 1 Q t+1 Q t 1 0 0 xx Q t Q t E 1 1 1 1 0 DQ t+1 0 0 1 1 x Q t E 1 1 0 S' R' Q Q D E S R Q Q SR Q t+1 00 Q t 01 0 10 11 0 1 Q t+1 Q t 1 0 0 restricted S Q Q R Q S R Q SR Latch

Transcript of ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn...

Page 1: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

1 Instructor: Daniel Llamocca

Unit 6 – Synchronous Sequential Circuits

FUNDAMENTAL CIRCUITS

ASYNCHRONOUS CIRCUITS: LATCHES SR LATCH:

𝑄𝑡+1 ← ��𝑆 + ��𝑄𝑡

SR LATCH WITH ENABLE:

𝑄𝑡+1 ← 𝐸��𝑆 + ��𝑄𝑡 + ��𝑄𝑡 D LATCH WITH ENABLE: ▪ This is essentially an SR Latch with enable, where 𝑅 = 𝑛𝑜𝑡(𝐷), 𝑆 = 𝐷. The D Latch always has an enable input.

𝑄𝑡+1 ← ��𝑄𝑡 + 𝐸𝐷

S'

R'

Q

Q

R

S

E

S R Qt+1

0 0 Qt

0 1 0

1 0

1 1 0

1

Qt+1

Qt

1

0

0

x x Qt Qt

E

1

1

1

1

0

D Qt+1

0 0

1 1

x Qt

E

1

1

0

S'

R'

Q

Q

D

E

S

R

Q

Q

S R Qt+1

0 0 Qt

0 1 0

1 0

1 1 0

1

Qt+1

Qt

1

0

0

restricted

S Q

QR

Q

S

R

Q

SR Latch

Page 2: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

2 Instructor: Daniel Llamocca

SYNCHRONOUS CIRCUITS: FLIP FLOPS

▪ Flip flops are made out of: o A Latch with an enable input. o An Edge detector circuit.

▪ The figure depicts an SR Latch, where the enable is connected to the output of an Edge Detector Circuit. The input to the

Edge Detector is a signal called 'clock'. A clock signal is a square wave with a fixed frequency.

▪ The edge detector circuit generates short-duration pulses during rising (or falling) edges. These pulses act as short-time

enables of the Latch. ▪ The behavior of the flip flops can be described as that of a Latch that is only enabled during rising (or falling edges). ▪ Depending on what type of edge we are detecting, flip flops can be classified as:

o Positive-edge triggered flip flop: The edge detector circuit generates pulses during rising edges. o Negative-edge triggered flip flop: The edge detector circuit generates pulses during falling edges.

o Dual-edge triggered flip flop: The edge detector circuit generates pulses during both rising and falling edges. Current FPGA technology does not support dual-edge triggered flip flops.

FLIP FLOP TYPES SR Flip Flop

Excitation Table:

Excitation Equation: 𝑄𝑡+1 ← 𝑆�� + 𝑄𝑡𝑆�� = ��(𝑆 + 𝑄𝑡𝑆) = ��(𝑆 + 𝑆)(𝑆 + 𝑄𝑡) = ��𝑆 + ��𝑄𝑡 (on the edge)

Note that when there are no rising edges, 𝑄𝑡+1 = 𝑄𝑡

clock

T Period Frequency = 1/T

Edge Detector

S'

R'

Q

Q

R

S

Eclock

or

SR Flip Flop

S Q

Q

clock

R

S Rclock Qt+1

0 0 Qt

0 1 0

1 0 1

1 1 0

Qt+1

Qt

1

0

0

Positiveedge-triggered

S Q

Q

clock

R

Negativeedge-triggered

S Q

Q

clock

R

Page 3: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

3 Instructor: Daniel Llamocca

D Flip Flop

Excitation Equation: 𝑄𝑡+1 ← 𝐷

T Flip Flop

Excitation Equation: 𝑄𝑡+1 ← 𝐷 = 𝑇𝑄𝑡

JK Flip Flop

Excitation Equation: 𝑄𝑡+1 ← 𝐽𝑄𝑡 + 𝐾𝑄𝑡

SYNCHRONOUS AND ASYNCHRONOUS INPUTS

Synchronous Inputs ▪ Typically, flip flops only change their outputs on the rising (or falling edge). Usually, a change on the inputs forces a change

on the outputs. These inputs are known as synchronous inputs, as the inputs' state is only checked on the rising (or falling) edges. Example: Input D of a D flip flop, Inputs J, K of a JK flip flop.

Asynchronous Inputs ▪ However, in many instances, it is useful to have inputs that force the outputs to a value

immediately, disregarding the rising (or falling edges). These inputs are known as asynchronous inputs. Common asynchronous inputs are 𝑝𝑟𝑛 and 𝑐𝑙𝑟𝑛 (they can be active-low or active high)

▪ The figure depicts a D Flip Flop with two asynchronous inputs: ✓ 𝑝𝑟𝑛: Preset (active low). When 𝑝𝑟𝑛 = 0 → 𝑄 = 1.

✓ 𝑐𝑙𝑟𝑛 (sometimes called 𝑟𝑒𝑠𝑒𝑡𝑛): Clear (active low). When 𝑐𝑙𝑟𝑛 = 0 → 𝑄 = 0.

✓ If 𝑝𝑟𝑛 and 𝑐𝑙𝑟𝑛 are both 0, usually 𝑐𝑙𝑟𝑛 is given priority.

▪ A Flip flop can have more than one asynchronous inputs, or none.

Tclock Qt+1

0 Qt

1 Qt

D Q

Qclock

T T Q

Qclock

J Kclock Qt+1

0 0 Qt

0 1 0

1 0 1

1 1 Qt

J Q

Q

clock

K

D Q

Qclock

K

J

Q

Q

D

E

D Q

Qclock

Edge Detector

clock

Dclock Qt+1

0 0

1 1

D Flip Flop

D Q

Qclock

prn

clrn

D

Page 4: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

4 Instructor: Daniel Llamocca

PRACTICE EXERCISES I

1. Complete the timing diagram of the circuit shown below: 2. Complete the VHDL description of the circuit shown below. Also, get the excitation equation for 𝑄.

library ieee;

use ieee.std_logic_1164.all;

entity circ is

port ( a, b, s, clk, clrn: in std_logic;

q: out std_logic);

end circ;

architecture a of circ is

begin

-- ???

end a;

𝑄𝑡+1 ←

3. Complete the VHDL description of the circuit whose excitation table is shown below. What is the excitation equation for 𝑄?

library ieee;

use ieee.std_logic_1164.all;

entity circ is

port ( A, B, C, clrn, clk: in std_logic;

q: out std_logic);

end circ;

architecture a of circ is

begin

-- ???

end a;

𝑄𝑡+1 ←

4. Complete the timing diagram of the circuit whose VHDL description is shown below. What is the excitation equation for 𝑄?

library ieee;

use ieee.std_logic_1164.all;

entity circ is

port ( clrn, x, clk: in std_logic;

q: out std_logic);

end circ;

architecture a of circ is

signal qt: std_logic;

begin

process (clrn, clk, x)

begin

if clrn = ‘0’ then

qt <= ‘0’;

elsif (clk’event and clk = ‘1’) then

if x = ‘1’ then qt <= not (qt); end if;

end if;

end process;

q <= qt

end a;

𝑄𝑡+1 ←

clk

x

clrn

Q

0

1b

s

clk

clrn

Q

a

D

𝑄

𝑄

A B Qt+1

0 0

0 1 C

1 0

1 1

1

Qt

Qt

clkclrn

1

1

1

1

X X 00 X

0

1D

E

Q

clk

D

clrn

E

Q

D

𝑄

𝑄

clk

clrn

Page 5: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

5 Instructor: Daniel Llamocca

5. Complete the timing diagram of the circuit shown below. If the frequency of the signal clock is 25 MHz, what is the frequency (in MHz) of the signal 𝑄?

6. Complete the timing diagram of the circuit shown below:

7. Complete the timing diagram of the circuit shown below. What is the excitation equation for 𝑄?

𝑄𝑡+1 ←

8. With a D flip flop and gates, sketch a circuit whose excitation equation is given by: 𝑄𝑡+1 ← 𝑎𝑏 + (𝑎𝑏)𝑄𝑡

9. Given the following excitation equation of a synchronous

circuit with rstn and clock, complete the timing diagram.

𝑄𝑡+1 ← 𝑥𝑦𝑄𝑡 + 𝑥𝑦 𝑄𝑡

10. Complete the timing diagram of the circuit shown below:

J

clk

clrn

K

x

Q

y

clk

x

clrn

y

Q

𝑄

𝑄

clock

clrn

Q

T

clock

clrn

'1'

𝑄

𝑄

D

resetn

QD Q

QLD Q

Q

Latch

E

clk

clk

resetn

D

Q

QL

clk

a

resetn

b

s

D

FA

xycin

s

cout

sa

b

clk

resetn

Full Adder

Q

Q

cout

cout

𝑄

𝑄

clk

x

rstn

y

Q

Page 6: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

6 Instructor: Daniel Llamocca

SYNCHRONOUS CIRCUITS: REGISTERS

n-BIT REGISTER: This is a collection of 'n' D-type flip flops, where each flip flop independently stores one bit. The flip flops are connected in parallel. They also share the same resetn and clock signals.

n-bit SHIFT REGISTER: This is a collection of 'n' D-type flip flops, connected serially. The flip flops share the same resetn

and clock signals. The serial input is called 'din', and the serial output is called 'dout'. The flip flop outputs (also called the

parallel output) are called 𝑄 = 𝑄𝑛−1𝑄𝑛−2⋯𝑄0. Depending on how we label the bits, we can have:

▪ Right shift register: The input bit moves from the MSB to the LSB, and ▪ Left shift register: The input bit moves from the LSB to the MSB.

Timing Diagram example:

D Q

clk

resetn

Dn-1

D Q

D Q

...

Dn-2

D0

...

Qn-1

Qn-2

Q0

...

D Q

resetn

D Q

clk

nn

D Q

resetn

din D Q D Q D Q

clk

...

Qn-1 Qn-2 Qn-3 Q0

D Q

resetn

D Q D Q D Q

clk

...

Q0 Q1 Q2 Qn-1

din

dout

dout

din dout

resetn

din dout

clk

Qn-1

Qn-2

Qn-3

Q0...

din dout

resetn

din dout

clk

Q0

Q1

Q2

Qn-1

...

RIGHT SHIFT REGISTER:

LEFT SHIFT REGISTER:

D Q

resetn

D Q D Q D Q

clk

Q3

clk

resetn

Q 0000

x

x

Q2 Q1 Q0

0000 0000 1000 0100 0010 1001 0100 1010 1101 1110 0111 0011 0001

Q3

Q2

Q1

Q0

Page 7: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

7 Instructor: Daniel Llamocca

PARALLEL ACCESS SHIFT REGISTER: ▪ This is a shift register in which we can write data on the flip flops in parallel. 𝑠_𝑙 = 0 → shifting operation, 𝑠_𝑙 = 1 → parallel

load. The figure below shows a 4-bit parallel access right shift register.

ADDING AN ENABLE INPUT TO FLIP FLOPS: ▪ In many instances, it is very useful to have a signal that controls whether the value of the flip flop is kept. The following

circuit represent a flip flop with synchronous enable.

✓ E = ‘0’: the flip flop keeps its value.

✓ E = ‘1’: the flip flop captures the value of the input D.

▪ We can thus create n-bit registers and 𝑛-bit shift registers with enable. Here, all the flip flops share the same enable input. ▪ Excitation equation: 𝑄𝑡+1 ← ��𝑄𝑡 + 𝐸𝐷

D Q

clk

resetn

0 1

din D3

D Q

0 1

D2

D Q

0 1

D1

D Q

0 1

D0s_l

Q3 Q2 Q1 Q0

clk

din

resetn

Q

D

0000

0000

s_l

1101 1001 1100

0000 1000 1100 0110 0011 1001 1101 1110 0111 1011 1100 0110 0011 1100 1110 0111 0011

0

1D

E

Q

clk

D

resetn

E

Q

D Q

clk

resetn

din

Edout

resetn

din

Edout

clk

Qn-1

Qn-2

Qn-3

Q0...

resetn

din

E

clk

Q0

Q1

Q2

Qn-1

...

RIGHT SHIFT REGISTER: LEFT SHIFT REGISTER:

din

E din

E

s_l

dout

resetn

din

E

s_l

dout

clk

PARALLEL ACCESS

SHIFT REGISTER:

𝑛

𝑛

Q

D

doutdoutD

E

Q

resetn

D

E

Q

clk

REGISTER:

𝑛 𝑛

Page 8: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

8 Instructor: Daniel Llamocca

Parallel access shift register with enable ▪ All the flip flops share the same enable input.

ADDING A SYNCHRONOUS CLEAR INPUT TO FLIP FLOPS ▪ In many instances, it is very useful to have a signal that can clear the value of the flip flop but only on the rising (or falling

edges): synchronous clear (𝑠𝑐𝑙𝑟). Typically, all synchronous signals are validated by enable. For example, for a D flip flop, the table show how the output state 𝑄 changes (on the rising edge):

𝐸 𝑠𝑐𝑙𝑟 𝑄 (output state)

0 X 𝑄 ← 𝑄

1 0 𝑄 ← 𝐷

1 1 𝑄 ← 0

▪ We can thus create 𝑛-bit registers and 𝑛-bit shift registers with enable and 𝑠𝑐𝑙𝑟. Here, all the flip flops share the same enable

and 𝑠𝑐𝑙𝑟 inputs.

D Q

E

clk

resetn

0 1

din D3

D Q

E

0 1

D2

D Q

E

0 1

D1

D Q

E

0 1

D0s_l

Q3 Q2 Q1 Q0

clk

din

resetn

Q

D

E

0000

E

0000

s_l

1101 1001 1100

0000 1000 1100 0110 1011 1101 1101 0110 1101 0110 1100 0110 0011 1001 1100 0110 0011

E

QD Q

clk

resetn

0

10

sclr

D0

1

D Q

resetn

D

E

sclr

Q

clk

din

E

sclr

dout

resetn

din

E

sclr

dout

clk

Qn-1

Qn-2

Qn-3

Q0...

RIGHT SHIFT REGISTER:REGISTER:

𝑛 𝑛 din

E

sclr

dout

resetn

din

E

sclr

dout

clk

LEFT SHIFT REGISTER:

Q0

Q1

Q2

Qn-1

...

din

E

sclr

s_l

dout

resetn

din

E

sclr

s_l

dout

clk

PARALLEL ACCESS

SHIFT REGISTER:

𝑛

𝑛

Q

D

Page 9: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

9 Instructor: Daniel Llamocca

SYNCHRONOUS COUNTERS ▪ Counters are useful for: counting the number of occurrences of a certain event, generate time intervals for task control,

track elapsed time between two events, etc. Counters are made of flip flops and combinatorial logic. Common design techniques include using the Finite State Machine (FSM) method of a synchronous accumulator.

▪ Synchronous counters change their output on the clock edge (rising or falling). Each flip flop shares the same clock input signal. If the initial count is zero, each flip flop shares the resetn input signal.

COUNTER CLASSIFICATION:

a) Binary counter: An 𝑛 − 𝑏𝑖𝑡 counter counts from 0 to 2𝑛 − 1. The figure depicts a 2-bit counter.

b) Modulus counter: A counter 𝑚𝑜𝑑𝑢𝑙𝑜 − 𝑁 counts from 0 to N-1. Special case: BCD (or decade) counter: Counts from 0

to 9.

c) Up/down counter: Counts both up and down, under command of a control input. d) Parallel load counter: The count can be given an arbitrary value. e) Counter with enable: If enable = 0, the count stops. If enable = 1, the counter counts. This is usually done by

connecting the enable inputs of the flip flops to a single enable. f) Ring counter: Also called one-hot counter (only one bit is 1 at a time). It can be constructed using a shift register. The

output of the last stage is fed back to the input to the first stage, which creates a ring-like structure. The asynchronous signal startn sets the initial count to 100…000 (first bit set to 1). Example (4-bits): 1000, 0100, 0010, 0001, 1000, …

The figure below depicts an 𝑛 − 𝑏𝑖𝑡 ring counter.

g) Johnson counter: Also called twisted ring counter. It can be constructed using a shift register, where the �� output of

the last flip flop is fed back to the first stage. The result is a counter where only a single bit has a different value for two consecutive counts. All the flip flops share the asynchronous signal ‘resetn’, which sets the initial count to 000…000. Example (4 bits): 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000, … The figure below depicts

an 𝑛 − 𝑏𝑖𝑡 Johnson counter.

clk

resetn

Q 0000 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 0001

Q 4

BCD counter

resetn

clk

D Q

resetn

D Q

Q0

Q1

clk

clk

resetn

Q 0000 01 10 11 00 01 10 11

D Q

startn

D Q D Q D Q

clk

...

Qn-1 Qn-2 Qn-3 Q0

prn

D Q

resetn

D Q D Q D Q

clk

...

Qn-1 Qn-2 Qn-3 Q0

Q

Page 10: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

10 Instructor: Daniel Llamocca

COUNTER DESIGN USING AN ACCUMULATOR:

▪ A generic modulo-N counter is shown on the right (𝑛 = ⌈log2𝑁⌉). An example is shown

below of a counter modulo-200 (it uses a register, an adder, a comparator, and an OR gate). 𝑄: count. 𝑧: output signal asserted only when the maximum count (199) is reached.

RANDOM ACCESS MEMORY EMULATOR ▪ The following sequential circuit represents a memory with 8 addresses, where each address holds a 4-bit data. The memory

positions are implemented by 4-bit registers. The reset and clock signals are shared by all the registers. Data is written or read onto/from one of the registers (selected by the signal 𝑎𝑑𝑑𝑟𝑒𝑠𝑠).

▪ Writing onto memory (𝑤𝑟_𝑟𝑑 = 1): The 4-bit input data (D_in) is written into one of the 8 registers. The address signal

selects which register is to be written. Here, the 7-segment display must show 0. For example: if address = “101”, then D_in is written into register 5.

▪ Reading from memory (𝑤𝑟_𝑟𝑑 = 0): The MUX output appears on the 7-segment display (hexadecimal value). The

address signal selects the register from which data is read. For example: If address = “010”, then data in register 2 must appear on the 7-segment display. If data in register 2 is ‘1010’, then the symbol ‘A’ appears on the 7-segment display.

Decoderaddress

wr_rd

Din4

E

D

E

D

E

D

E

D

E

D

E

D

E

D

E

D

Q

Q

Q

Q

Q

Q

Q

Q

4Decoder:HEX to 7 segments

7

MUX

3

E

wr_rd

E

clock

resetn

0

1

2

3

4

5

6

7

4

4

3

+

00000001

E

sclr

8

8

resetn

E

sclr

Qsclr: synchronous clearIf E=sclr=1, then Q = 0

8 8

clock

A=B

= 199?

a7

b7

a6

b6

a5

b5

a4

b4

A

11000111

8B

A=B

z

a3

b3

a2

b2

a1

b1

a0

b0

𝑛 = log2 200 =

E

sclr

Q

resetn

E

sclr

Q

clock

𝑛

zz

N

Page 11: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

11 Instructor: Daniel Llamocca

SUMMARY OF COMMON COMPONENTS AVAILABLE IN PARAMETERIZED VHDL CODE: ▪ The following components are popular in the design of digital logic circuits and their generic VHDL code is available:

✓ D-type flip flop with enable: dffe ✓ D-type flip flop with enable and synchronous clear: dffes

✓ n-bit register with enable and synchronous clear: my_rege

Parameter (VHDL code): n (number of bits)

✓ Counter modulo-N with enable and synchronous clear: my_genpulse_sclr

Parameter (VHDL code): N (sometimes COUNT is used)

This circuit counts from 0 to N-1 (this is the maximum count).

The number of bits of the output Q is given by 𝑛 = ⌈log2𝑁⌉

z: output of a comparator between Q and N-1. z = ‘1’ when Q = N-1, else z = ‘0’.

Depending on the application, some inputs/outputs might not be used:

The output Q might not be used. Only z suffices.

The output z might not be used. The count Q suffices.

The input sclr might not be used. In this case, you need to tie it to ‘0’ so it doesn’t

affect the counter behavior.

The enable input (E) might not be used. In this case, you need to tie it to ‘1’, so the counter works.

✓ n-bit parallel access (right/left) register with enable and synchronous clear: my_pashiftreg_sclr

Parameters (VHDL code):

n (number of bits)

DIR (direction): “LEFT”, “RIGHT”

din: serial input.

dout: serial output (also called shiftout):

dout = Q0 if DIR = “RIGHT”

dout = QN-1 if DIR= “LEFT”

Depending on the application, some inputs/outputs might not be used:

The output Q might not used. Only dout suffices.

The output dout might not be used. The output Q suffices.

The input sclr might not be used. In this case, you need to tie it to ‘0’ so it doesn’t affect the counter behavior.

The enable input (E) might not be used. In this case, you need to tie it to ‘1’, so the counter works.

s_l: It controls whether we shift in din (s_l= 0) or load (s_l=1) n-bit D. If you tie this input to a fixed value, you get:

If you tie s_l to ‘1’, then the circuit becomes just an n-bit register.

If you tie s_l to ‘0’, then the circuit is just a left/right shift register.

▪ Generic components: Summary of the behavior on the clock tick:

n-bit register:

If E=0, the output is kept

Counter modulo-N:

If E=0, the count stays.

n-bit Parallel access left/right shift register:

If E=0, the output is kept if E = 1 then

if sclr = 1 then

Q 0

else

Q D

end if;

end if;

if E = 1 then

if sclr = 1 then

Q 0

elseif Q = N-1 then

Q 0

else

Q Q+1

end if;

end if;

* z = 1 if Q = N-1

if E = 1 then

if sclr = 1 then

Q 0

elseif s_l = 1 then

Q D

else

Q shift in ‘din’

(to the left or right) end if;

end if;

E

sclr

Q

resetn

E

sclr

Q

clockzz

N

D Q

resetn

D

E

sclr

Q

clk

n

din

E

sclr

s_l

dout

resetn

din

E

sclr

s_l

dout

clk

Q

Dn DIR

D Q

resetn

D

E

sclr

Q

clk

D Q

resetn

D

E

Q

clk

Page 12: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

12 Instructor: Daniel Llamocca

FINITE STATE MACHINES: ▪ Sequential circuits are also called Finite State Machines (FSMs), because the functional behavior of these circuits can be

represented using a finite number of states (flip flop outputs). ▪ Suppose you want to design a circuit that counts from 0 to 3 and issues a one-cycle pulse when the maximum count is

reached. We can implement this circuit with a counter with some gates. What if we want a two-cycle pulse? We can, with painstaking effort, implement this circuit with a counter, flip flops, and logic gates. The Finite State Machine method offers a systematic way of implementing this circuit.

FSM MODEL

▪ The figure below represents the Finite State Machine model. Any digital circuit that performs some sequential control can be represented by this model.

▪ Classification: Moore machine: Outputs depend solely on the current state of the flip flops. Mealy machine: Outputs depend on the current state of the flip flops as well as on the input to the circuit.

Important: Since the inputs can change at any time, the outputs are not restricted to only change on the clock edges. ▪ The signal 𝑟𝑒𝑠𝑒𝑡𝑛 sets the flip flops to an initial state.

▪ A sequential circuit with certain behavior and/or specification can be formally designed using the Finite State Machine

method: drawing a State Diagram and coming up the Excitation Table. ▪ Designing sequential circuits using Finite State Machines is a powerful method in Digital Logic Design. Example: 2-bit counter with enable and 𝑧 output: 00, 01, 10, 11, 00, … The output 𝑧 is 1 when the present count is ‘11’.

▪ First step: Draw the State Diagram and State Table. If we were to implement the state machine in VHDL, this is the only step we need.

▪ Second step: State Assignment. We assign unique flip flop states to our state labels (S1, S2, S3, S4). This assignment is

arbitrary (e.g.: S1: Q=10, S2: Q=11, S3: Q=00, S4: Q=01). However, we can simplify our procedure if we assign each state so that they follow the desired count:

✓ S1: Q = 00 ✓ S2: Q = 01 ✓ S3: Q = 10 ✓ S4: Q = 11

This way, the output C1C0 (the count) matches the states encoded in binary (i.e., FSM flip flops outputs): C1 = Q1, C0 = Q0.

Combinational Circuit

Flip

Flops

Combinational Circuit

Inputs Q(states)

clock

resetn

Only for Mealy Machine

Outputsn

S1 S2

S4 S3

1/0

0/0

resetn = 0E/z

0/0

1/0

1/0

1/1

0/1

0/00 S1

0 S2

0 S3

0 S4

1 S1

1 S2

1 S3

1 S4

S1 0 0 0

S2 0 1 0

S3 1 0 0

S4 1 1 1

S2 0 1 0

S3 1 0 0

S4 1 1 0

S1 0 0 1

PresentStateE z

NextState

Input OutputsC1 C0

Page 13: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

13 Instructor: Daniel Llamocca

▪ Third step: Excitation table. Here, we replace the state labels by the flip flop states:

Note that C1C0 = Q1Q0. This is very

common when designing counters using this method.

As a result, it is customary to omit the

output signals C1 and C0 in the State

Diagram and Table, since Q1Q0 (the

binary-encoded states) already represent the counter output.

▪ Fourth step: Excitation equations and minimization. 𝑄1(𝑡 + 1) and 𝑄0(𝑡 + 1) are the next state of the flip flops, i.e. these

signals are to be connected to the inputs of the flip flops.

𝑄1(𝑡 + 1) ← 𝑄1𝑄0 + ��𝑄1 + 𝐸𝑄1 𝑄0

𝑄0(𝑡 + 1) ← 𝐸𝑄0 + ��𝑄0

𝑧 = 𝑄1𝑄0 → This is called Boolean output equation; it is always valid (not just on the clock edge) Output 𝑧 only depends on the present state. Outputs 𝑄1, 𝑄0 are the states and they only depend

(in terms of the combinational output circuit) on the present state. Thus, this is a Moore FSM. ▪ Fifth step: Circuit implementation.

Example: 2-bit gray-code counter with enable and 𝑧 output: 00, 01, 11, 10, 00, … The output 𝑧 is 1 if the present count is ‘10’.

▪ First step: Draw the State Diagram and State Table. If we were to implement the state machine in VHDL, this is the only step we need.

0 1

0 1

Q0

EQ1

0

1

00 01

1 0

0 1

11 10

Q1(t+1)

0 0

1 1

Q0

EQ1

0

1

00 01

1 1

0 0

11 10

Q0(t+1)

0 0

0 1

Q0

EQ1

0

1

00 01

0 0

1 0

11 10

z

resetn

clk

z

D Q Q1

D Q Q0

E

clock

E

resetn

Q

z

00

state S1 S1 S2 S3 S3 S4 S4 S1 S2 S2

00 01 10 10 11 11 00 01 01

0 S1

0 S2

0 S3

0 S4

1 S1

1 S2

1 S3

1 S4

S1 S2

S4 S3

1/0

0/0

resetn = 0

E/z

0/0

1/0

1/0

1/1

0/1

0/0S1 0 0 0

S2 0 1 0

S3 1 1 0

S4 1 0 1

S2 0 1 0

S3 1 1 0

S4 1 0 0

S1 0 0 1

PresentStateE z

NextState

Input OutputsC1 C0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0

0 1

1 0

1 1

0 1

1 0

1 1

0 0

C1 C0 zQ0(t+1)Q1(t+1)Q0(t)Q1(t)E

0 0

0 1

1 0

1 1

0 1

1 0

1 1

0 0

0

0

0

1

0

0

0

1

Present State Next StateInput Outputs

Page 14: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

14 Instructor: Daniel Llamocca

▪ Second step: State Assignment. We assign unique flip flop states to our state labels (S1, S2, S3, S4). This assignment is arbitrary. However, we can simplify our procedure if we assign each state so that they follow the desired count:

✓ S1: Q = 00 ✓ S2: Q = 01 ✓ S3: Q = 11 ✓ S4: Q = 10

This way, the output C1C0 (the count) matches the states encoded in binary (i.e., FSM flip flops outputs): C1 = Q1, C0 = Q0.

Alternatively, we could make S1: Q=00, S2: Q=01, S3: Q=10, S4: Q=11. Here the output C1C0 will not match Q1Q0 (the

binary-encoded states), though it makes the encoding of the states more consistent.

▪ Third step: Excitation table. Here, we replace the state labels by the flip flop states (we use the simpler state assignment): ▪ Fourth step: Excitation equations and minimization. 𝑄1(𝑡 + 1) and 𝑄0(𝑡 + 1) are the next state of the flip flops, i.e. these

signals are to be connected to the inputs of the flip flops.

𝑄1(𝑡 + 1) ← ��𝑄1 + 𝐸𝑄0 𝑄0(𝑡 + 1) ← 𝐸𝑄1 + ��𝑄0 𝑧 = 𝑄1𝑄0

Output 𝑧 only depends on the present state. Outputs 𝑄1, 𝑄0 are the states and they only depend

(in terms of the combinational output circuit) on the present state. Thus, this is a Moore FSM.

▪ Fifth step: Circuit implementation.

Note: In these 2-bit counters, the states are represented by the outputs of the flip flops: 𝑄1, 𝑄0. They also happen to be

the outputs of the FSM. This is common in counters, as the count is usually the same as the flip flop outputs.

0 1

0 1

Q0

EQ1

0

1

00 01

0 0

1 1

11 10

Q1(t+1)

0 0

1 1

Q0

EQ1

0

1

00 01

0 1

0 1

11 10

Q0(t+1)

0 1

0 0

Q0

EQ1

0

1

00 01

1 0

0 0

11 10

z

D Q

resetn

D Q

Q0

Q1

clk

E

z

clock

E

resetn

Q

z

00

state S1 S1 S2 S3 S3 S4 S4 S1 S2 S2

00 01 11 11 10 10 00 01 01

0 0 0

0 0 1

0 1 1

0 1 0

1 0 0

1 0 1

1 1 1

1 1 0

0 0

0 1

1 1

1 0

0 1

1 1

1 0

0 0

C1 C0 zQ0(t+1)Q1(t+1)Q0(t)Q1(t)E

0 0

0 1

1 1

1 0

0 1

1 1

1 0

0 0

0

0

0

1

0

0

0

1

Present State Next StateInput Outputs

Page 15: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

15 Instructor: Daniel Llamocca

Example: BCD counter implemented as FSM. Outputs: 𝑄(3. .0), 𝑧. When the count reaches 1001, 𝑧 becomes 1. Moore FSM

Example: FSM. Input: 𝑤. Output: 𝑧. This is a Moore FSM as 𝑧 only depends on the present state.

Example: FSM. Input: 𝑥. Output: 𝑧. This is a Mealy FSM as 𝑧 depends on the present state and the input. This implies that 𝑧 can change during a clock cycle, as in the timing diagram:

We can get the excitation table and excitation equations from the FSM diagram:

S1: Q = 00 S2: Q = 01 S3: Q = 10 S4: Q = 11

𝑄1(𝑡 + 1) ← 𝑥𝑄1 + (𝑄1𝑄0) 𝑄0(𝑡 + 1) ← 𝑥𝑄1 + 𝑥𝑄0 + ��𝑄1𝑄0

𝑧 = 𝑄1 𝑄0 + 𝑥(𝑄1𝑄0 )

0/1

clock

x

resetn

state

z

S1

S1 S2

S4 S3

0/1

1/0

0/0

1/10/1

resetn = 0x/z

1/0

1/1

S1 S2 S4 S1 S2 S3 S4 S4 S4

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0

1 0

1 1

0 0

0 1

1 1

1 0

1 1

zQ0(t+1)Q1(t+1)Q0(t)Q1(t)x

1

1

0

1

0

1

1

0

Present State Next StateInput Outputs

S1

Q=0,z=0

S2

Q=1,z=0

S3

Q=2,z=0

S4

Q=3,z=0

S5

Q=4,z=0

S10

Q=9,z=1

S9

Q=8,z=0

S8

Q=7,z=0

S7

Q=6,z=0

S6

Q=5,z=0

resetn = '0'

S1

z=0

S2

z=0

S9

z=1

w=0

w=1

w=1

resetn = 0 w=1

clk

w

resetn

z

state S1

S3

z=0

S4

z=1

S5

z=0

S6

z=0

S7

z=0

S8

z=0

w=0 w=0 w=0

w=1

w=0w=0

w=0

w=1

w=0

w=1 w=1 w=0

w=1w=1

S1 S2 S9 S8 S9 S1 S2 S3 S2 S3 S4 S5 S4 S3 S4

Page 16: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

16 Instructor: Daniel Llamocca

EXAMPLE: Pulse Detector ▪ Circuit with an input 𝑥 and output 𝑧. The machine generates 𝑧 = 1 when it detects a pulse. Note how in this design, the

output 𝑧 is 1 as soon as the 1 → 0 transition is detected.

Assumption: For the circuit to detect a ‘1’ or a ‘0’ on 𝑥, the value needs to happen when a rising edge occurs.

▪ In order to have a clean output pulse, a common technique is to include a flip flop whose input is 𝑧 ▪ The first state (S1) is to make sure that the pulse started at ‘0’. This is a Mealy FSM. EXAMPLE: Sequence Detector ▪ Circuit with an input 𝑥 and output 𝑧. The machine generates 𝑧 = 1 when it detects the sequence 1011011. The value of a

bit is detected on the clock edge. Right after the sequence is detected, the circuit looks for a new sequence. Assumption: For the circuit to detect a ‘1’ or a ‘0’ on 𝑥, the value needs to happen when a rising edge occurs.

Signal 𝐸 is an input enable: It validates the input 𝑥, i.e., if 𝐸 = 1, 𝑥 is valid, otherwise 𝑥 is not valid. The figure below

illustrates the behavior for a certain input stream. This is a Mealy FSM.

FINITE STATE MACHINE

resetn

clock

x zx

E

z

E

0 1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1

S1 S2

S7

11/0

resetn=0

Ex/z

S3

S6

10/0

11/0

11/0

10/0

10,0X/0 11/1

S4

S5

11/0

110/0

10/0

10 101

101110110101101

0X/0

11,0X/00X/0

0X/0

11/0

10/00X/00X/0

10/0

S2

clock

E

resetn

z

state S1

x

S1 S2 S3 S4 S5 S5 S6 S7 S1 S2 S3 S4 S3 S4 S5

FSM

resetn

clock

xz

clock

resetn

x

z

pulse

S1 S2

S3

0/0

resetn=0

x/z

1/0

0/1

0

01

0/0

1/0

1/0

clock tick

Page 17: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

17 Instructor: Daniel Llamocca

EXAMPLE: Sequence Detector (2 versions) ▪ Circuit with an input 𝑥 and output 𝑧. The machine generates 𝑧 = 1 when it detects the sequence 01101. The value of a bit

is detected on the clock edge. Right after the sequence is detected, the circuit looks for a new sequence. ▪ Here, two FSM versions are presented:

✓ (left): When the last bit (‘1’) is detected (i.e., 𝑥 = 1 on the clock edge), the output 𝑧 will be 0 right after the clock edge.

Note that the output 𝑧 will become 1 as soon as 𝑥 is 1 in S5. This is a Mealy FSM.

* In order to have a clean output pulse, a common technique is to include a flip flop whose input is 𝑧.

✓ (right): The output 𝑧 will be 1 for one clock cycle right after the last bit (‘1’) is detected on the clock edge. This requires

6 states. This is a Moore FSM.

S1

clock

resetn

z

state S1

x

S1 S1 S2 S3 S4 S5 S1 S2 S3 S4 S5 S1 S2 S3 S4

S1 S20/0

resetn=0

x/z

S31/0

1/0

S4S5

0

1/0

0/0

01

0110110 0/01/1

S1

z

state S1 S1 S1 S2 S3 S4 S5 S6 S2 S3 S4 S5 S6 S2 S3 S4

0/0

1/0

S1 S20/0

resetn=0

x/z

S31/0

1/0

S4S5

0

1/0

0/0

01

0110110 0/01/0

0/0

1/0

S601101

1/1

0/1

0/0 0/0

Page 18: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

18 Instructor: Daniel Llamocca

ALGORITHMIC STATE MACHINE (ASM) CHARTS:

0 0 1 0 0 1 1 0 1 0 1 0 1 0 0 1 1 0

S1 S2

S4 S3

1/0

0/0

resetn = 0E/z

0/0

1/0

1/0

1/1

0/1

0/0

S1

S2

resetn=0

1

E0

S4

z 1

E1 0

1

E0

S3

1

E0

S1 S2

S6 S5

0/0

1/0

resetn = 0x/z

S3

S4

1/0

0/0

0/01/0

1/1

0/0 1/0

0/0

0/0

S1

S2

resetn=0

0

x1

S4

x

z 1

0

1

1

x0

S3

0

x1

Gray counter, z=1 when Q=10 Sequence Detector: 010011

S5

x

1

0

S6

x10

x

z

Page 19: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

19 Instructor: Daniel Llamocca

EXAMPLE: ARBITER CIRCUIT ▪ Three devices can request access to a certain resource at any time (example: access to a bus made of tri-state buffers, only

one tri-state buffer can be enabled at a time). The FSM can only grant access to one device at a time.There should be a priority level among devices.

▪ If the FSM grants access to one device, one must wait until the request signal to that device is deasserted (i.e. set to zero) before granting access to a different device.

▪ Algorithmic State Machine (ASM) chart:

grant1

DEVICE 1req1

grant2

DEVICE 2req2

grant3

DEVICE 3req3

FINITE STATE MACHINE

resetn

clock

r1

r2

r3

CONTROL CIRCUIT

g1

g2

g3

priority

resetn=0

g1,g2,g3 0

r1

g1 1

r1

S1

r2

g2 1

r2

r3

g3 1

r3

1 1 1

0 0 0

0 1

0

1 1

0

S2 S3 S4

Page 20: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

20 Instructor: Daniel Llamocca

Modifying the rate of change of a Finite State Machine: ▪ We usually would like to reduce the rate at which FSM transitions occur. A straightforward option is to reduce the frequency

of the input clock. But this is a very complicated problem when a high precision clock is required. ▪ Alternatively, we can reduce the rate at which FSM transitions occur by including an enable signal in our FSM: this means

including an enable to every flip flop in the FSM. For any FSM transition to occur, the enable signal has to be ‘1’. Then we assert the enable signal only when we need it. The effect is the same as reducing the frequency of the input clock.

✓ The figure below depicts a counter modulo-N (from 0 to N-1) connected to a comparator that generates a pulse (output

signal ‘z’) of one clock period every time we hit the count ‘N-1’. The number of bits the counter is given by 𝑛 = ⌈log2𝑁⌉. The effect is the same as reducing the frequency of the FSM to 𝑓 𝑁⁄ , where 𝑓 is the frequency of the clock.

✓ A modulo-N counter is better designed using VHDL behavioral description, where the count is increased by 1 every clock

cycle and ‘z’ is generated by comparing the count to ‘N-1’. A modulo-N counter could be designed by the State Machine method, but this can be very cumbersome if N is a large number. For example, if N = 1000, we need 1000 states.

✓ As an example, we provide the timing diagram of the counter from 0 to N-1, when N=10. Notice that ‘z’ is only activated

when the count reaches “1001”. This ‘z’ signal controls the enable of a state machine, so that the FSM transitions only occur every 10 clock cycles, thereby having the same effect as reducing the frequency by 10.

▪ We can apply the same technique not only to FSMs, but also to any sequential circuit. This way, we can reduce the rate of

any sequential circuit (e.g. another counter) by including an enable signal of every flip flop in the circuit.

clk

resetn

Q 0000

z

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 0001

E

resetn

Q

clock

n

counter0 to N-1

z

FSMOutputs

Inputs

Q=N-1?

comparator

EE

Page 21: ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, …llamocca/Courses/ECE2700/Notes - Unit 6.pdfIn many instances, it is very useful to have a signal that controls whether the value

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter 2021

21 Instructor: Daniel Llamocca

PRACTICE EXERCISES II 1. Two-pulse Detector: Draw the State Diagram (in ASM form) for a circuit that asserts a signal 𝑧 when two pulses are detected

on its input port 𝑥. Once the two pulses are detected, the FSM looks for a new pair of pulses.

Assumption: For the circuit to detect a ‘1’ or a ‘0’ on 𝑥, the value needs to occur when a rising edge happens.

2. Sequence Detector: The circuit has to generate 𝑧 = 1 when it detects the sequence 01011 or 11100. Once a sequence is

detected, the circuit looks for a new sequence. Note that once the sequence starts being detected, we prioritize that sequence over the other (example: last sequence inside a dotted red rectangle is not considered). ✓ Draw the State Diagram. Also, provide the State Table and Excitation Table of this circuit.

3. Given the following state diagram (in ASM form): ✓ Is this a Mealy or a Moore Machine? Why? ✓ Get the excitation equations and the Boolean equations for 𝑥, 𝑧, and 𝑤.

✓ Sketch the circuit for this Finite State Machine. Identify the parts of your circuit that correspond to the FSM model components.

4. The following VHDL code describes an FSM. Get the excitation equations and Boolean equations for the output signals.

library ieee;

use ieee.std_logic_1164.all;

entity circ is

port ( clk, rstn: in std_logic;

a, b: in std_logic;

x,w,z: out std_logic);

end circ;

architecture behavioral of circ is

type state is (S1, S2, S3);

signal y: state;

begin

Transitions: process (rstn, clk, a, b)

begin

if rstn = '0' then y <= S1;

elsif (clk'event and clk = '1') then

case y is

when S1 =>

if a = '1' then y <= S2; else y <= S3; end if;

when S2 =>

if b = '1' then y <= S3; else y <= S1; end if;

when S3 =>

if a = '1' then y <= S3; else y <= S1; end if;

end case;

end if;

end process;

Outputs: process (y,a,b)

begin

x <= ‘0’; w <= ‘0’; z <= ‘0’;

case y is

when S1 => if a = ‘1’ then z <= ‘1’; end if;

when S2 => x <= ‘1’;

when S3 => w <= '1';

end case;

end process;

end behavioral;

0 0 1 0 1 1 1 1 1 0 0 1 0 1 1 1 0 0 1 0 1 1 0 1 0 1 1 1 0 0

FINITE STATE MACHINE

resetn

clock

x z x

z

rstn=0

a

x 1

b

S1

b

b

1 1

0 0

0 1

0 1

S2 S3

z 1

a

1

0w 1

CombinationalCircuit

Flip FlopsCombinational

CircuitInputs

Q

clock

resetn

Only for Mealy MachineO

utp

uts𝑛

FSM

resetn

clock

xz pulse pulse

clock tick clock tickclock tick