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ELEC 326: Digital Logic Design

Kartik MohanramDept. of Electrical and Computer Engineering

Rice University

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ELEC 220 background (lectures 1-7)

Bits, data types, arithmetic, etc.Transistors, MOSFETs, logic gatesTransistor-level diagrams and circuit schematicsLogic design with gates, Boolean equivalenceAddersMemory typesCombinational vs. sequential, latches, flip-flopsFinite state machinesLogic simplification, Karnaugh maps

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Design metrics

How to evaluate performance of a digital circuit (gate, block, …)?

ScalabilityCostSpeed (delay, operating frequency) Power dissipationEnergy to perform a functionReliability

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Understanding technology scaling

Moore’s lawIf transistor count is an acceptable metric of processing powerNumber of transistors that can be crammed into the same real estate will double every 24 months

More an industry driverSemiconductor technology will double its effectiveness every 18 monthsThe key (in some sense) to this is technology scaling

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A rough timeline – what’s missing?

© Intel Corp.

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© Intel Corp.

Pictorially

http://www.intel.com/technology/mooreslaw/index.htm

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Processor frequency

P6Pentium ® proc

48638628680868085

8080800840040.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Freq

uenc

y (M

hz)

Doubled every2 years

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Processor power

5KW 18KW

1.5KW 500W

400480088080

80858086

286386

486

Pentium® proc

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Pow

er (W

atts

)

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What’s missing

We know now that the trend did top-out?Why?

To understand this, we need to look atDie size andProcess technology used for fabricationWhy is this information important?Broader questionHow does one evaluate technology alternatives?

First-order circuit analysis when we get to transistors

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Technology scaling

What do the words 0.5 micron, 0.35 micron, 0.25 micron, 0.18 micron, … mean to you

Do you see a rough trend in this series?This sqrt(2) shrinking in successive generations is termed technology scalingUsually attributed to the minimum feature size used for fabricationWhere are we now?

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Why scaling?

Technology shrinks by 0.7/generationWith every generation can integrate 2X more functions per chip; chip cost does not increase significantlyCost of a function decreases by 2XBut …

How to design chips with more and more functions?Design engineering population does not double every two years…

Hence, a need for more efficient design methodsExploit different levels of abstraction

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Processor power density

400480088080

8085

8086

286 386486

Pentium® procP6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Pow

er D

ensi

ty (W

/cm

2 )

Hot Plate

NuclearReactor

RocketNozzle

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The Pentium M: A case study

First generation Pentium MCodename Banias0.13 micron technology1.3 to 1.7 GHzL2 cache 1 MBPower 24 WattsTransistor count 77 millionDie size 82 mm2

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Banias die photograph

© Intel Corp.

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Second generation Pentium M

Codename Dothan0.09 micron technology1.7 to 2.0 GHzL2 cache 2 MBPower 21 WattsTransistor count 140 millionDie size 87 mm2

Let’s analyze these numbers and see if they conform to technology scaling

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Types of memory

RAM – Random access memorySRAM – Static RAM

Microprocessor cachesFast, burns more powerStandard design used 6 transistors per cellSo, 1 MB of on-chip cache requires ? TransistorsWhat about with ECC (Error Correcting Codes)

SDRAM – Synchronous dynamic RAMOff-chip memoryUsually used in DIMMs (dual inline memory module)RDRAM, DDR SDRAM, etc. are all flavors of DRAMs

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Side-by-side comparison

Dothan dieNot to scale, but let’s eyeball it anyway

© Intel Corp.

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Multi-core dies

AMD’s Opteron-based onesIntel’s Montecito

Next generation dual-core chip in the Itanium familyMcKinley -> Madison -> MontecitoMadison – single-core Itanium

0.13 micron technology9 MB cache memory432 mm2, approx 592 million transistors

Assignment: Estimate ball-park transistor count for the Montecito die on next slide

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Montecito die photograph

© Intel Corp.

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“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Variability• Reliability, Manufacturability• Power Dissipation• Clock distribution

Everything Looks a Little Different

“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.

…and There’s a Lot of Them!

∝ DSM ∝ 1/DSM

Challenges

Deep sub-micron (DSM) or sub-100nm technologies