Elastic Circuits blending synchronous and asynchronous technologies

Elastic Circuitsblending synchronous and asynchronous technologies

Jordi CortadellaUniversitat Politècnica de Catalunya, Barcelona

(joint work with M. Kishinevsky and M. Galceran-Oms)

Collège de FranceMay 21st, 2013

Elastic circuitsCollège de France 2013 2

Synchronous circuit

Elastic circuits

CombinationalLogic

Flip

Flo

ps

Flip

Flo

ps

PLL

Collège de France 2013 3

Asynchronous circuit

Elastic circuits

CombinationalLogic LL

delay

CC 4-phase


Asynchronous circuit

C

ReqIn ReqOut

AckIn AckOut

C C C

• David Muller’s pipeline (late 50’s)• Sutherland’s Micropipelines (Turing award, 1989)


Globally-asynchronousLocally-synchronous

GALS

SoC design with GALS• Most IPs are synchronous

• Different components may have different operating frequencies

• Some components have variable latencies (e.g., cache hit/miss latency)

• Multiple clock domains are essential

Elastic circuits

Bridge

CDC

DSP

P

Fast Bus

Slow Bus

Bridge

CDC

Mem

CLK2

CLK1

CLK3


Multiple clock domains

Elastic circuits

CLK

Single clock(mesochronous)

f1/f0

f2/f0

f3/f0

CLK(f0)

Rational clockfrequencies

CLK

1C

LK2

CLK

3

CLK

0

Independent clocks

(controllable skew)


Synchronous handshakes

Elastic circuits

CLK1 CLK2

Data

Sender ReceiverValid

Ack

• The arrival of data is unpredictable• Handshakes solve the problem


The problem: metastability

Elastic circuits

D Q

CLKS

D Q

?

D

Q

CLKRCLKR

setup hold


Metastability

Elastic circuits

Source: W. J. Dally, Lecture notes for EE108A, Lecture 13.Metastability and Synchronization Failure (or When Good Flip-Flops go Bad) 11/9/2005.


Metastability

Elastic circuits

logic 0 logic 1

metastable


Classical synchronous solution

Elastic circuits

D Q D Q D Q D Q

CLKT CLKR

Wffe

D

rtMTBF

2

Mean Time Between Failures fФ: frequency of the clock fD: frequency of the data tr: resolve time available W: metastability window : resolve time constant

# FFs MTBF

1 FF 15 min

2 FF 9 days

3 FF 23 years

Example


Handshake with synchronizers

Elastic circuits

CLK1 CLK2

Data

Sender ReceiverValid

Ack

• Simple solution• Throughput can be highly degraded:

a long round trip for every transaction


Asynchronous FIFOs

Elastic circuits

Circular buffer

Valid Valid

Ack Ack

Data Data

Clk In Clk Out

FIFO control

• Ack is issued as soon as data has been delivered

• No impact on throughput (1 token/cycle)

• Min latency determined by the internal synchronizers

• Some tricky structures for the FIFO pointers (e.g. Grey encoding)


1 cycle 1 cycle3-4 cycles

SoC design with GALS

Elastic circuits

Bridge

CDC

DSP

P

Fast Bus

Slow Bus

Bridge

CDC

Mem

CLK2

CLK1

CLK3

• Bridges for Clock Domain Crossing usually contain asynchronous FIFOs

• Latency cost only when interfacing with synchronous domains

• No latency penalty between asynchronous domains


Synchronous and Asynchronousmeeting each other

Asynchronia

Collège de France 2013 Elastic circuits

Meanwhile, a small village ofindomitable engineers was resisting the

synchronous occupation …

18

Bill Grundmann(Intel’s director of CAD research,Technical director for CAD technology for the Alpha Microprocessor):

“The specification of a complex system is usuallyasynchronous (functional units, messages, queues, …),

… however the clock appears when we move downto the implementation levels”

(in a technical discussion about system designwith M. Kishinevsky and J. Cortadella, 2004)


Async and Sync meeting each other

Elastic circuits

Async

Sync

• Modular (time elasticity)• But hard to analyze and synthesize

• Easy to analyze and synthesize• Not modular (time rigid)

J. O’Leary and G. Brown, 1997Synchronous emulation of asynchronous circuits

A. Peeters and K. Van Berkel, 2001Synchronous handshake circuits Elastic Circuits

(Sync / Async)

L. Carloni et al., 1999A methodology for correct-by-construction latency-insensitive design

Cortadella et al., Desynchronization, 2003


Different flavors of elasticity

Elastic circuits

+147 … 348201…

…Rigid

+a48…147…

201… 3Asynchronous

+e ……Synchronous Elastic

8 4 37 4 1

1 20…

time


Why synchronous elasticity?• Time is discrete (cycle based), but

unpredictable (unknown number of cycles)

• Examples– Short/long integer addition (8 bits, 64 bits)– Floating-point units– Cache latency: fast hit(2), slow hit(3), miss(>20)– Bus arbitration– Latencies in Network-on-Chip– … and many others


… even at design time

Elastic circuits

ReceiverSender

CLK

Can we add a register without modifying the functionality of the system?


Many systems are already elastic

AMBA AXI bus protocol

Handshake signals


Designing withsynchronous elasticity

Communication channel

Elastic circuits

receiversender

Data Data

Long wires: slow transmission


Pipelined communication

Elastic circuits

sender receiver

DataData

How about if the sender does not always send valid data?



Elastic circuits

sender receiver

DataData



Elastic circuits

sender receiver

DataData

???


The Valid bit

Elastic circuits

sender receiver

Data Data

Valid Valid


The Valid bit

Elastic circuits

sender receiver

Data

Valid

Data

Valid


The Valid bit

Elastic circuits

sender

Data

Valid

receiver

Data

Valid


The Valid bit

Elastic circuits

Data

Valid

sender receiver

Data

Valid

How about if the receiver is not always ready ?


The Stop bit

Elastic circuits

00000

sender

Data

Valid

Stop

receiver

Data

Valid

Stop


The Stop bit

Elastic circuits

11000

sender

Data

Valid

Stop

receiver

Data

Valid

Stop


The Stop bit

Elastic circuits

11100

sender

Data

Valid

Stop

receiver

Data

Valid

Stop


The Stop bit

Elastic circuits

11111

sender

Data

Valid

Stop

receiver

Data

Valid

Stop

Back-pressure


The Stop bit

Elastic circuits

01111

sender

Data

Valid

Stop

receiver

Data

Valid

Stop


The Stop bit

Elastic circuits

00000

sender

Data

Valid

Stop

receiver

Data

Valid

Stop


The Stop bit

Elastic circuits

10000

sender

Data

Valid

Stop

receiver

Data

Valid

Stop

Long combinational path


Relay stations (Carloni, 1999)

Elastic circuits

shell

pearl

sender

shell

pearl

receiver

main main main

aux aux aux



Elastic circuits

main main main

aux aux aux

shell

pearl

receiver

shell

pearl

sender



Elastic circuits

main main main

aux aux aux

shell

pearl

sender

shell

pearl

receiver



Elastic circuits

main main main

aux aux aux

shell

pearl

receiver

shell

pearl

sender

• Handshakes with short wires• Double storage required


Flip-flops vs. latches

Elastic circuits

sender receiver

1 cycle

FF FF



Elastic circuits

sender receiver

1 cycle

H L H L



Elastic circuits

sender receiver

1 cycle

H L H L

Flip-flops already have adouble storage capability, but …



Elastic circuits

sender receiver

1 cycle

H L H L

Not allowed in conventionalFF-based design !



Elastic circuits

sender receiver

1 cycle

H L LH

Let’s make the master/slave latches independent



Elastic circuits

sender receiverH L H L

½ cycle ½ cycle

Let’s make the master/slave latches independent

Only half of the latches (H or L) can move tokens


Synchronous elasticity

Elastic circuits

sender receiver

V V V V

S S S S

En En En En

Data

Valid

Stop

Data

Valid

Stop



Elastic circuits

sender receiver

V V V V

S S S S

En En En En

Data

Valid

Stop

Data

Valid

Stop

1

0



Elastic circuits

sender receiver

V V V V

S S S S

En En En En

Data

Valid

Stop

Data

Valid

Stop

0

0



Elastic circuits

sender receiver

V V V V

S S S S

En En En En

Data

Valid

Stop

Data

Valid

Stop

1

1



Elastic circuits

sender receiver

V V V V

S S S S

En En En En

Data

Valid

Stop

1

1

Data

Valid

Stop



Elastic circuits

sender receiver

V V V V

S S S S

En En En En

Data

Valid

Stop

1

0

Data

Valid

Stop



Elastic circuits

sender receiver

V V V V

S S S S

En En En En

1

0

Data

Valid

Stop

Data

Valid

Stop



Elastic circuits

sender receiver

V V V V

S S S S

En En En En

Data

Valid

Stop

Data

Valid

Stop

1

0


Basic VS block

Si

Eni

Vi

Si-1

Vi-1

VSSi

Eni

Vi

Si-1

Vi-1


Elastic netlists

VS ForkJoin

Join / Fork

Enable signalto data latches

Elastic circuits

VSVS

VS

VS

VS

VS

VS


Join

VS

+

V1

V2

S1

S2

V

S

VS

VS

VS

VS


Lazy Fork

V1

V2

S1

S2

V

S


Eager Fork

Elastic circuits

V1

V2

S1

S2

^

^

V

S


Variable Latency Units

Elastic circuits

[0 - k] cycles

[0 - k] cycles

donego clear

V/S V/S


Design automation

Transforming sync into elastic



Elastic circuits

Behavioralequivalenceis preserved


Elastic Esterel

module ABRO: input A,B,R; output O; loop [ await A || await B ]; emit O each Rend module

Elastic circuitsCollège de France 2013

Marc Galceran Oms, Master thesis, 2007

106

Elastic Esterel

A

B

RO

Boot

PauseReg7

PauseReg11


Elastic Esterel

A

B

RO

Elastic Control Layer

Valid_AStop_AValid_BStop_BValid_RStop_R

Valid_O

Stop_O

Boot

PauseReg7

PauseReg11


Circuit vs. μarchitectural cycles


Synchronous handshake circuits (Peeters, 2001)

Collège de France 2013 Elastic circuits

→

SEQ

xR

R

RWMUX

→

yR

R

RWMUX

*

DMX-

DMX-

DMX <>

DMX <

do

→→ @

áá ññ→

out

int = type [0..255]& gcd: main proc (in? chan <<int,int>> & out! chan int)begin x, y: var int| forever do in?<<x,y>>

; do x <> y then if x < y then y:=y-x else x:=x-y fi od

; out!x odend

Sources:

J. Kessels and A. Peeters.DESCALE: A Design Experiment for a SmartCard Application Consuming Low Energy,in Principles of Asynchronous Circuit Design, A Systems Perspective,Eds., J. Sparso and S. Furber, Kluwer Academic Publishers, 2001.

P.A.Beerel, R.O. Ozdag and M. Ferretti.A Designer’s Guide to Asynchronous VLSI,Cambridge University Press, 2010. 110

Generalization: bounded FIFOs

InOut

B1 B3

B2

Bounded Dataflow Networks


Behavioral equivalence

Elastic circuits

D: a b c d e f g h i j k …

Synchronous:

Elastic:

D: a a b b b c d e e f g g h i i i j k … V: 1 0 1 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 …


Early evaluation

Early evaluation

52

3

x 15


Early evaluation

2

3

x 6


Early evaluation

0

x 0

8


PC+4

Branch targetaddress

Example: mux for next-PC calculation

Take branch

• Only wait for required inputs• Late arriving tokens are cancelled by anti-

tokens

No branch

Early evaluation

Collège de France 2013 Elastic circuits 117

How to implement anti-tokens ?

Valid+ Valid+

Valid–

Valid+

Stop+ Stop+

Valid–

Stop–Stop–

+

-Elastic circuitsCollège de France 2013 118

Dual elastic controllers

S+

V+

V-

S-

S+

V+

V-

S-

En En


Fork/join

Dual fork/join Join with early evaluation


Re-designing for average performance

F

Early evaluation

slow / fast

Fslow

Ffast


H.264 CABAC decoder

Gotmanov, Kishinevsky and Galceran-OmsEvaluation of flexible latencies: designing synchronous elastic H.264 CABAC decoderProc. Problems in design of micro- and nano-electronic systemsMoscow, Oct. 2010 (in Russian)Collège de France 2013 Elastic circuits 122

Profiling


H.264 CABAC decoder


Area vs. Performance

0,90

1,00

1,10

1,20

1,30

1,40

1,50

1,60

1,70

0,50 0,70 0,90 1,10 1,30 1,50 1,70 1,90

Original Optimized

Area

Effective Cycle Time


Conclusions

• Rigid systems preserve timing equivalence(data always valid at every cycle)

• Elastic systems waive timing equivalence to enablemore concurrency

(bubbles decrease throughput, but reduce cycle time)

• A new avenue of performance optimizations can emerge to build correct-by-construction pipelines

Θ Θ


Unifying sync/async elasticity

• J. Carmona, J. Cortadella,M. Kishinevsky and A. Taubin,Elastic Circuits,IEEE Trans. On CAD, Oct. 2009.


Elastic Circuits blending synchronous and asynchronous technologies

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