EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 1 Chapter 3a Instruction Sets: Characteristics and Functions EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 2 What is an Instruction Set? Defines many functions performed by processor. A programmers means of controlling the processor. The complete collection of instructions that are understood by a CPU Machine Code Binary Usually represented by assembly codes EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 3 Elements of an Instruction Operation code (Op code) Do this Source Operand reference To this Result Operand reference Put the answer here Next Instruction Reference When you have done that, do this... Operand - An entity on which operation is performed. reference - address What is an Instruction Set? EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 4 Main memory (or virtual memory or cache) CPU register I/O device Where have all the Operands Gone? EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 5 Instruction Cycle State Diagram EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 6 In machine code each instruction has a unique bit pattern For human consumption (well, programmers anyway) a symbolic representation is used e.g. ADD, SUB, LOAD Operands can also be represented in this way ADD A,B Instruction Representation EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 7 Simple Instruction Format EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 8 Data processing: Arithmetic and logic Instruction Data storage (main memory): memory Instruction Data movement (I/O): I/O Instruction Program flow control: Test and branch Instruction Instruction Types EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 9 One of traditional ways of describing processor architecture and 3 Addresses use Program Counter for next instruction. 4 addresses May be a forth - Operand 1, Operand 2, Result and next instruction (usually implicit) Not common Needs very long words to hold everything 3 addresses Operand 1, Operand 2, Result a = b + c; Number of Addresses (a) EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 10 2 addresses One address doubles as operand and result a = a + b Reduces length of instruction Requires some extra work Temporary storage to hold some results Number of Addresses(b) EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 11 1 address Implicit second address Usually a register (accumulator) Common on early machines Number of Addresses (c) EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 12 0 (zero) addresses All addresses implicit Uses a stack (top two), stack is a LIFO set of locations e.g. c = a + b push a push b add pop c Stack special memory organization Number of Addresses (d) EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 13 ExerciseExercise Given the following expression: c = a + b Using the zero address format, write the instructions and sketch the stack operation. EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 14 ?????????? f = a - b c + (d x e) EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 15 More addresses More complex (powerful?) instructions More registers Inter-register operations are quicker Fewer instructions per program (Fig 10.3 p/g 325 stalling) Fewer addresses Less complex (powerful?) instructions More instructions per program Faster fetch/execution of instructions How Many Addresses EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 16 Operation repertoire How many ops? What can they do? How complex are they? Data types Instruction formats Length of op code field Number of addresses Instruction Set Design Decisions (1) EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 17 Registers Number of CPU registers available Which operations can be performed on which registers? Addressing modes RISC vs CISC Design Decisions (2) EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 18 Addresses Numbers Integer/floating point Characters Sequence of bits ASCII (same as IRA)etc. each character uses a unique 7-bit pattern, which leads to 128 different characters that can be represented in such manner. Logical Data Bit-oriented view Bits or flags IRA-international Reference Alphabet ASCII American Standard Code for Information Interchange. Types of Operands EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 19 8 bit Byte 16 bit word 32 bit double word 64 bit quad word Addressing is by 8 bit unit A 32 bit double word is read at addresses divisible by 4 Pentium Data Types EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 20 General - arbitrary binary contents Integer - single binary value Ordinal - unsigned integer Unpacked BCD - One digit per byte Packed BCD - 2 BCD digits per byte Near Pointer - 32 bit offset within segment Bit field Byte String Floating Point Specific Data Types EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 21 Pentium Numeric Data Formats EKT 422/4 COMPUTER ARCHITECTURE SoME-0809-I 22 8 (byte), 16 (halfword), 32 (word) and 64 (doubleword) length data types Some instructions need operand aligned on 32 bit boundary Can be big- or little-endian Fixed point processor recognises: Unsigned byte, unsigned halfword, signed halfword, unsigned word, signed word, unsigned doubleword, byte string (