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Transcript of Eidgenossische¨ Ecole polytechnique federale de Zurich´´ … · 2015. 12. 24. · tro duction to...
Zurich¨Technische HochschuleEidgenossische¨
Swiss Federal Institute of Technology ZurichPolitechnico federale di ZurigoEcole polytechnique federale de Zurich´ ´
Signal and Information Processing Laboratory, ETH Z�urich
Department of Communications and Integrated Systems,
Tokyo Institute of Technology
Diploma Thesis
1.05 GHz VCO for a BS-Receiver
in 0.35�m CMOS
Matthias U. Frey
Advisors:
Prof. Dr. F. Eggimann, ETHZ
Prof. Dr. S. Takagi, Titech
Dr. F. Lustenberger, ETHZ
March 13, 2001
aufgabenstellung1...
II
aufgabenstellung2...
III
aufgabenstellung3
IV
"What I crave is simplicity."
{ Edward Weston
Abstract
Voltage controlled oscillators (VCOs) are among the most important
components of modern receivers and their design is a challenge to the
analog IC designer. In order to comply with the very stringent speci�cations
demanded by modern communication devices, passive components with
low parasitics and low-power, low-noise active elements at high frequencies
are required. VCOs with a large tuning range as well as an excellent phase
noise performance are essential.
This diploma thesis discusses the design of a low phase noise radio
frequency voltage controlled oscillator (RF VCO) used for a monolithic
implementation of a Broadcasting Satellite Receiver (BS Receiver). Initially,
the VCO's speci�cations had to be determined, as there are no known
speci�cations available. The VCO is used as a mixer's local oscillator,
therefore, to minimize the VCO's phase noise was a priority: A low phase
noise RF VCO with a midfrequency of 1.05 GHz is needed.
The �rst part of the thesis provides an introduction to BS Receivers, to
the di�erent RF VCO topologies and their characteristics and to phase noise.
The VCO's speci�cations were determined and the optimal topology, in
regard to these speci�cations, was established. A complementary di�erential
LC VCO was found to yield the best overall performance. Its elements were
derived from calculations and simulations in Hspice. The layout of the entire
LC VCO was completed, using a 0.35 �m standard CMOS process. The
thesis is concluded with a summary of the results, with a comparison of this
VCO with other recently published RF VCOs and with a presentation of
possibilities for future research.
Zusammenfassung
Spannungsgesteuerte Oszillatoren (Voltage Controlled Oscillators,
VCOs) geh�oren zu den wichtigsten Baubl�ocken moderner Empf�anger. Ihre
Entwicklung stellt in jeder Technologie eine Herausforderung dar, da passive
Komponenten mit kleinen parasit�aren E�ekten und leistungs- und rauschar-
me aktive Elemente bei hohen Frequenzen ben�otigt werden. Nur so k�onnen
die sehr strikten Anforderungen, welche moderne Kommunikationsmittel
stellen, erf�ullt werden; ein gen�ugend grosser Frequenzaussteuerbereich wird
ebenso verlangt wie niedriges Phasenrauschen.
Die vorliegende Diplomarbeit besch�aftigt sich mit der Entwicklung
eines phasenrauscharmen Hochfrequenz (Radio Frequency, RF) VCO's
f�ur die Verwendung in einem monolithischen \Broadcasting Satellite"-
Empf�angersystem (BS-Empf�anger). Die Spezi�kationen des VCO's mussten
zuerst hergeleitet werden, weil es f�ur VCOs in BS-Empf�angern keine ge-
nauen Spezi�kationen gibt. Da der VCO als Lokaloszillator eines Mischers
dient, wurde vor allem auf niedriges Phasenrauschen Wert gelegt: Ein
rauscharmer RF VCO mit der Mittenfrequenz 1.05 GHz wird ben�otigt.
Der erste Teil der Arbeit vermittelt eine Einf�uhrung zu BS-Empf�angern,
zu den verschiedenen RF VCO-Typen und deren Charakteristiken und zum
Thema Phasenrauschen. Die Spezi�kationen des VCO's wurden hergelei-
tet und die ideale Topologie des VCO's bestimmt. Es wurde ein komple-
ment�arer di�erentieller LC VCO gew�ahlt, da dessen Charakteristik bez�uglich
der Spezi�kationen am idealsten ist. Mittels Handrechnungen und Simula-
tionen konnten die verschiedenen Elemente des LC VCO's charakterisiert
werden. Das Layout der kompletten Schaltung wurde mit den Daten f�ur ei-
ne 0.35 �m CMOS Standardtechnologie entworfen. Die Diplomarbeit wird
mit der Pr�asentation der erhaltenen Simulationsresultate, mit einem Ver-
gleich mit bereits existierenden RF VCOs und mit Vorschl�agen f�ur weitere
Forschung abgeschlossen.
Acknowledgements
This thesis indebted me to many people:
First, I would like to thank my diploma professor, Prof. Dr. F. Eggi-
mann, for helping me organize this thesis abroad, for his encouraging mails
and words and for his unceasing support during the course of this thesis.
I would like to thank Prof. Dr. S. Takagi for accepting me as a research
student at the FNT-Lab and thereby providing me with the opportunity of
studying in his fascinating country, for proposing the research topic and for
his help taking care of all the necessary procedures.
Most of all I am indebted to Dr. Felix Lustenberger for his astounding
support from abroad, his superior technical knowledge, his encouraging
mails and for all the time he spent helping me.
Many thanks to my \technical sta�", Hajime Shibata and Sohrab
Emami, for sharing their great technical abilities, for their kind help and
the fruitful discussions at all times.
I am also grateful to Meng Mei Cheong (cultural and culinary support),
my tutor Kohsuke Suzuki, Nicodimus Retdian (Cadence), Dr. Kazuyuki
Wada, Takahide Sato (Dracula), Tetsu Ohshima and Kouhei Hosokawa
(unix) and all the other members of the FNT-Laboratory for creating such
a friendly atmosphere.
Donhee Ham (Caltech), Dr. Ali M. Niknejad (ex-UC Berkeley) and
Dr. Alain-Serge Porret (ex-EPFL) kindly explained me their research via
e-mail. Thank you!
VIII
I am thankful to Mrs. R. Gilli of the Foreign Students OÆce at ETHZ
and Prof. Dr. H. Tschirky for their help in organizing a gratifying stay in
Tokyo. I am also indebted to the A. Karolus Fond, who supported my trip
to Japan �nancially.
Last but not least I would like to thank my parents and my sisters
for arousing my technical curiosity, for supporting me during all stages of
my education and most of all for making me aware that there are other
countries besides Switzerland.
Tokyo, March 13, 2001
Matthias U. Frey
IX
Contents
Project Description II
Abstract VII
German Abstract VIII
Table of Contents X
List of Figures XIII
1 Preface 1
1.1 Broadcasting Satellite Receiver - a Brief Description . . . . . 1
1.2 Low Noise Voltage Controlled Oscillators (VCOs) . . . . . . . 3
2 Introduction 4
2.1 The Family of VCOs . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.1 Ring oscillators . . . . . . . . . . . . . . . . . . . . . . 5
2.1.2 LC Oscillators . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Noise in VCOs . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 The Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Speci�cations . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Design Issues 12
3.1 Deciding on the Topology . . . . . . . . . . . . . . . . . . . . 12
3.2 The Key Elements of a Complementary Di�erential LC VCO 13
3.2.1 The LC Tank . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.2 The Cross Coupled Pairs . . . . . . . . . . . . . . . . 15
3.2.3 The Current Source . . . . . . . . . . . . . . . . . . . 15
X
4 Design and Simulation of an LC VCO 16
4.1 Simulation of an LC VCO . . . . . . . . . . . . . . . . . . . . 16
4.2 Determining the Elements of a Complementary Di�erential
LC VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2.1 The Spiral Inductor . . . . . . . . . . . . . . . . . . . 17
4.2.2 The Cross Coupled Pairs . . . . . . . . . . . . . . . . 19
4.2.3 The Varactors . . . . . . . . . . . . . . . . . . . . . . 23
4.2.4 The Current Source . . . . . . . . . . . . . . . . . . . 30
4.3 Phase Noise of the LC VCO . . . . . . . . . . . . . . . . . . . 32
4.4 Simulation of the Complete LC VCO . . . . . . . . . . . . . . 36
5 Layout of the LC VCO 39
5.1 Layout Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2 The Spiral Inductors . . . . . . . . . . . . . . . . . . . . . . . 40
5.3 The Cross Coupled Pairs . . . . . . . . . . . . . . . . . . . . . 40
5.4 The Varactors . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.5 The Current Source . . . . . . . . . . . . . . . . . . . . . . . 42
5.6 The Complete Layout . . . . . . . . . . . . . . . . . . . . . . 43
5.7 Extraction and Simulation of the Layout's Equivalent Circuit 43
6 Concluding Remarks 46
6.1 Summary of the Simulation Results . . . . . . . . . . . . . . . 46
6.2 Comparison with Recent Publications . . . . . . . . . . . . . 47
6.3 Further Research . . . . . . . . . . . . . . . . . . . . . . . . . 48
A Hspice Simulation Files 49
A.1 Subcircuit: Spiral Inductor . . . . . . . . . . . . . . . . . . . . 49
A.2 Subcircuit: MOSCAP Varactor . . . . . . . . . . . . . . . . . 50
A.3 Subcircuit: MOSCAP Varactor Extracted from the Layout . . 50
A.4 VCO with Ideal Capacitors, Ideal Current Source and Non-
Ideal Spiral Inductor . . . . . . . . . . . . . . . . . . . . . . . 51
A.5 VCO with Ideal Current Source, Varactors and Spiral Induc-
tors for Measuring Tunability . . . . . . . . . . . . . . . . . . 53
A.6 VCO with Non-Ideal Current Source, Varactors and Spiral
Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
A.7 VCO including all Parasitic Capacitances and some Resistances 56
XI
A.8 Finding the Equivalent Parallel Resistance of the LC Tank at
Resonance Frequency . . . . . . . . . . . . . . . . . . . . . . . 59
A.9 Determining the Q-Factor of the Varactor and its Series Re-
sistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
B Picture Gallery 61
C Environment 65
Bibliography 67
XII
List of Figures
1.1 Structure of a Broadcasting Satellite Receiver . . . . . . . . . 2
2.1 The spectrum of a non-ideal oscillator. . . . . . . . . . . . . . 7
2.2 Typical plot of the phase noise versus the o�set from the
carrier of a VCO. . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Schematic of a simple and a complementary di�erential VCO 12
3.2 Schematic of a complementary di�erential LC VCO . . . . . . 13
4.1 Metal Layer 3 and 2 of the stacked spiral inductor . . . . . . 18
4.2 Equivalent circuit of the spiral inductor . . . . . . . . . . . . 19
4.3 The parasitic series resistance Rs can be transformed to a
parallel resistance Rp. . . . . . . . . . . . . . . . . . . . . . . 19
4.4 In case of resonance (1.05 Ghz), the peak of the amplitude
corresponds to the equivalent parallel resistance Rp of the LC
tank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 (a) The schematic of the VCO, (b) schematic of the half cir-
cuit, (c) half circuit at resonance frequency, (d) simpli�ed
schematic of the half circuit at resonance frequency. . . . . . 21
4.6 The current Ibias gets switched from one side to the other. . . 22
4.7 The circuit was simulated using Hspice, evidently verifying
the calculated values. . . . . . . . . . . . . . . . . . . . . . . . 23
4.8 The output voltage is as expected about 2.5 V while the os-
cillation frequency lies at 1.05 GHz. . . . . . . . . . . . . . . 24
4.9 The capacitances of a MOSFET. . . . . . . . . . . . . . . . . 25
4.10 The varactor's equivalent circuit. . . . . . . . . . . . . . . . . 25
4.11 (a) The equivalent circuit of the VCO, (b) AC equivalent
circuit, (c) simpli�ed AC equivalent circuit. . . . . . . . . . . 26
XIII
4.12 This schematic was simulated to determine the correct size of
the MOSCAP varactor, M1, and its Q-factor. . . . . . . . . . 27
4.13 Gate capacitance of the varactor versus its gate to
source/drain voltage. . . . . . . . . . . . . . . . . . . . . . . . 27
4.14 The resonator gets tunable using the gate capacitance of a
pMOS varactor. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.15 Direct coupling: The voltage across the varactor does not stay
constant, as the output is oscillating. . . . . . . . . . . . . . . 29
4.16 Sweep over di�erent gate lengths. By increasing the gate
length from 0.7 �m to 1.05 �m, the tuning range could be
increased. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.17 The VCO is now tunable from 955 MHz to 1110 MHz. . . . . 30
4.18 Schematic of the VCO with all the noise sources included. . . 33
4.19 Schematic of the complete VCO including all the transistor
dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.20 Simulation result of the complete VCO, in the time- and in
the frequency-domain. . . . . . . . . . . . . . . . . . . . . . . 37
4.21 The frequency versus tuning voltage characteristic is fairly
linear from 0.5 V to 1.7 V. . . . . . . . . . . . . . . . . . . . . 38
5.1 The varactors were split up into even parts and cross-connected. 42
5.2 The current mirror was split up and made symmetric. . . . . 42
5.3 The VCO can be tuned from 962 MHz to 1110 MHz. . . . . . 44
5.4 The LC VCO has an output voltage of Vpp=4.4 V. . . . . . . 44
5.5 The LC VCO's tuning characteristic is fairly linear for
Vtune=0.5V to Vtune=1.7V. . . . . . . . . . . . . . . . . . . . 45
B.1 The di�erent patterns and colors used by Cadence for the
various layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
B.2 The layout of the two spiral inductors. . . . . . . . . . . . . . 61
B.3 The layout of the nMOS and the pMOS cross coupled pairs. . 62
B.4 The layout of the two varactors. . . . . . . . . . . . . . . . . 62
B.5 The layout of the completely symmetric current source. . . . 63
B.6 The layout of the LC VCO and all the terminals. . . . . . . . 63
B.7 The layout of the completely symmetric LC VCO. . . . . . . 64
XIV
Chapter 1
Preface
The goal of this diploma thesis is the design and the implementation
of a low noise voltage controlled oscillator (VCO) for a fully monolithic
Broadcasting Satellite (BS) Receiver. The design of this VCO is part of
a student's research project at the Department of Communications and
Integrated Systems, Tokyo Institute of Technology in Japan.
The �rst chapter gives a brief description of the BS Receiver and its
VCO. The second chapter focuses on the di�erent VCO types, its advan-
tages and disadvantages and on noise and phase noise of VCOs. In the third
chapter, according to the given speci�cations, the topology of the VCO is
depicted and the key-elements of the VCO are listed. The fourth chapter
describes the simulation of the VCO and how the parameters of the ele-
ments are found. Some phase noise calculations are also demonstrated. The
layout of the LC-VCO is explained in the �fth chapter and the simulation
of the circuit including the inserted parasitic elements is introduced. Chap-
ter six concludes with experimental results and with suggestions for further
research.
1.1 Broadcasting Satellite Receiver - a Brief De-
scription
The Broadcasting Satellite (BS) system is a Japanese system for broad-
casting high-quality television signals. The structure of the BS Receiver
is illustrated in Figure 1.1. The carrier frequency is at 13 GHz which
1
Chapter 1 Preface
will be down-converted o�-chip to 1.3 GHz. After being ampli�ed with a
low noise ampli�er (LNA), this �rst intermediate frequency (IF1) signal
will be down-converted to a second intermediate frequency signal (IF2)
with a center frequency of 134 MHz. This is achieved by multiplying
the IF1 signal with the output signal of the voltage controlled oscillator
(VCO) implemented in this thesis. By changing the frequency of this VCO,
di�erent channels could be selected. This circuit, however, does not allow
choosing di�erent channels - the VCO only has one midfrequency1. In order
to compensate frequency-drift due to varying temperature and process
parameters, the VCO output frequency will be adjusted automatically
using a channel detector loop. The IF2 will then be down-converted and
frequency demodulated into the baseband. The spectrum of the signal is
split up by a lowpass and a highpass �lter (divider) into an audio (between
4.5 MHz and 6.5 MHz) and a video signal (below 4.5 MHz) respectively.
LNA VCOx
IF-Amp BPF limiterAGC
FM de-modulator
Channel selector (ch7, ch9)
channeldetector
DividerAudio-SignalVideo-Signal
38.36MHz
19.18MHz
27MHz
1203MHz1165MHz 1068.74MHz1030.74MHz
134.26MHz96.26MHz
172.26MHz134.26MHz
ch7 ch9
ch7 ch 9
ch7 ch9
ch9
ch7
134.26MHz
4.5MHz 6.5MHz
AudioVideo
4.5MHz 6.5MHz
Video
4.5MHz 6.5MHz
Audio
Figure 1.1: Structure of a Broadcasting Satellite Receiver
1In the �rst project description the circuit was supposed to be able to switch between
channel 7 and 9, but this feature was dropped in order to make the whole circuit less
complex.
2
Chapter 1 Preface
1.2 Low Noise Voltage Controlled Oscillators
(VCOs)
Fully monolithic VCOs are among the key components of receivers.
They present numerous challenges to any technology, since they require
low-parasitic passive components and low-power active devices at high
frequencies to obtain an acceptable tuning range and low phase noise. The
requirements on VCOs have become more stringent, especially due to the
recent growth of wireless telecommunications and the resulting decrease of
available bandwidth per channel. This limited bandwidth stands in direct
relations to the more demanding noise-requirements of VCOs. Another
opposing condition on minimizing the phase noise ist that most wireless
devices have to be battery-operated. The power-consumption, therefore,
should be minimized.
As the VCO described in this thesis will be used for the down-conversion
of an RF input signal, the speci�cations are set so as to minimize phase
noise, without setting overly tight conditions on the power consumption of
the circuit.
3
Chapter 2
Introduction
2.1 The Family of VCOs
Many di�erent VCO topologies exist, each suited for di�erent purposes, dif-
ferent frequencies or di�erent tuning-ranges. VCOs are mainly characterized
by the following properties:
Center Frequency: The midrange frequency value is determined by the
application the VCO is used for.
Tuning range: The tuning range is determined by the frequency range
necessary for the application and by the variation of the VCO center
frequency due to temperature and process variations.
Phase noise: The amount of phase noise is a measure de�ning the spectral
purity of the VCOs output signal.
Power consumption: The power consumption is de�ned as the amount
of power the VCO core dissipates.
The latter three properties are strongly related to one another. Simpli-
�ed, it can be said that the higher the power consumption or the smaller
the tuning range, the less phase noise the circuit exhibits [1]. Therefore, a
trade-o� among these properties has to be made when de�ning the ideal
point of operation.
Only two di�erent concepts for oscillators in the gigahertz frequency
range seem to exist: LC oscillators (using passive or active inductances)
4
Chapter 2 Introduction
and ring oscillators. Both can be implemented in di�erential or single-ended
mode.
2.1.1 Ring oscillators
Ring oscillators have the great advantage of not using any passive elements
which are usually very big and may even require special processing. Their
tuning range can be very wide (> 50%), but the phase noise performance
limits their use in most wireless systems. Interpolating ring oscillators seem
to o�er less phase noise, but again their tuning range is smaller (� 20%) [2].
2.1.2 LC Oscillators
LC oscillators are a well discussed topic today. As the passive induc-
tors (ideally) do not introduce any noise into the circuit, they o�er the
best phase noise performance among all oscillator types. Their disad-
vantage lies in the limited tuning range and in the size of the passive
elements. In addition, they might require special processing steps to
optimize the performance of the passive elements; this greatly increases
the cost of the CMOS process. The limited tuning range may be overcome
by the use of a set of resonators instead of using only a single resonator,
as demonstrated in [3]. This, however, increases the VCO's size even further.
The Q-factor of the LC tank is among the most important parameters
in an LC oscillator, as the phase noise times power consumption depends
mainly on the Q-factor of the tank [4], [5].
The limiting element of the Q-factor of the LC tank is mainly the
Q-factor of the inductor, caused by its resistive loss and the resulting
eddy currents in the substrate. In order to overcome this limiting factor,
either bond-wires are used as inductances, or discrete external LC tanks
are applied. Bond-wires have the disadvantage of having a large spread
in inductance of about 20% - this is diÆcult to compensate with the
tunability of the VCO. External LC tanks are often not appreciated, as
fully monolithic circuits are desired. A highly predictable and repeatable
alternative is the use of planar spiral inductors that feature less spread
(� 5%). They, however, o�er greater resistive losses, causing the Q-factor
to decrease [4]. Many ways of improving the Q-factor have been proposed.
5
Chapter 2 Introduction
By using shielding techniques for the spiral inductor, eddy currents in the
substrate can be reduced; by using thicker metal layers, the resistive losses
can be reduced [6], [7]. Tuning of the oscillator is achieved by using variable
capacitances: \Varicap" diodes, accumulation mode MOSFETs or inversion
mode MOSFETs are possible choices [8].
LC oscillators using active inductances have been introduced in recent
experiments [9], [10]. An active inductance uses active elements (e.g.
transistors) to transform the impedance of a capacitance to behave like the
impedance of an inductance. Although the Q-factor of the active LC tank
may be favorable [11], the phase noise is still higher, because the active
elements introduce further noise. Another problem are process variations,
which make it diÆcult to control the greatly desired high Q-factor of the
active LC tank.
The advantages of such active inductance LC oscillators are evident:
the circuits are signi�cantly smaller, no extra processing steps are required
and the tuning range may be higher. All these extra bene�ts are bought
at the expense of increased phase noise, making it less riveting for wireless
applications.
2.2 Noise in VCOs
The output of an ideal sinusoidal oscillator can be written as:
Vout(t) = Acos[!ot+ �] (2.1)
where A is the amplitude of the signal, !0 the frequency and � a constant
phase reference. The spectrum of this ideal oscillator shows a pair of impulses
at �!0. A more general (and more realistic) expression of the output of an
oscillator is given by equation (2.2).
Vout(t) = A(t)f [!ot+ �(t)], f : 2�-periodic (2.2)
The time-varying amplitude and phase introduce sidebands to the oscil-
lator's spectrum close to the oscillation frequency !0. To quantify this noise,
a unit bandwidth is considered at a certain o�set frequency �! from !0 as
shown in Figure 2.1.
6
Chapter 2 Introduction
���
��
���
Figure 2.1: The spectrum of a non-ideal oscillator.
The noise power in this unit bandwidth is calculated and then divided
by the carrier power as depicted in equation (2.3).
Ltotal(�!) = 10 � log�Psideband(!0 +�!; 1Hz)
Pcarrier
�(2.3)
Psideband(!0+�!; 1Hz) stands for the single sideband power at a frequency
o�set �! from the carrier with a bandwidth of 1 Hz. The units used in this
expression are in [dBc/Hz] and the phase noise is usually calculated at an
o�set frequency of 100 kHz or 600 kHz. A speci�cation requiring a phase
noise of -100 dBc/Hz at 100 kHz o�set means that the phase noise power
per unit bandwidth must be -100 dB below the carrier power at an o�set
of 100 kHz from the carrier.
It is important to note that the de�nition in equation (2.3) includes the
noise introduced by amplitude as well as phase uctuations (A(t), �(t)). As
the noise contributed by amplitude uctuations can be easily removed (e.g.
by using limiters), the main portion of noise Ltotal(�!) is contributed by
phase noise, Lphase(�!), which will be simply denoted as L(�!).
Due to the growing interest in low noise oscillators, many recent scien-
ti�c publications discussed the noise of VCOs [5], [6], [12], [13]. The �rst
proposed electrical oscillator noise model dates back to D. B. Leeson and
L. S. Cutler, namely the Leeson-Cutler phase noise model [14]. They intro-
duced \a heuristic derivation, presented without formal proof" predicting
the following single sideband (SSB) phase noise for an LC tank oscillator:
7
Chapter 2 Introduction
L(�!) = 10 � log(2FkT
Ps�"1 +
�!0
2QL�!
�2#)
� 10 � log(2FkT
Ps��
!02QL�!
�2)(for �! � !0
2Q) (2.4)
where �! is the o�set frequency from the carrier, QL the Q-factor
of the LC tank, F the excess noise factor (noise contribution from
the active devices), k the Boltzmann's constant, T the absolute tempera-
ture and Ps the average power dissipated in the resistive part of the LC tank.
There are two problems related to this model: Although oscillators are
highly non-linear, this is a linear model. Additionally, F is circuit speci�c
and can, therefore, not be determined a priori; it has to be determined by
measurement. Nevertheless, this relatively simple equation shows, that by
increasing the carrier power or the Q-factor of the LC tank, the phase noise
performance of the oscillator can be improved.
Without any further explanations, measurements show that the noise
skirts around the carrier frequency have the following characteristics [5]:
- The noise spectral density is inversely proportional to the frequency
o�set from the carrier, except very close to the carrier, where the
in uence of up-converted icker noise dominates.
- The noise skirt is symmetric above and below the carrier-frequency.
The equivalent to phase noise in the time domain is jitter on the zero-
crossing of the output signal.
- It is widely believed that by doubling the Q-factor of the LC-tank, the
oscillator's noise spectral density to carrier ratio is increased by 6 dB.
The typical plot of the phase noise of an oscillator is shown in Figure
2.2 [15]. The 1=f3-corner is the frequency of the point between the 1=f3
and the 1=f2 regions.
Linear time variant (LTV) models give us further insight into the
behavior of phase noise - they are capable of predicting phase noise
8
Chapter 2 Introduction
������
������
�� �������� ������������������
�������������� ����
��������������
�������������� ����
������� ��������
!����
� ��������"���� �������� �������
���� ��������
�����#�����������#������
��
Figure 2.2: Typical plot of the phase noise versus the o�set from the carrier
of a VCO.
accurately at a small, as well as at a large o�set from the carrier frequency.
LTV models depict that noise added at di�erent stages of the oscillation
cycle, a�ect the oscillator's output di�erently; linear time invariant (LTI)
models do not consider this aspect at all, they treat all instants as equals
[12]. By applying the insights gained from LTV models, a powerful way of
suppressing the 1=f -noise of MOSFET-Oscillators can be found [7].
The LTV model proposed in [12] is rather complex and the derivation
of the impulse sensitivity function � (ISF) is very time-consuming. The ISF
describes the time-varying sensitivity of the oscillator's phase to noise. A
less precise but easier way of computing the phase noise of an oscillator, is
by approximating �. �rms is the RMS value of the ISF for a noise source
and is 1=p2 for an ideal sine [16], [17], [18]. Phase noise in the 1=f2-region
can, therefore, be computed using equation (2.5).
L(foff ) =1
8�2f2off� �
2rms
q2max
�Xn
i2n�f
!(2.5)
� 1
16�2f2off� 1
q2max
�Xn
i2n�f
!(2.6)
foff is the o�set frequency of the carrier and qmax the total charge swing
of the LC tank.P
n
�i2n
�f
�is the sum of the current noise densities of individ-
9
Chapter 2 Introduction
ual noise sources. Using formula (2.6), the phase noise of an oscillator in the
1=f2-region can be roughly computed. In [17] the estimate using equation
(2.6) was only 1 dB di�erent from simulation results, legitimizing the use of
this formula.
2.3 The Technology
The VCO will be fabricated using a 0.35 �m CMOS standard process by
ROHM. This process provides 3 metal layers and allows stackable vias.
ROHM o�ers Level 28 models that can be used with Hspice. The extrac-
tion models for Dracula only include parasitic capacitances but no sheet-
resistances. A very stern Non-Disclosure Agreement (NDA) applies to this
CMOS process, no further information can therefore be published.
2.4 Speci�cations
As there are no speci�cations for the down-converting VCO of a BS-Receiver
available, and the other parts of the BS-Receiver were not yet designed, the
following speci�cations were found to be proper:
Voltage supply : 3V
Supply current : max. 10mA
Control voltage : 0� 3V
Frequency range : 1050MHz � 5%
Magnitude of output signal : > 2Vpp
Phase noise : < �100 dBc=Hz @ 100 kHz o�set
from center frequency
Process technology : 0:35 �m CMOS (Rohm)
The supply voltage, as well as the tuning voltage, were speci�ed by the
project group. The VCO's midfrequency was set so that by multiplying the
VCO's output signal with the �rst intermediate frequency (IF1) signal, a
speci�ed channel can be extracted. The tuning range should be suÆcient for
compensating drifting parameters. The phase noise speci�cations are derived
from DCS-1800 speci�cations [19]. These slightly weakenend speci�cations
should be suÆcient for the BS Receiver's VCO. The supply current and the
magnitude of the output voltage were set after having consulted publications
describing VCOs with similar phase noise and tuning range characteristics.
10
Chapter 2 Introduction
The power dissipation is not that crucial, as the BS Receiver is not a battery-
operated device.
11
Chapter 3
Design Issues
3.1 Deciding on the Topology
The �rst step in designing a VCO is deciding what type of oscillator and
which topology should be used. Considering the importance of minimizing
the phase noise for the down-mixing oscillator, we decided to use a passive-
LC resonater based oscillator. There are di�erent well studied types of LC
oscillators, o�ering di�erent characteristics. Even though the resonators are
kept identical, the two topologies illustrated in Figure 3.1 can show signi�-
cantly di�erent phase noise performance due to a higher output amplitude
of the complementary di�erential VCO [1], [13], [20]. The output voltage
of this structure is approximately a factor of two larger than that of the
nMOS-only structure.
$��
!� !�
% %
&�� �
$��
!� !�% %
&�� �
Figure 3.1: Schematic of a simple and a complementary di�erential VCO
12
Chapter 3 Design Issues
In the 1 GHz frequency range, pMOSFETs are still fast enough to be
used, therefore, the use of a complementary LC oscillator was decided. As
this circuit shows both left-right and bottom-top symmetry, it is also referred
to as \doubly symmetric VCO" [7]. Best phase noise performance of fully
monolithic VCOs in the speci�ed frequency range was reported for using the
circuit shown in Figure 3.2 [13], [16], [17], [18].
$��
!� !�
% %
&�� �
'
'�
'(
'
'%'%�
$����
Figure 3.2: Schematic of a complementary di�erential LC VCO
3.2 The Key Elements of a Complementary Dif-
ferential LC VCO
The doubly symmetric LC VCO, as shown in Figure 3.2, consists of the
following elements:
L: Integrated spiral inductances
C: Varactors (variable capacitances) determine
the oscillation frequency
M1, M2, M3, M4: Cross coupled pairs for negative resistance,
realized in nMOS and pMOS
MC1, MC2: Simple current mirror used as a current source
13
Chapter 3 Design Issues
3.2.1 The LC Tank
The frequency-determining element of the oscillator is the LC tank; its res-
onance frequency is de�ned in equation (3.1).
fres =1
2�pLC
(3.1)
As the inductance is �xed, the value of the capacitor has to be control-
lable. Therefore, varactors (variable capacitors) instead of simple capacitors
are used. Di�erent methods of implementing inductances monolithically
exist: coplanar wave guides (in the multiple gigahertz frequency range only)
or spiral silicon inductors. As the resonator should oscillate at 1.05 GHz,
spiral silicon inductors will be used.
The Q-factor of an LC tank is composed of the Q-factor of the inductors
and the Q-factor of the capacitors (or varactors for VCOs) as described in
equation (3.2).
1
Qtot=
1
QL+
1
QC(3.2)
The Q-factor of a monolithic LC tank is limited mainly by the inductor;
its Q-factor lies usually below 10 [7]. The Q-factor of an inductor QL is
de�ned as 2� times the ratio of the stored energy and the dissipated energy
per cycle [21]:
Q = 2�Peak energy stored
Energy loss=cycle, or (3.3)
Q =Im(Z)
Re(Z)(3.4)
Z is the impedance of the inductor.
The Spiral Inductance
Concerning its Q-factor, the inductor is the most important part of the LC
tank. The inductance of a spiral inductor can be computed using easy to
handle equations [7] or by using simulators specialized on modelling and
designing spiral inductors [22], [23]. These simulators also compute the pa-
rameters of the equivalent circuit of the spiral inductor. In order to minimize
14
Chapter 3 Design Issues
resistive losses, multiple layer spirals with coupled magnetic �elds can be
used [6].
The Varactor
Di�erent ways of designing a varactor have been investigated in various
scienti�c publications [24], [25], [26], [27]; junction diodes, MOS capacitors
and accumulation mode capacitors are some of the possibilities. The ratio
determining the tuning range, which is Cv;max=Cv;min, ought to be maxi-
mized. This ratio is restricted by physical limitations of the varactor. The
tuning range of the VCO is further limited ascribable to the non-varying
(mostly parasitic) capacitances in parallel to the varactors. Another impor-
tant performance parameter is the capacitance vs. tuning-voltage character-
istic C(Vtune), in which case mainly a linear characteristic is appreciated. By
using a folded layout, the series resistance of the varactor can be minimized.
This maximizes QC , the corresponding Q-factor [8], [27].
3.2.2 The Cross Coupled Pairs
The resonator of an LC oscillator cannot maintain steady oscillation by
itself, due to the energy lost in the parasitic resistances of the LC tank. The
cross-coupled pairs provide negative resistance to replenish the lost energy
and sustain the oscillation. The negative resistance is obtained using positive
feedback [28].
3.2.3 The Current Source
The design of the current source does not seem as crucial as the design of
the other parts. Its main characteristics are the output resistance and the
saturation voltage. Having a high output resistance results in only small
voltage changes at the source of M1 and M2, minimizing the harmonic dis-
tortion. A low saturation voltage allows a high output voltage swing. Again,
this results in a trade-o�. The e�ects of a tail capacitor are discussed in
[13]. Brie y, a tail capacitor can improve the phase noise performance of the
di�erential LC VCO, but it reduces the output impedance of the current
source at high frequencies.
15
Chapter 4
Design and Simulation of an
LC VCO
4.1 Simulation of an LC VCO
The diÆculty of simulating an oscillator lies in its truly nonlinear behavior.
Therefore, no AC analysis, a small signal analysis method, will lead to
meaningful results. Using Hspice, only simulations in the time domain,
transient simulations, are possible for the simulation of an oscillator[29].
To transform the signals from the time-domain into the frequency-domain,
fourier transform functions are available. Transient simulations are very
time consuming and phase noise cannot be measured accurately.
Level 28 models are Meta-Software proprietary models to be used with
Hspice; they are provided by ROHM. The Level 28 model o�ers the MOS-
FET capacitance model CAPOP 13 [30]. This was used to determine the
capacitance versus gate-to-drain/source voltage of the varactor.
4.2 Determining the Elements of a Complemen-
tary Di�erential LC VCO
After having decided on the VCO topology (see schematic in 3.2), the �rst
step was to determine the parameters of the spiral inductor.
16
Chapter 4 Design and Simulation of an LC VCO
4.2.1 The Spiral Inductor
The spiral inductor is very important in maximizing the phase noise of the
VCO. In order to minimize the up-conversion of device 1=f -noise, the LC
tank should be designed completely symmetric. Therefore, the inductance
is split into two equal parts.
Two parameters of the spiral inductor were �xed, namely its width and
its inductance, while the other parameters were determined using ASITIC1
with the goal of maximizing the inductor's Q-factor [22].
The size of the layout of the complete VCO is mainly determined by the
size of the spiral inductors. Their dimension is limited by the speci�cations
of the size of the complete VCO (1mm � 1mm). The second parameter that
has to be �xed, is the inductance of the inductor. In order to achieve an LC
tank with a high Q-factor, the highest inductance should be chosen. How-
ever, the greater the inductance, the smaller the capacitance (considering a
�xed frequency); and the smaller the capacitance is chosen, the smaller the
tuning range will be. In this case, one can see the trade-o� between tuning
range and phase noise. After having consulted the literature, the following
parameters were �xed:
Inductance L: 8nH
Width of spiral inductor: 300�m
We consequently want to determine the physical and electrical parame-
ters of the 4 nH-spiral inductor with a side length of 300 �m and a maximal
Q-factor. The Q-factor can be greatly increased using a stacked topology,
due to the mutual inductance and due to the greater circuit width which
result in smaller resistive losses. Another big advantage of stacked spiral
inductors is the fact that both ports can be at the outside of the spiral
inductor. If an even number of layers is used, no crossings of the windings
from the exit layer are necessary.
After many sweeps with ASITIC over all possible widths, spacings and
number of turns, the spiral inductor with the following characteristics was
1ASITIC is freeware and can be downloaded from
http://www.eecs.berkeley.edu/ niknejad/.
17
Chapter 4 Design and Simulation of an LC VCO
determined to be the one bearing the highest Q-factor:
Width of spiral inductor: 300�m
Width of conductor: 46�m
Spacing between conductors: 1�m
Turns per layer: 2.25
Metal Layers used: M3 and M2
Inductance @ 1.05GHz: 4.06nH
Q-factor @ 1.05GHz: 6.2
The two layers of the spiral inductor are illustrated in Figure 4.1.
Figure 4.1: Metal Layer 3 and 2 of the stacked spiral inductor
The parameters of the spiral inductor's equivalent circuit were extracted
using ASITIC. They are valid in the vicinity of the operating frequency of
1.05 GHz. The schematic of the equivalent circuit is illustrated in Figure 4.2
[23], [31]. Its elements have the following values:
L = 4.06 nH R = 3.74
Cs1 = 728 fF Rs1 = 1.62
Cs2 = 992 fF Rs2 = 0.175
Q = 6.2
The values of these elements have no direct physical meaning, they are
�tting parameters obtained by modelling the behavior of the spiral inductor
at the given frequency using the physical parameters of the technology. The
Hspice de�nition of this circuit is given in section A.1.
18
Chapter 4 Design and Simulation of an LC VCO
)����� ��
� ! *
%��
*��
%�
*�
Figure 4.2: Equivalent circuit of the spiral inductor
4.2.2 The Cross Coupled Pairs
The nMOS and pMOS cross coupled pairs are responsible for providing the
negative resistance for keeping up the oscillation of the VCO. The resistive
losses of the LC tank can be modelled using only one resistor parallel to the
inductor and the capacitor as shown in Figure 4.3.
*�
!
%!
%
*+
Figure 4.3: The parasitic series resistance Rs can be transformed to a parallel
resistance Rp.
The value of this parallel resistor can be determined by simulation using
Hspice or by hand calculations using equation (4.2) [28].
Rp � Q2Rs (4.1)
� L2!2
Rs(4.2)
� (4:06nH)2 � (2� � 1:05 GHz)2
3:74� 192
19
Chapter 4 Design and Simulation of an LC VCO
The result acquired with equation (4.2) was con�rmed using an Hspice
ac-simulation (section A.8). As the Q-factor of the LC tank is mainly de-
termined by the Q-factor of the inductor, the capacitor can be assumed
as being ideal. In resonance, the impedance of the inductor and of the ca-
pacitor cancel themselves out, therefore, the voltage over the LC resonator
is directly dependent on Rp and can be found in the simulation shown in
Figure 4.4. The parallel resistance determined using Hspice is 193 . This
corresponds to the value derived from equation (4.2).
0
20
40
60
80
100
120
140
160
180
200
1g 1.5g
Rp=1.93e+02Frequency=1.05e+09
Frequency
Res
ista
nce
Figure 4.4: In case of resonance (1.05 Ghz), the peak of the amplitude cor-
responds to the equivalent parallel resistance Rp of the LC tank.
The equivalent circuit of the VCO is derived as shown in Figure 4.5.
From this equivalent circuit, the condition for oscillation, stated in equation
(4.3), can be deduced [28].
(gm1 + gm2) �Rp � 1 (4.3)
In order to improve the 1=f3-corner of phase noise, the conductances of
the nMOS and the pMOS transistors are chosen to be equal: gm;n = gm;p,
gm1 = gm3 [13]. The critical transconductance of the VCO can be determined
using equation (4.4).
gm;crit =1
2Rp(4.4)
gm;crit =1
2 � 193 = 2:6 mS
The critical transconductance, gm;crit, o�ers just enough gain in order
to keep up an oscillation. It is critical to use a transconductance with this
20
Chapter 4 Design and Simulation of an LC VCO
$��
!� !�
% %
&�� �
*+ *+
!�
%
*+
,��
,�
� ��-�.% � ��-�.%
��*���� ���#���������
,�
*+
,��
���+������
,��/,�
*+
� � ��� ��� ���
Figure 4.5: (a) The schematic of the VCO, (b) schematic of the half circuit,
(c) half circuit at resonance frequency, (d) simpli�ed schematic of the half
circuit at resonance frequency.
value, as only small drifts in any parameters may lower the desired transcon-
ductance. However, if the transconductance is chosen too big, excessive noise
will be injected. An appropriate value seems to be gm = 3 � gm;crit [32].
gm;i = 3 � gm;crit = 7:8 mS, for i = 1::4
The next step is to determine the VCO's tail current, as the drain cur-
rent, together with the transconductance, determine the physical dimensions
of the transistors. In the current-limited regime [13], the tank voltage am-
plitude is dependent on the tail-current, but not on the transconductance of
the transistors. The dependency is shown in equation (4.5).
Vtank � 2Rp � Ibias (4.5)
This can easily be understood by assuming that the tail current Ibias is
switched from one side to the other, as illustrated in Figure 4.6. In that case,
the amplitude of the LC tank voltage corresponds exactly to equation (4.5).
The VCO's output voltage speci�cations are very unrestricted. However,
in order to optimize the VCO for lowest phase noise, the output voltage has
to be maximized. The limiting factor is the saturation voltage of the current
21
Chapter 4 Design and Simulation of an LC VCO
$��
&�� �
*+ *+
&�&��
�
�
�
&�� �
&��
&�
Figure 4.6: The current Ibias gets switched from one side to the other.
source's transistor. A tank voltage of 2.5 V is therefore assumed, resulting in
Vpp = 5V. By applying equation (4.5) the bias current can be determined:
Itail =Vtank2Rp
=2:5V
386� 6:5mA
Now that the transconductances and the currents of the transistors are
set, their widths and lengths can be computed according to equations (4.6).
The operating-point drain current is assumed to be Itail2
and minimum gate-
length transistors are used, Ln = Lp = 0:35�m.
Wn =g2m;n � Ln
k0n � ItailWp =
g2m;p � Ln
k0p � Itail(4.6)
Withkn = 110:9 � 10�6 1
V
kp = 42:7 � 10�6 1V
the widths of the transistors are �xed at:
Wn = 29.30 �m Ln = 0.35 �m
Wp = 73.25 �m Lp = 0.35 �m
The circuit shown in Figure 4.7 was then simulated using Hspice (section
A.4) and the computed values could be veri�ed, as shown in the following
table. The capacitance was set as to attain an oscillation of 1.05 GHz.
22
Chapter 4 Design and Simulation of an LC VCO
M1 (n): gm1: 7.6 mS iD1: 3.25 mA
M2 (n): gm2: 7.6 mS iD2: 3.25 mA
M3 (p): gm3: 7.7 mS iD3: 3.25 mA
M4 (p): gm4: 7.7 mS iD4: 3.25 mA
$���0�$
%��� %���
&�� ��0�123�.
! *%��
*��
%�
*�
!*%�
*�
%��
*��
�+���2�+ �+���2�+
'�
'('
'
$���/ $���#
�042��!�0�523��
�0623��!�0���523��
�0623��!�0���523��
�042��!�0�523��
Figure 4.7: The circuit was simulated using Hspice, evidently verifying the
calculated values.
The output voltage and frequency are veri�ed and plotted in Figure 4.8.
The desired values were con�rmed.
4.2.3 The Varactors
The �rst step in designing the varactors lies in choosing their type. Due to
its ease of implementation and simulation, the gate channel capacitance of
a pMOS transistor is used. The ratio of maximal to minimal capacitance is
higher for MOS varactors than for junction-diodes, but the capacitance to
voltage-characteristic is steeper. This problem can be overcome by directly
coupling the varactor to the oscillator. The steep characteristic of the
varactor capacitance is averaged out over the oscillator swing and the VCO
tuning characteristic can be linearized [33].
In order to determine the necessary size of the varactor, all the capac-
itances of the VCO have to be modelled. The VCO's load will be a gate
23
Chapter 4 Design and Simulation of an LC VCO
-2.5
-2
-1.5
-1
-500m
0
500m
1
1.5
2
2.5
0 2n 4n 6n 8n 10n 12n 14n 16n 18n 20n 22n 24n 26n 28n 30n 32n 34n 36n 38n 40n
Time=2.56e+00Voltage=2.91e-08
Out
put V
olta
ge, [
V]
Time, [ns]
050m
100m
150m
200m
250m
300m
350m
400m
450m
500m
550m
600m
650m
700m
750m
800m
850m
900m
950m
1g 2g
Frequency=1.05e+09
Frequency
Figure 4.8: The output voltage is as expected about 2.5 V while the oscilla-
tion frequency lies at 1.05 GHz.
of a mixer stage or a source follower; this was simulated as Cload = 40 fF.
The other transistors were modelled as shown in Figure 4.9 [30]. Figure 4.10
depicts the model of the varactor that was used for deriving the VCO's
equivalent circuit, shown in Figure 4.11 [17], [18].
The tank capacitance, Ctank, is given in equation (4.7). The resistances
Rs2 and Rv were neglected for simpli�cation.
Ctank =1
2(4Cgd;n + 4Cgd;p + Cdb;p + Cdb;n +
+ Cgs;n + Cgs;p + Cs2 + Cv + Cload) (4.7)
The capacitance needed in order to reach a midfrequency of 1.05 GHz was
24
Chapter 4 Design and Simulation of an LC VCO
7
8 )
9
%,� %,�
%��
Figure 4.9: The capacitances of a MOSFET.
%:
*:7
8 )9
Figure 4.10: The varactor's equivalent circuit.
computed using equation (3.1).
Ctank =1
(2�fres)2L(4.8)
=1
(2� � 1:05GHz)2 � 2 � 4:06nHCtank � 2:83pF
All the capacitances, obtained with an operating-point simulation in
Hspice, were used to compute the desired varactor capacitance, Cvar, in
equation (4.9).
Cvar = 2Ctank � (4Cgd;n + 4Cgd;p + Cdb;p + Cdb;n +
+Cgs;n + Cgs;p + Cs2 + Cload) (4.9)
Cvar � 2 � 2:83pF � 1
2[4 � 16:26fF + 4 � 39:05fF + (94:56fF � 39:05fF) +
+ (38:79fF � 16:25fF) + 30:45fF + 80:56fF + 40fF + 992fF]
� 4:94pF
According to equation (4.9), varactors are needed with a mean capac-
itance of 4.94 pF each. The tuning voltage is �xed to Vtune = 0:::3V, the
25
Chapter 4 Design and Simulation of an LC VCO
! *%��
*��
%�
*�
!*%�
*�
%��
*��
%: %:*:*:
%,�-�
%,�-�
%��-� %,�-�
%,�-�
%��-�
%,�-+
%,�-+
%��-+ %,�-+
%,�-+
%��-+
%�� � %�� �
� �
%: %:*:*:
%�� � %�� �
(%,�-+ (%,�-+
#,�-+ #,�-+
#,�-� #,�-�
%��-�/�%,�-�
%��-�/�%,�-�
%��-+/�%,�-+
%��-+/�%,�-+
(%,�-� (%,�-�
! !*� *�
%� %�*�*�
���
+#';)������#���+����+ ��
�#';)������#���+����+ ��
+#';): � �����
�+�� �����������
! *%��
*��
%�
*�
%: %:*:*:
%�� � %�� �
(%,�-+ (%,�-+
#,�-+ #,�-+
#,�-� #,�-�
%��-�/�%,�-�
%��-�/�%,�-�
%��-+/�%,�-+
%��-+/�%,�-+
(%,�-� (%,�-�
���
!*%�
*�
%��
*��
Figure 4.11: (a) The equivalent circuit of the VCO, (b) AC equivalent circuit,
(c) simpli�ed AC equivalent circuit.
potential of the output node, where the varactor is attached to, lies at a mean
potential of 1.5 V. Subsequently, the voltage over the varactor lies between
-1.5 V and 1.5 V. A �rst estimate for the size of the varactor was attained
using Hspice's CAPOP model [30] and by measuring the output frequency
of the circuit as shown in Figure 4.12. The according Hspice circuit is listed
in section A.5.
For maximizing the Q-factor of the varactor, minimal length transistors
26
Chapter 4 Design and Simulation of an LC VCO
$�
%��<��
'�
&�
!
Figure 4.12: This schematic was simulated to determine the correct size of
the MOSCAP varactor, M1, and its Q-factor.
ought to be chosen [8]. The graphs shown in Figures 4.13 and 4.14 contain
the results of the simulation with a MOSCAP of length L = 0:7�m and
width W = 1400�m.
2p
2.2p
2.4p
2.6p
2.8p
3p
3.2p
3.4p
3.6p
3.8p
4p
4.2p
4.4p
4.6p
4.8p
5p
5.2p
-1.6 -1.4 -1.2 -1 -800m -600m -400m -200m 0 200m 400m 600m 800m 1000m 1.2 1.4 1.6Vgs
Cg,
tot
Figure 4.13: Gate capacitance of the varactor versus its gate to source/drain
voltage.
The varactor's Q-factor can now be computed, using Rp, the equiva-
lent parallel resistance of the LCVaractor resonator, obtained from the graph
shown in Figure 4.14. This graph was obtained by simulating the circuit
stated in section A.9, the moscap subcircuit is listed in section A.2. Rp
varies with the resonance frequency, therefore, this calculation is not very
precise. A worst-case scenario is assumed, using Rp = Rp;min [28].
27
Chapter 4 Design and Simulation of an LC VCO
0
1k
2k
3k
4k
5k
6k
7k
8k
9k
10k
11k
12k
13k
500x 1g 1.5g 2g
Rp=1.73e+03Frequency=9.76e+08
Rp=9.33e+03Frequency=1.32e+09
Rp=1.50e+03Frequency=1.27e+09
Frequency
Rp,
[Ohm
]
Figure 4.14: The resonator gets tunable using the gate capacitance of a
pMOS varactor.
Rp � 1
!2C2Rs(4.10)
� Q2varactorRs (4.11)
From equations (4.10) and (4.11) the varactor's series resistance, Rs, can
be computed.
Rs � 1
!2C2Rp(4.12)
� 1
(2� � 1:05 GHz)2 � (4:9 pF)2 � 1:5 kRs � 0:64
Qvaractor � 1
!CRs(4.13)
� 1
2� � 1:05 GHz � 0:64 � 4:9 pFQvaractor � 48:5
It is important to note, that these calculations are not very precise,
as the layout of the varactor is not incorporated into the simulation. The
28
Chapter 4 Design and Simulation of an LC VCO
varactor's series resistance is, therefore, higher and the corresponding
Q-factor lower.
The tuning range shown in Figure 4.14 is not realistic, because the capac-
itance of the varactor does not stay constant during a cycle of the oscillator,
as the varactor is directly attached to the oscillating output of the VCO. This
\direct coupling" is used to linearize the tuning voltage to output frequency
characteristic and it is illustrated in Figure 4.15.
$��
!� !�
% %
'
'�
'(
'
$����;��# ;��/
&�� �
Figure 4.15: Direct coupling: The voltage across the varactor does not stay
constant, as the output is oscillating.
It was found, that the tuning range can be improved by increasing the
gate length of the varactor from 0.7 �m to 1.05 �m, and by decreasing
the width accordingly. Figure 4.16 shows the di�erent capacitance versus
voltage curves, with the gate lengths and widths as parameters. Increasing
the gate length lowers the Q-factor of the varactor. Therefore, this is an
additional trade-o� between phase noise (high Q-factor of the varactor) and
VCO tuning range.
The size of the varactor was set to:
Wvaractor= 1000 �m Lvaractor = 1.05 �m
The frequency range of the VCO is from 955 MHz to 1110 MHz. Figure
4.17 shows the tuning range of the (ideal) VCO.
29
Chapter 4 Design and Simulation of an LC VCO
1.2p
1.4p
1.6p
1.8p
2p
2.2p
2.4p
2.6p
2.8p
3p
3.2p
3.4p
3.6p
3.8p
4p
4.2p
4.4p
4.6p
4.8p
5p
5.2p
5.4p
5.6p
-1.6 -1.4 -1.2 -1 -800m -400m 0 400m 800m 1 1.2 1.4 1.6Vgs, [V]
Cto
t, [p
F]
Wvaractor = 2800 / a
L varactor = 0.35 x a
a=1
a=2
a=3
a=4
a=5
Figure 4.16: Sweep over di�erent gate lengths. By increasing the gate length
from 0.7 �m to 1.05 �m, the tuning range could be increased.
0
100m
200m
300m
400m
500m
600m
700m
800m
900m
1000m
850x 900x 950x 1g 1.05g 1.1g 1.15g 1.2g 1.25g 1.3g 1.35g 1.4g 1.45g 1.5g 1.55g 1.6g
Frequency=9.55e+08
Frequency=1.11e+09
Frequency, [GHz]
Figure 4.17: The VCO is now tunable from 955 MHz to 1110 MHz.
4.2.4 The Current Source
The last part of the VCO that needs to be designed is the current source. The
two important characteristics of a current source are the output resistance
and the saturation voltage. Ideally, an in�nite output resistance and 0 V
30
Chapter 4 Design and Simulation of an LC VCO
saturation voltage are desired. Having a high output resistance results in low
harmonic distortion, a low saturation voltage enables a high voltage swing,
resulting in a trade-o�. The smallest saturation voltage can be achieved
by using a simple current mirror as a current source. The two equations
describing saturation voltage and output resistance are given in equations
(4.14) and (4.15) [34].
r�1out =
dIDdVDS
(4.14)
= k0W
L(VGS � Vt � VDS)
= k0W
L(VDSat � VDS)
VDSat =
r2
L
Wk0ID (4.15)
The output voltage amplitude is 2.5 V, leaving not enough headroom
even for the simple current mirror. In order to lower the output voltage, the
bias current was lowered to 5 mA and the transistor sizes were adjusted.
Wn = 60 �m Ln = 0.35 �m VDSat = 2323
Wp = 162 �m Lp = 0.35 �m VDSat = 2211
Ibias = 5 mA Vpp = 4.4 V
Simulations with an ideal current source and a resistor in parallel were
then made, and following speci�cations were determined to be most �tting:
Rout � 3 k
VDSat � 500 mV
The gate length of the current mirror transistor was then set to 0.7 �m,
double the size of the other transistors. Consequently, the gate width could
be computed using equation (4.15).
Wcurrent-mirror =2LIDk0VDSat
Wcurrent-mirror � 130�m
The resulting output resistance is 3.6 k.
31
Chapter 4 Design and Simulation of an LC VCO
Wcurrent-mirror = 130 �m Lcurrent-mirror = 0.7 �m
Rout = 3.6 k VDSat = 460 mV
The bias current is set to Ibias = 5mA, a current that can be easily
adjusted by an o�-chip current source. As a result, both transistors of the
current mirror are set to be of equal size.
4.3 Phase Noise of the LC VCO
As there is no possibility to simulate phase noise properly using Hspice,
hand calculations had to be relied on. The equations that were used, are
described in section 2.2. The equation used to compute the phase noise in
the 1=f2-region was already denoted in (2.6).
L(foff ) � 1
16�2f2off� 1
q2max
�Xn
i2n�f
!
� 1
16�2f2off� Ltank
2!04
V 2sw
�Xn
i2n�f
!(4.16)
� 2�2 � f04
f2off� Ltank
2
V 2sw
�Xn
i2n�f
!(4.17)
L(100 kHz) � 2�2 � (1:05 GHz)4
(100 kHz)2� (8:12 nH)2
(2:2 V)2�Xn
i2n�f
!(4.18)
� 32:685 � 109 1
A2�Xn
i2n�f
!(4.19)
Pn
�i2n
�f
�is the sum of the current noise densities of all independent
noise sources in the equivalent circuit. The noise sources that were considered
are enclosed in the schematic in Figure 4.18.
Transistor drain noise: A simple model is used for the transistor channel
thermal di�erential current noise [13]:
i2M;d
�f=
i2Mp;d
�f+i2Mn;d
�f
= 2kT (gd0;n + gd0;p) (4.20)
32
Chapter 4 Design and Simulation of an LC VCO
&�� �
%: %:*:*:
! !*� *�
*)*)
�'+-�
���'+-�
��
�'+-,
���'+-,
��
�'�-�
���'�-�
���'�-,
���'�-,
��
��:%:
:%:
��
��:*+
:*+
��
:*�
��:*�
��
'�
'+
'�
'+
%)%)
Figure 4.18: Schematic of the VCO with all the noise sources included.
where for short-channel transistors = 2:5, and
gd0;n =2Id;n
LnEsat;n
(4.21)
gd0;p =2Id;p
LpEsat;p: (4.22)
The total drain current noise density is computed in equation (4.23).
i2M;d
�f= 4kT (
Id;nLnEsat;n
+Id;p
LpEsat;p) (4.23)
� 1:77 � 10�22A2s
Transistor gate noise: All the gate noise sources are in parallel to the
drain noise sources; they therefore add up in the same way as the
drain current noise sources do [13]. For short channel transistors, the
33
Chapter 4 Design and Simulation of an LC VCO
total gate current noise density is given in equation (4.24).
i2M;g
�f=
i2Mp;g
�f+i2Mg;d
�f(4.24)
=1
2
4kTÆ!2C2
gs;nESatLn
5Ibias+4kTÆ!2C2
gs;pESatLp
5Ibias
!
=2kTÆ!2
5Ibias
�C2gs;nLnESat;n + C2
gs;pLpESat;p
�For short channel devices Æ is assumed to be about 4. The total gate
current noise density is therefore:
i2M;g
�f� 3:21 � 10�24A2s
Inductor noise: Two noise sources of the inductor are considered: the
noise of the ohmic losses in the windings and the noise of the losses in
the substrate [18].
i2L�f
= 2kTgL (4.25)
where
gL =Rs
(!L)2+Cs2!
Qs2
(4.26)
� Rs
(L!)2+ (!Cs2)
2Rs2
The total inductor noise density is computed in equation (4.27).
i2L�f
� 2kT
�Rs
(L!)2+ (!Cs2)
2Rs2
�(4.27)
� 4:32 � 10�23A2s
Varactor noise: The varactor noise can be modelled using equation (4.28)
[18].
i2C�f
=8kT
Rv;p
(4.28)
� 8kTRv(!Cv)2
34
Chapter 4 Design and Simulation of an LC VCO
Rv;p is the equivalent parallel resistance of the varactor. Rv;p is actually
frequency-dependent, but for simplicity, worst-case is assumed: Rv;p =
Rv;p;max. The total varactor noise density is:
i2C�f
� 2:46 � 10�23A2s
Summing up all the noise densities of the di�erent noise sources leads
to:
Xn
i2n�f
!=
i2M;d
�f+i2M;g
�f+
i2L�f
+i2C�f
� 2:48 � 10�22A2s
The total amount of phase noise at 100 kHz o�set from the carrier fre-
quency of 1.05 GHz was then computed as shown in equation (4.29).
L(foff ) � 1
16�2f2off� 1
q2max
�Xn
i2n�f
!(4.29)
L(100 kHz) � 32:685 � 109 1
A2� 2:48 � 10�22A2s
� �111 dBc
Hz
Several parts of the VCO contribute di�erently to the total phase noise
of the VCO:
Transistor drain noise: 71.4 %
Transistor gate noise: 1.3 %
Inductor noise: 17.4 %
Varactor noise: 9.9 %
The biggest contribution to phase noise comes from transistor drain cur-
rent, which is linearly dependent on the transconductance of the transistors.
By increasing the Q-factor of the LC tank, this transconductance can be
lowered, resulting in better phase noise performance. The amount of phase
noise lies well below the speci�ed phase noise margin.
35
Chapter 4 Design and Simulation of an LC VCO
4.4 Simulation of the Complete LC VCO
Having determined all the elements of the VCO, the complete LC VCO,- as
shown in Figure 4.19 and listed in section A.6, can now be simulated. No
parasitic capacitances or resistances were added, except for the ones included
in the equivalent circuit of the spiral inductor.
$��0$
&�� �03�.
! *
%��
*��
%�
*�
!*%�
*�
%��
*��
�+���2�+ �+���2�+
'�
'('
'
$���/ $���#
�015��!0523��
�0�1��!0523��
�0�1��!0523��
�015��!0523��
'%'%�
$����
�0�555��!�0��253��
�0�5��!0526��
�0�5��!0526��
Figure 4.19: Schematic of the complete VCO including all the transistor
dimensions.
The graphs in Figure 4.20 show the output voltage in the time-
and in the frequency-domain. The tuning voltage to output frequency
characteristic is depicted in Figure 4.21. As the characteristic of the tuning
voltage to capacitance of the varactor is not monotonous (see Figure 4.13),
the tuning-voltage to frequency characteristic is also not monotonous. The
useful range for the tuning voltage has to be limited from 0.5 V to 1.7 V.
This can, for example, be done by using a �xed voltage divider.
All the speci�cations were ful�lled and as a result, the layout of the LC
VCO could be commenced. The simulation results are summarized in the
following table:
Speci�cations Simulation
Supply Current: max. 10mA 5mA
Tuning Range: 1:05GHz � 5% 1:05GHz + 6%;�9%Control voltage: 0V � 3V 0:5V � 1:7V
Output signal > 2Vpp 4:4Vpp
Phase noise: L(100kHz) < �100 dBc=Hz � �111 dBc=Hz
36
Chapter 4 Design and Simulation of an LC VCO
-2.5
-2
-1.5
-1
-500m
0
500m
1
1.5
2
2.5
-2n 0 2n 6n 10n 14n 18n 22n 26n 30n 34n 38n 42n 46n 50n 54n 58n 62n
Voltage=2.28e+00Time=4.08e-08
Voltage=-2.28e+00Time=4.13e-08
Time, [ns]
Out
putv
olta
ge, [
V]
0
100m
200m
300m
400m
500m
600m
700m
800m
900m
1000m
1.1
800x 840x 880x 920x 960x 1g 1.04g 1.08g 1.12g 1.16g 1.2g 1.24g 1.28g 1.32g
Frequency=9.52e+08
Frequency=1.10e+09
Frequency, [GHz]
Figure 4.20: Simulation result of the complete VCO, in the time- and in the
frequency-domain.
37
Chapter 4 Design and Simulation of an LC VCO
435
465
445
�5�5
�55
�535
�565
�545
��55
5$ 523$ �25$ �23$ 25$ 23$ 25$
;��+�
�����
����
�-�='
��>
$����-�=$>
�26$-����5'��
523$-�433'��
Figure 4.21: The frequency versus tuning voltage characteristic is fairly linear
from 0.5 V to 1.7 V.
38
Chapter 5
Layout of the LC VCO
5.1 Layout Issues
The layout of an analog RF circuit is very delicate, as it greatly in uences
its performance. There are several issues that have to be taken into account;
only a few important ones will be mentioned here:
� The most important issue in the layout of a di�erential circuit is \sym-
metry": both half-circuits have to be as similar as possible. All de-
viations from symmetry deteriorate the output signal; additionally,
symmetry inhibits the e�ect of common-mode noise and even-order
nonlinearity. In order to improve symmetry large transistors may fur-
ther be split up to counteract gradient e�ects: transistors are decom-
posed, placed on both sides of the symmetry axis and connected (e.g.
common-centroid layout, cross coupling) [28].
� Another important issue are body-e�ects: many substrate contacts
have to be inserted to ensure that all elements of the circuit are at the
same potential [28], [34].
� It is essential to minimize parasitic elements; especially connections
between critical parts (for example paths carrying RF signals) should
be kept as short as possible. The resistance of a connection can also
be lowered by increasing its width, however, this results in an increase
of parasitic capacitance. As conductor-crossings carrying RF signals
cause coupling and may deteriorate the signal, they should be kept to
a minimum.
39
Chapter 5 Layout of the LC VCO
� By interleaving the transistors, their gate resistances and the
source/drain junction areas can be reduced [28], [35], consequently,
the transistor's performance ameliorates to a great extent.
� Transistors should all have the same orientation, as many steps in
lithography and wafer processing behave di�erently along di�erent
axes. This may otherwise cause bad matching [35].
Greatest e�ort was taken with these basic layout issues while working
on the layout of the LC VCO. The following sections brie y discuss the
layout of the di�erent parts of the LC VCO. The seperate layers of the
technology used are shown in Figure B.1. All �gures containing illustrations
of the layouts are collected in appendix B.
5.2 The Spiral Inductors
The layout of the spiral inductors was determined by ASITIC. The two layers
were connected using as many vias as allowed regarding the design rules. The
two inductors were connected via metal layer 3; the distance between the
two inductors was set later, as the space had to be large enough to �t the
cross coupled pairs. The layout of the two spiral inductors is shown in Figure
B.2.
5.3 The Cross Coupled Pairs
The layout of the nMOS and pMOS cross coupled pairs was designed next.
The nMOS and pMOS transistors used for the cross coupled pairs have to
be of following dimensions1:
Wn = 60 �m Ln = 0.4 �m
Wp = 162 �m Lp = 0.4 �m
The cross coupled pairs have common sources and one gate is connected
to the drain of the other transistor. Instead of connecting the sources via
1The design rules of the 0.35 �m ROHM process was only received after having already
determined all the elements and their dimensions of the LC VCO, however, the minimal
gate length in this 0.35 �m process is 0.4 �m, not 0.35 �m as expected. The resimulations
of the complete circuit demonstrated that no signi�cant changes occur by increasing the
gate lengths of all transistors.
40
Chapter 5 Layout of the LC VCO
metal layers, the transistors can be interweaved; the drains of each transistor
are enclosed by two common sources. The sources are connected via metal
layer 2 from both sides, while the gates of one transistor are connected with
the drains of the other transistor via metal layer 1. The substrate and n-well
is connected on two opposing sides of the cross coupled pair to ground and
Vdd respectively. The nMOS transistors are split up into two \�ngers", and
the pMOS is split into four. The dimensions of the complete cross coupled
pairs are as follows:
nMOS cc pair pMOS cc pair
Width: 20.4 �m 25.6 �m
Length: 12.9 �m 27.9 �m
The layout of the 2 cross coupled pairs can be seen in Figure B.3.
5.4 The Varactors
Many scienti�c publications have recently been devoted to the layout of
varactors [8], [27]. These describe, that two issues are very important in
designing a varactor: its series resistance should be minimized, and the
symmetry.
In order to minimize the series resistance, the transistors were inter-
leaved. The two varactors were split up into four and then interlinked, as
illustrated in Figure 5.1. This strategy decreases linear gradient e�ects and
improves the symmetry. The n-well is on the same potential as the drain
and the source are; the n-well is connected to drain and source on all four
sides of the varactor.
The varactor's layout is depicted in Figure B.4. The outer side of the
varactor serves as the di�erential outputs, the tuning voltage will be attached
to the bottom parts of the varactors. The dimensions of each varactor are
as follows:
Width: 36 �m
Length: 67 �m
41
Chapter 5 Layout of the LC VCO
$���/ $���#
$����
$���/ $���#
$���� $����
Figure 5.1: The varactors were split up into even parts and cross-connected.
5.5 The Current Source
The current source is not very crucial in design, but again, symmetry is
very important. Therefore, the current source was divided in order to make
it symmetric, as shown in Figure 5.2.
�0�5��!�0�526��
�0�5��!�0�526��
�� ��
�
�0�5��!�0�526��
�0�13��!�0�526��
�0�13��!�0�526��
� �
Figure 5.2: The current mirror was split up and made symmetric.
As all the current (i.e. 5 mA) ows through the current source, the
conductor has to be wide enough to minimize resistive losses and voltage
drop. The substrate's potential around all three transistors is de�ned
from three sides and the ground-contact is held as short and as wide as
possible to ensure a properly de�ned potential. The layout of the complete
current source is depicted in Figure B.5. The disadvantage of this layout is
the crossing of the output of the current source with the varactor-connection.
The dimensions of the complete current source are as follows:
42
Chapter 5 Layout of the LC VCO
Width: 50 �m
Length: 17 �m
5.6 The Complete Layout
After all parts of the LC VCO have been designed, the next step is to connect
them properly. The gap between the two spiral inductors was set big enough
to �t the cross coupled pairs in-between. Then the current source was placed
underneath the nMOS cross coupled pair and the varactors were placed on
either side and interconnected. The complete layout of the LC VCO can be
seen in Figures B.6 and B.7. The dimensions of the complete LC VCO are
as follows:
Width: 634 �m
Length: 381 �m
5.7 Extraction and Simulation of the Layout's
Equivalent Circuit
The �nished LC VCO's layout was now examined. First, the equivalent cir-
cuit containing all the parasitic capacitances was extracted. The parasitic
resistances could not be determined, as ROHM did not provide this infor-
mation. Therefore, the most important resistances were added by hand. The
resulting circuit description is stated in section A.7 The spiral inductor had
to be removed prior to extracting the equivalent circuit, as it would have
been treated as a short-circuit. The spiral inductor's equivalent circuit in-
cluding all the parasitcs was already extracted with ASITIC. The resulting
circuit-�le was then simulated in Hspice. As the midfrequency of the VCO
was too low, due to all the parasitic resistances, the size of the varactor was
adjusted and the circuit was again extracted and simulated. The following
results were obtained:
Due to the parasitic capacitances, the tuning range shrank slightly, which
can be seen in Figure 5.3. The e�ective tuning range of the LC VCO is now
between 962 MHz and 1110 MHz. The output voltage is similar to the one
before having included the parasitic elements, Vpp=4.4V, as shown in Figure
5.4. The tuning characteristic was plotted in Figure 5.5.
43
Chapter 5 Layout of the LC VCO
-50m0
50m
100m
150m
200m
250m
300m
350m
400m
450m
500m
550m
600m
650m
700m
750m
800m
850m
900m
950m
1
2g
Frequency=9.62e+08
Frequency=1.11e+09
1gFrequency, [GHz]
Figure 5.3: The VCO can be tuned from 962 MHz to 1110 MHz.
-2
-1.5
-1
-500m
0
500m
1
1.5
2
0 1n 2n 3n 4n 5n 6n 7n 8n 9n 10n 11n 12n 13n 14n 15n 16n 17n 18n 19n 20n
Voltage=2.20e+00Time=1.59e-08
Voltage=-2.20e+00Time=1.60e-08
Time, [ns]
Out
put V
olta
ge, [
V]
Figure 5.4: The LC VCO has an output voltage of Vpp=4.4 V.
44
Chapter 5 Layout of the LC VCO
435
465
445
�5�5
�55
�535
�565
�545
��55
5$ 523$ �25$ �23$ 25$ 23$ 25$
;��+�
�����
����
�-�='
��>
$����-�=$>
�26$-����5'��
523$-�41'��
Figure 5.5: The LC VCO's tuning characteristic is fairly linear for
Vtune=0.5V to Vtune=1.7V.
45
Chapter 6
Concluding Remarks
In this thesis, the design of a low phase noise LC VCO was presented. The
topology was determined, its elements were calculated and simulated and
�nally the layout was designed. In this approach, special care was taken to
minimize the phase noise.
The project is concluded with the simulation of the complete layout,
including all parasitic capacitances and the most important resistances. The
VCO will be fabricated, but as the time frame of this thesis does not allow
to wait for the chip, only simulation results can be presented.
6.1 Summary of the Simulation Results
The complete layout was simulated including all the parasitic capacitances
and the most important parasitic resistances. The phase noise calculation
was repeated with the new parameters, however, this did not change the
result. Due to the �xed parasitic capacitance from the layout, the tuning
range decreased, but the speci�cations were still attained. The results are
presented in the following table:
46
Chapter 6 Concluding Remarks
Speci�cations Simulation of the
complete layout
Supply Current: max. 10mA 5mA
Tuning Range: 1:05GHz � 5% 1:05GHz + 6%;�8%Control voltage: 0V � 3V 0:5V � 1:7V
Output signal > 2Vpp 4:4Vpp
Phase noise: L(100kHz) < �100 dBc=Hz � �111 dBc=Hz
These results show that low phase noise LC VCO's using this CMOS
process are feasible. The most important part of the VCO is its LC tank, as
this mainly determines the amount of phase noise and the power dissipation.
However, it has to be pointed out that these results are not very precise:
The process parameters are not very accurate and the simulation programs
(i.e. DRACULA and Hspice) cannot be fully relied on for RF circuit design.
6.2 Comparison with Recent Publications
The LC VCO designed and simulated in this thesis is being compared to
recently published designs in the following table:
Published in Frequency Tuning Power Phase noise
range consumption (600kHz)
LC VCOs
this thesis 1050 MHz 14% 15 mW -126 dBc/Hz
[16] 1910 MHz 26% 10 mW -121 dBc/Hz
[4] 1300 MHz 25% 12 mW -119 dBc/Hz
[18] 1800 MHz 10% 3.2 mW -118 dBc/Hz
[13] 1800 MHz - 6 mW -121 dBc/Hz
Ringoscillators
[10] 1500 MHz 48% 2.5 mW -88 dBc/Hz
[36] 900 MHz 50% 30 mW -117 dBc/Hz
All designs were published recently, either in the year 1999 or 2000. This
comparison shows that all three parameters, tuning range, phase noise
and power consumption, are related to one another. By increasing the
power dissipation, the phase noise performance is improved, however, by
improving the phase noise performance the VCO's tuning range becomes
47
Chapter 6 Concluding Remarks
limited. Ringoscillators achieve a higher tuning range, but for very low
phase noise performance, LC VCOs are more suitable.
Keeping this thesis' goal in mind, to design a minimal phase noise RF
VCO, the design was successful: The phase noise is minimal, but at the same
time, the tuning range is lower and the power consumption is higher than in
other designs. The improved low phase noise performance results from the
high Q-factor of the LC tank, and the relatively high power consumption.
The tuning range could be enhanced by decreasing the tank inductance and
increasing the varactor size, however, this excellent phase noise performance
would not be attained any longer.
6.3 Further Research
Many interesting topics concerning the LC VCO have not yet been fully
investigated:
� The e�ects of the current source on the LC VCO could be further ex-
amined, in order to determine the ideal saturation voltage and output
resistance so as to maximize the VCO's performance.
� The layout of the varactors seems to be very important. Further re-
search can be made to minimize the varactor's series resistance. In
addition, various types of varactors should be considered to optimize
future low phase noise LC VCOs.
� The mutual in uence of the two spiral inductors has not yet been in-
vestigated, this might be an important parameter to further maximize
their Q-factor.
� Shielding techniques for the transistors and the inductors could be ex-
plored, in order to minimize the inductor's eddy losses and to minimize
the potentially disturbing �eld in-between the two spiral indutors.
48
Appendix A
Hspice Simulation Files
A.1 Subcircuit: Spiral Inductor
.subckt spind 3 1 5
* two inputs of inductance and substrate connection
************* Circuit Data ***************
R11 (3 2) R1
Rss1 (6 5) Rs1
Rss2 (4 5) Rs2
L11 (2 1) L1
Css1 (3 6) Cs1
Css2 (1 4) Cs2
********** Parameterdefinitions **********
*Pi Model at f=1.05 GHz: Q = 6.180,5.875,6.605
*L = 4.06 nH R = 3.74
*Cs1= 728 fF Rs1= 1.62
*Cs2= 992 fF Rs2= 0.175 f_res = 2.92GHz
.param Cs1 = 728f
.param Cs2 = 992f
.param Rs1 = 1.62
.param Rs2 = 0.175
49
Chapter A Hspice Simulation Files
.param R1 = 3.74
.param L1 = 4.06n
.ends
A.2 Subcircuit: MOSCAP Varactor
.subckt moscap 1 2 3
************* Circuit Data ***************
M1 (3 1 3 3) p (l=length w=width)
M2 (3 2 3 3) p (l=length w=width)
.param length = '1.05u'
.param width = '1000u'
.ends
A.3 Subcircuit: MOSCAP Varactor Extracted
from the Layout
.subckt moscap 1 2 3
********** Circuit Data *************
****MOSCAP 900um
*M1 (3 1 3 3) p (l=1.05u w=900u) AD=463.50P
*+ PD=960.90U AS=463.50P PS=960.90U
*M2 (3 2 3 3) p (l=1.05 w=900u) AD=463.50P
*+ PD=960.90U AS=463.50P PS=960.90U
***moscap 855um
*M1 (3 1 3 3) p (l=1.05u w=805u)
*+ AD=440.33P PD=914.40U AS=440.33P PS=914.40U
*M2 (3 2 3 3) p (l=1.05u w=805u)
*+ AD=440.33P PD=914.40U AS=440.33P PS=914.40U
***moscap 804um
50
Chapter A Hspice Simulation Files
*M1 (3 1 3 3) p (l=1.05u w=805u)
*+ AD=414.06P PD=861.70U AS=414.06P PS=861.70U
*M2 (3 2 3 3) p (l=1.05u w=805u)
*+ AD=414.06P PD=861.70U AS=414.06P PS=861.70U
***moscap 804um including parasitic resistances and
***moscaps split up
M1 (3 4 3 3) p (l=1.05u w=402.5u)
M2 (3 6 3 3) p (l=1.05u w=402.5u)
M3 (3 11 3 3) p (l=1.05u w=402.5u)
M4 (3 9 3 3) p (l=1.05u w=402.5u)
R1a (4 5) '637m*x'
R1b (9 8) '637m*x'
R2a (5 1) '197m*x'
R2b (8 2) '197m*x'
R3a (5 10) '419m*x'
R3b (8 7) '419m*x'
R4a (6 7) '825m*x'
R4b (10 11) '825m*x'
* switching the resistances on/off, on: x=1
.param x = 1
.ends
A.4 VCO with Ideal Capacitors, Ideal Current
Source and Non-Ideal Spiral Inductor
************* Circuit Data ***************
.inc spind.sp
51
Chapter A Hspice Simulation Files
Vdd (6 0) DC 3V
Ianr (3 0) PULSE (0A 1mA 0 0 0 0.5n 1)
M3 (3 2 6 6) P (L=lp W=wp)
M4 (2 3 6 6) P (L=lp W=wp)
XL1 (3 5 0) spind
XL2 (2 5 0) spind
*L1 (3 5) 4.06nH
*L2 (2 5) 4.06nH
C1 (3 4) Cres
C2 (2 4) Cres
R2 (4 0) 10G
M1 (3 2 1 0) N (L=ln W=wn)
M2 (2 3 1 0) N (L=ln W=wn)
R1 (1 0) 10g
I1 (1 0) DC tail
********** Parameterdefinitions **********
.param wp = 73.35u
.param lp = 0.35u
.param wn = 29.3u
.param ln = 0.35u
.param ctrl = 1.7V
.param Cres = 4.2p
.param tail = 6.5mA
**************** Commands ****************
.inc comp21n1.mdl
.op
.tran .001n 40.001n 0.1n
.four 1.1g v(3,2) v(2) v(3) v(7,3) v(7,2)
52
Chapter A Hspice Simulation Files
.print tran i(M1) i(M2) i(m3) i(m4)
.option POST
.end
A.5 VCO with Ideal Current Source, Varactors
and Spiral Inductors for Measuring Tunabil-
ity
************* Circuit Data ***************
.inc spind.sp
.inc newmoscap.sp
Vdd (6 0) DC 3V
Ianr (3 0) PULSE (0A 1mA 0 0 0 0.5n 1)
M3 (3 2 6 6) P (L=lp W=wp)
M4 (2 3 6 6) P (L=lp W=wp)
XL1 (3 5 0) spind
XL2 (2 5 0) spind
*L1 (3 5) 4.06nH
*L2 (2 5) 4.06nH
XC1 (3 2 7) moscap
V7 (7 0) DC ctrl
*C1 (3 4) Cres
*C2 (2 4) Cres
*R2 (4 0) 10G
M1 (3 2 1 0) N (L=ln W=wn)
M2 (2 3 1 0) N (L=ln W=wn)
R1 (1 0) 10g
53
Chapter A Hspice Simulation Files
I1 (1 0) DC tail
Cload1 (3 0) 40fF
Cload2 (2 0) 40fF
********** Parameterdefinitions **********
.param wp = 73.25u
.param lp = 0.35u
.param wn = 29.3u
.param ln = 0.35u
.param ctrl = 1.7V
.param Cres = 4.12p
.param tail = 6.5mA
**************** Commands ****************
.inc comp21n1.mdl
.op
.tran .001n 20.001n 0.1n sweep ctrl 0V 3V .5V
.four 1.1g v(3,2)
.print tran i(M1) i(M2) i(m3) i(m4)
.option dccap=1 post nomod
.print cgb = Par('LX18(XC1.M1) + LX19(XC1.M1) + LX20(XC1.M1)')
+ CBG=Par('-LX21(XC1.M1)')
+ CGS=Par('-LX20(XC1.M1)')
+ CSG=Par('LX18(XC1.M1) + LX21(XC1.M1) + LX32(XC1.M1)')
+ CGD=Par('-LX19(XC1.M1)')
+ CDG=Par('-LX32(XC1.M1)')
+ CG =Par('LX14(XC1.M1)')
+ CGtot =Par('- LX19(XC1.M1) - LX21(XC1.M1) -LX20(XC1.M1)')
.option POST
.end
54
Chapter A Hspice Simulation Files
A.6 VCO with Non-Ideal Current Source, Varac-
tors and Spiral Inductors
************* Circuit Data ***************
.inc spind.sp
.inc newmoscap.sp
Vdd (6 0) DC 3V
Ianr (3 0) PULSE (0A 1mA 0 0 0 0.5n 1)
M3 (3 2 6 6) P (L=lp W=wp)
M4 (2 3 6 6) P (L=lp W=wp)
XL1 (3 5 0) spind
XL2 (2 5 0) spind
XC1 (3 2 7) moscap
V7 (7 0) DC ctrl
M1 (3 2 1 0) N (L=ln W=wn)
M2 (2 3 1 0) N (L=ln W=wn)
V10 (1 10) 0.0000001mV
*R1 (10 0) 1k
*I1 (10 0) DC tail
MC1 (10 8 0 0) N (L=.7u W=130u)
MC2 (8 8 0 0) N (L=.7u W=130u)
I1 (0 8) DC tail
Cload1 (3 0) 40fF
Cload2 (2 0) 40fF
********** Parameterdefinitions **********
55
Chapter A Hspice Simulation Files
.param wp = 162u
.param lp = 0.4u
.param wn = 60u
.param ln = 0.4u
.param ctrl = 1.7V
.param tail = 5mA
**************** Commands ****************
.inc comp21n1.mdl
*The measure of a man is the way he bears up under misfortune.
* ~Plutarch ~
.op
.tran 0.001n 60.001n 0.1n sweep ctrl 0V 3V 0.5V
.four 1.05g v(3,2) v(2) v(3)
.print tran i(M1) i(M2) i(m3) i(m4) i(mc1) i(mc2) i(v10)
.option dccap=1 post nomod
.print cgb = Par('LX18(XC1.M1) + LX19(XC1.M1) + LX20(XC1.M1)')
+ CBG=Par('-LX21(XC1.M1)')
+ CGS=Par('-LX20(XC1.M1)')
+ CSG=Par('LX18(XC1.M1) + LX21(XC1.M1) + LX32(XC1.M1)')
+ CGD=Par('-LX19(XC1.M1)')
+ CDG=Par('-LX32(XC1.M1)')
+ CG =Par('LX14(XC1.M1)')
+ CGtot =Par('- LX19(XC1.M1) - LX21(XC1.M1) -LX20(XC1.M1)')
.option POST
.end
A.7 VCO including all Parasitic Capacitances and
some Resistances
************* Circuit Data ***************
.inc spind.sp
56
Chapter A Hspice Simulation Files
.inc newmoscapsim.sp
Vdd (30 0) DC 3V
Ianr (3 0) PULSE (0A 1mA 0 0 0 0.5n 1)
M3 (3 2 6 6) P L=0.40U W=162.00U AD=89.10P PD=170.80U
+ AS=98.21P PS=191.95U
M4 (2 3 6 6) P L=0.40U W=162.00U AD=89.10P PD=170.80U
+ AS=98.21P PS=191.95U
M1 (3 2 1 0) N L=0.40U W=60.00U AD=39.75P PD=80.30U
+ AS=33.00P PS=64.40U
M2 (2 3 1 0) N L=0.40U W=60.00U AD=39.75P PD=80.30U
+ AS=33.00P PS=64.40U
MC1 (10 8 32 32) N (L=.7u W=130.4u) AD=79.87P PD=182.60U
+ AS=65.20P PS=146.40U
MC2 (8 8 32 32) N (L=.7u W=130u) AD=79.62P PD=172.30U
+ AS=65.00P PS=138.00U
XL1 (3 5 0) spind
XL2 (2 5 0) spind
XC1 (3 2 7) moscap
V7 (7 0) DC ctrl
I1 (0 31) DC tail
Cload1 (3 0) 40fF
Cload2 (2 0) 40fF
CC1 (10 8) 5.52000E-15
CC2 (10 0) 3.50858E-14
CC3 (1 3) 6.33179E-15
CC4 (1 2) 6.29158E-15
CC5 (8 0) 1.15950E-13
CC6 (3 0) 6.51073E-14
57
Chapter A Hspice Simulation Files
CC7 (3 2) 4.28437E-16
CC8 (3 6) 3.45477E-14
CC9 (3 5) 2.14420E-13
CC10 (2 0) 6.53114E-14
CC11 (2 6) 3.45477E-14
CC12 (2 5) 2.14412E-13
CC13 (5 0) 3.51204E-14
Rsh1 (30 6) 630m
Rsh2 (31 8) 150m
Rsh3 (32 0) 82.5m
Rsh4 (1 10) 186m
********** Parameterdefinitions **********
.param wp = 'wn*2.7'
.param lp = 0.4u
.param wn = 60u
.param ln = 0.4u
.param ctrl = 1.7V
.param Cres = 4.12p
.param tail = 5mA
**************** Commands ****************
.inc comp21n1.mdl
.op
.tran 0.001n 80.001n 0.1n sweep ctrl 0V 3V .1V
.four 1.05g v(3,2) v(2) v(3)
.option dccap=1 post nomod
.print cgb = Par('LX18(XC1.M1) + LX19(XC1.M1) + LX20(XC1.M1)')
+ CBG=Par('-LX21(XC1.M1)')
+ CGS=Par('-LX20(XC1.M1)')
+ CSG=Par('LX18(XC1.M1) + LX21(XC1.M1) + LX32(XC1.M1)')
+ CGD=Par('-LX19(XC1.M1)')
58
Chapter A Hspice Simulation Files
+ CDG=Par('-LX32(XC1.M1)')
+ CG =Par('LX14(XC1.M1)')
+ CGtot =Par('- LX19(XC1.M1) - LX21(XC1.M1) -LX20(XC1.M1)')
.option POST
.end
A.8 Finding the Equivalent Parallel Resistance of
the LC Tank at Resonance Frequency
************* Circuit Data ***************
.inc spind.sp
XL1 (1 0 0) spind
C1 (1 0) Cres
I1 (1 0) DC 0 AC 1
********** Parameterdefinitions **********
.param Cres = 4.9p
**************** Commands ****************
.inc comp21n1.mdl
.op
.ac DEC 1000 .1g 10g
.pz v(1) I1
.option POST
.end
A.9 Determining the Q-Factor of the Varactor and
its Series Resistance
************* Circuit Data ***************
L1 (1 0) 4.06nH
M1 (2 1 2 2) P (l=1.05u w=1000u)
59
Chapter A Hspice Simulation Files
C1 (1 2) 1440fF
I1 (1 0) DC 0 AC 1
V1 (0 2) DC abc
**************** Commands ****************
.inc comp21n1.mdl
.op
.dc abc -1.5V 1.5V .1V
.ac DEC 100 .1g 10g sweep abc -1.5 1.5 0.1
.option dccap=1 post nomod
.print cgb = Par('LX18(M1) + LX19(M1) + LX20(M1)')
+ CBG=Par('-LX21(M1)')
+ CGS=Par('-LX20(M1)')
+ CSG=Par('LX18(M1) + LX21(M1) + LX32(M1)')
+ CGD=Par('-LX19(M1)')
+ CDG=Par('-LX32(M1)')
+ CG =Par('LX14(M1)')
+ Cgtot =Par('- LX19(M1) - LX21(M1) -LX20(M1)')
.option POST
.end
60
Appendix B
Picture Gallery
Figure B.1: The di�erent patterns and colors used by Cadence for the various
layers.
Figure B.2: The layout of the two spiral inductors.
61
Chapter B Picture Gallery
Figure B.3: The layout of the nMOS and the pMOS cross coupled pairs.
Figure B.4: The layout of the two varactors.
62
Chapter B Picture Gallery
Figure B.5: The layout of the completely symmetric current source.
Figure B.6: The layout of the LC VCO and all the terminals.
63
Chapter B Picture Gallery
Figure B.7: The layout of the completely symmetric LC VCO.
64
Appendix C
Environment
This thesis was written at the Tokyo Institute of Technology (Titech)
and submitted to the Swiss Federal Institute of Technology (ETH). There
are many di�erences between these two universities that one has to get
accustomed to �rst.
I was working in a students' group of �rst year master's (M1) students
on a 1 year project. Their project started in April 2000. Problems with some
parts of the circuits arose after a few months, making it necessary to change
the structure of the BS Receiver and the VCO's requirements several times.
These changes were still in progress when I joined the project in November
2000. Communication with the other students was sometimes challenging
because of language barriers; furthermore, most group meetings were held
in Japanese, making it diÆcult for me to join the ongoing discussions.
The �rst month was spent reading papers, attending Japanese technical
seminars and meetings in order to decide on the topology of the BS Receiver
and its VCO. The many changes in the topology made it diÆcult to choose
what type of VCO had the most advantageous properties. More than one
week was spent building a Simulink VCO model with adjustable phase noise
performance in order to simulate the complete BS Receiver. This model
could help us determine how crucial phase noise on the BS Receiver is. The
model was never used, as the other parts of the BS Receiver model were not
�nished during the course of this thesis. The VCO was ulitized as a local
oscillator for the down mixer, therefore, a low noise VCO was required.
The physical parameters of the 0.35 �m CMOS process were not exact
65
Chapter C Environment
enough to enable the use of a passive LC VCO, as the performance of the
spiral inductor depends very much on these parameters. An alternative was
the employment of an active LC resonator, as some publications reported
low phase noise performance due to the use of this resonator. Many weeks
were spent performing simulations with active LC resonators, however, no
promising results could be attained.
After two months without much progress, speci�cations were �xed by
ETH and the not very reliable physical process-parameters were used to
design an LC VCO. Further problems arose with the programs needed to
design a circuit. As I was the �rst to use the 0.35 �m technology in this
laboratory, Cadence had to be con�gured, the design rule checker (DRC)
had to be set up, the program Dracula had to be con�gured and the
Postscript printers had to be installed.
The computers at Titech are maintained by master's students of the
Laboratory. Therefore, at least every second year the system operator
changes. This causes the network to be non-homogeneous: many di�erent
keyboards are present and many di�erent operating systems (Win2k,
Solaris, FreeBSD, Linux) co-exist. Not all tasks can be ful�lled on each
system and di�erent shells and login-scripts are installed on di�erent
computers, making work challenging at times.
The time set for a master's thesis at Titech is 1 year; at ETH the time
frame for the diploma thesis is 4 months, however, the collaboration with
the student's advisor during this time is much closer. At Titech the students
work mainly on their own, and present their projects during seminars where
they receive advice from their professors, working by themselves again
afterwards.
The project was very interesting and educative, nevertheless, due to all
these di�erences and diÆculties, the obtained results are not quite as con-
clusive as results that could likely be obtained if the work were completed
in a more familiar surrounding. On the other hand, many topics not directly
related to electronics were explored and I was able to familiarize myself with
another culture, making this project a highly rewarding experience.
66
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