Efficient System-Level DSP Design Flow with WiMAX DUC and ... · Efficient System-Level DSP Design...
Transcript of Efficient System-Level DSP Design Flow with WiMAX DUC and ... · Efficient System-Level DSP Design...
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Efficient System-Level DSP Design Flow with WiMAX DUC and DDC Case Study
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© 2006 Altera Corporation 2
Agenda
FPGA in digital signal processing (DSP)
applications overview
System-level design tools for Altera® FPGAs
Overview
Introduction to DSP Builder
DSP Builder design flow walkthrough
Case study: WiMAX digital upconverter (DUC)
and digital downconverter (DDC) design
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© 2006 Altera Corporation 3
FPGA in DSP Applications
Consumer
Broadcast
Communications
Military
Industrial Automotive
Medical Test and
Measurement
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© 2006 Altera Corporation 4
DSP Design Flow in FPGA
Traditional Focus
of FPGA Tools
Area of
Innovation
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© 2006 Altera Corporation 5
IP Integration
Software
Development
System Integration
DSP Algorithm
Development
Altera System-Level Design Tools
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© 2006 Altera Corporation 6
What is DSP Builder? Interface between Quartus II and
MATLAB/Simulink
Library add-on to Simulink
Altera blockset Library of fixed-point Simulink functions
Uses double precision
Altera DSP IP OpenCore Plus
SignalCompiler utility Converts between Simulink
and Altera domain
Hardware debug
Hardware in the loop (HIL)/ SignalTap® logic analyzer
Floating Point Simulation
Signal Compiler
MDL Schematic Generic Simulink
Block
Fixed Point Conversion with Altera BlockSet
Fixed Point Simulation
Start
Simulink Design Entry
Synplify Pro
LeonardoSpecturm
Quartus II
RTL Synthesis
Quartus II
Fitting
ModelSim
RTL Simulation
Quartus II
Wave Simulation
DSP Builder
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© 2006 Altera Corporation 7
System-Level Simulation
of Algorithm Model
MATLAB/Simulink
Traditional System Design Tool Flow Development
Algorithm
Modeling (C/C++,M,MDL)
RTL Implementation
RTL Simulation
Precision, Synplify
Quartus II, ModelSim
Implementation
Synthesis
Place & Route
Simulation (VHDL/Verilog)
System-Level Verification of
Hardware Implementation
Hardware
Verification
System-Level
Verification (POF)
System Algorithm Design and FPGA Design Separated
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© 2006 Altera Corporation 8
System-Level Simulation
of Algorithm Model
MATLAB/Simulink
System-Level Verification of
Hardware Implementation
Hardware
RTL Implementation
RTL Simulation
LeonardoSpectrum
Precision, Synplify
Quartus II, ModelSim
DSP Builder - Simulink Design Flow
Single Simulink Representation
System-Level
Verification
Synthesis, Place and Route, RTL Simulation
Algorithm
Modeling
Development Implementation Verification
System Algorithm Design and FPGA Design Integrated
Algorithm
Modeling (C/C++,M,MDL)
Synthesis
Place & Route
Simulation (VHDL/Verilog)
System-Level
Verification (POF)
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© 2006 Altera Corporation 9
DSP Builder Features
Automatic generation of VHDL design from a
MATLAB/Simulink representation
Automatic generation of VHDL testbench Captures stimulus from Simulink, writes testbench
HDL import
Reads in design: Verilog or VHDL, or Quartus II project
Creates Simulink simulation model
SignalTap embedded logic analyzer Captures internal data and it into MATLAB
HIL testing Pass vectors to/from board
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© 2006 Altera Corporation 10
DSP Builder Benefits
For hardware engineer Extends RTL analysis and debug capabilities to system-
level tool
Access to MATLAB data formatting
Access to a large library of Simulink models
Speeds up simulation run time
Enables IP evaluation at system level
For system-level engineer Allows rapid prototyping with minimal PLD expertise
Provides easy access to hardware evaluation
Extends floating-point to fixed-point system analysis
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© 2006 Altera Corporation 11
DSP Builder Design Flow
Matlab/Simulink Domain
(C+ System Analysis)
VHDL Domain
(Implementation/Simulation)
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© 2006 Altera Corporation 12
Design Flow Overview
1) Create design in Simulink using Altera libraries
2) Simulate in Simulink
3) Add SignalCompiler to model
4) Create HDL code and generate testbench
5) Perform RTL simulation
6) Synthesize HDL code and place and route
7) Program device
8) Verify hardware: SignalTap logic analyzer/HIL
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© 2006 Altera Corporation 13
Altera DSP Builder Libraries AltLab
Arithmetic
Boards
Complex type
Gate and control
I/O and bus
Rate change
SOPC Builder links
State machine functions
Storage
MegaCore functions
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© 2006 Altera Corporation 14
Step 1: Create Design in Simulink Using Altera Libraries
Drag and drop library blocks into Simulink design and parameterize each block
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© 2006 Altera Corporation 15
Parameterization of IP MegaCore Functions
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© 2006 Altera Corporation 16
Step 2: Simulate in Simulink
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© 2006 Altera Corporation 17
Step 3: Add SignalCompiler to Model to
Generate HDL Code • Stratix and Stratix II
• Stratix GX
• Cyclone & Cyclone II
• ACEX® 1K
• Mercury™
• FLEX® 10K and FLEX 6000
• Development Boards
• APEX™ 20K/E/C
• APEX II
Message window
• LeonardoSpectrum™
• Synplify
• Precision
• Quartus II
Testbench generation
• Speed
• Area
• Balanced
• Fast fit – no timing
optimization
• Use current Quartus
II project
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© 2006 Altera Corporation 18
Step 4: Create HDL Code and
Generate Testbench
FilteringLab.vhd
FilteringLab.mdl
Enable “Generate
Stimuli for VHDL
Testbench” Button
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© 2006 Altera Corporation 19
HDL Code Generation
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© 2006 Altera Corporation 20
DSP Builder Report File
Lists all converted blocks
Port widths
Sampling frequencies
Warnings and messages
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© 2006 Altera Corporation 21
Step 5: Perform RTL Simulation (ModelSim)
1) Set working directory (File =>
Change Directory)
2) Run TCL file (Tools =>
Execute Macro)
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© 2006 Altera Corporation 22
Perform Verification
ModelSim
vs.
Simulink
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© 2006 Altera Corporation 23
Step 6: Synthesize HDL and Place and Route
•Synthesis
• Leonardo Spectrum
• Synplify
• Quartus II
•Quartus II Fitter
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© 2006 Altera Corporation 24
Step 7: Program Device
Download Design
to DSP
Development Kits
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© 2006 Altera Corporation 25 © 2006 Altera Corporation 25
Stratix II DSP Development Board
16-Bit Audio Codec
12-Bit, 125-MHz A/D
16-Mbyte SDR SDRAM
9-Pin RS232 Connector
VGA Connector
10/100 Ethernet
Texas Instruments
DSP Connector on Underside
of Board
14-Bit, 165-MHz D/A
Available with EP2S60 or EP2S180 Device
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© 2006 Altera Corporation 26 © 2006 Altera Corporation 26
Cyclone II DSP Development Board
Power Supply
Connector
Stereo Codec
VGA Connector
14-Bit 165-MHz DAC
12-Bit, 125-MHz ADC
TI EMIF Connector
on Underside of Board
1-Mbyte Synchronous
SRAM
Expansion Prototype Connector
256-Mbyte DDR2 DIMM
Now Available with EP2C70 Device
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© 2006 Altera Corporation 27
Step 8: SignalTap II Logic Analyzer
Embedded logic analyzer (ELA) Downloads into device
with design
Captures state of internal nodes
Uses JTAG for communication
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© 2006 Altera Corporation 28
SignalTap II Logic Analyzer
Imported Data
Imported Plot
Analysis of
Imported Data
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© 2006 Altera Corporation 29
Hardware in Loop (HIL)
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© 2006 Altera Corporation 30
Design Flow Review
1) Create design in Simulink using Altera libraries
2) Simulate in Simulink
3) Add SignalCompiler to model
4) Create HDL code and generate testbench
5) Perform RTL simulation
6) Synthesize HDL code and place and route
7) Program device
8) Verify hardware: SignalTap logic analyzer HIL
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© 2006 Altera Corporation 31
System Reference Designs
Altera DSP Development Kits
30-Day Evaluation Version
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WiMAX DUC and DDC Design Case Study
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© 2006 Altera Corporation 33
Base Station Architecture Overview
PLD Applications
Switch
Interface
Control Card
PA
LNA
Timing Card Switch Card
GPS Receiver
Control
Logic
Glue Logic BSC/RNC Interface
IP/ATM Interface
Glue Logic
Host
CPU
Clock Generator
RF Card
Glue Logic
Digital I/F DUC/DDC
A/D D/A
CFR DPD
Channel Card
Multiplexer/ De-
multiplexer
Host uP
IP Proc.
Glue Logic
Baseband Processing
(W-CDMA/
CDMA2000/WiMAX)
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© 2006 Altera Corporation 34
Reference Design Overview
DUC/DDC
Provides the link between digital baseband and analog RF front
end of generic transceiver
High throughput signal processing required makes FPGA
ideal platform
RF Front-end
Baseband Processing
ADC DDC
DAC DUC
RF IF Baseband
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© 2006 Altera Corporation 35
WiMAX DUC and DDC Designs
Compliant to the draft WiMAX standard (IEEE 802.16)
Multi-channel filter design for low cost
Support for multiple transmit and receive antenna
configurations
Easily modifiable to support scalable channel
bandwidths
Uses DSP Builder methodology
Backed up by DSP Builder-ready, highly
parameterizable IP MegaCore functions
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© 2006 Altera Corporation 36
DUC and DDC High-Level Block Diagrams
A/D
From Baseband
Modem
DUC and DDC: Wireless, Military, Medical, Broadcast
Crest-Factor Reduction (CFR) and Digital Predistortion (DPD): Wireless
CFR DPD D/A
FIR
Interpolation
NCO
I
Q
CIC
FIR CIC
To DAC
NCO
CIC Resampler
Q
To Baseband
FIR
CIC Resampler FIR
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© 2006 Altera Corporation 37
DSP Builder Implementation: IP MegaCore Library
IP Can Be Added to the
Library Separately
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© 2006 Altera Corporation 38
DSP Builder Implementation: Digital
Intermediate Frequency (IF) Library
Adapters
Provide input/output
interface to finite impulse
response (FIR) filter
Multichannel
Frame format converter
Decimation
Interpolation
Multiplexer
Demultiplexer
Rounding
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© 2006 Altera Corporation 39 © 2006 Altera Corporation 39
DUC With 2 Antennas Design Architecture
Timeshare DUC Hardware Between Antennas
NCO
FIR FIR
2
FIR
4
I1
Q1
I2
Q2
FIR
4
91.392 MHz 182.784 MHz 45.696 MHz 11.424 MHz 45.696 MHz 91.392 MHz
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© 2006 Altera Corporation 40
DSP Builder Implementation: DUC Example Design With
2 Antennas
Use FIR Compiler IP Use Numerically Controlled Oscillator
(NCO) Compiler IP
Multiplexer Multiplexer
Cascaded Filters Mixer
Oscillator
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© 2006 Altera Corporation 41
Simulation
Cascaded Filter
Output
After Upconversion
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© 2006 Altera Corporation 42
Convert to VHDL: SignalCompiler
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© 2006 Altera Corporation 43
DDC With 4 Antennas Design Architecture
FIR FIR
2
NCO
FIR
4
I1
Q1
I2
Q2
I3
Q3
I4
Q4
FIR
4
FIR
4
FIR
4 oversample
oversample
oversample
oversample
91.392 MHz 182.784 MHz 45.696 MHz 11.424 MHz 182.784 MHz 91.392 MHz
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© 2006 Altera Corporation 44
DSP Builder Implementation: DDC Example
Design With 4 Antennas
Analyze
output data
Input stimulus
loaded as part
of model
Initialization
function
Simulate
button
SignalCompiler
(convert to HDL) Mixer
Multiplexer
Oscillator
Filters
Outputs
Filters
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© 2006 Altera Corporation 45 © 2006 Altera Corporation 45
4xRx DDC Architecture
FIR FIR
2
NCO
FIR
4
I1
Q1
I2
Q2
I3
Q3
I4
Q4
FIR
4
FIR
4
FIR
4
oversample
oversample
oversample
oversample
Remove Redundant Filter Chains Change Input/Output Frame Formats
Modify Number
of Channels Change Input/Output
Frame Formats
2xRx DDC Architecture
30 minutes!
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© 2006 Altera Corporation 46 © 2006 Altera Corporation 46
ALUTs M512 M4K MRAM Multipliers
18x18 fmax
MHz
DUC Time Multiplexed IQ Design
2,113 21 23 0 30 281
DUC 2 Antenna Design
4,229 21 56 0 55 193
DDC Time Multiplexed IQ Design
2,488 19 22 0 25 293
DDC 4 Antenna Design
10,753 67 69 0 74 201
DUC and DDC Synthesis Results
Highly Optimized and Cost Efficient Designs!
More Information at www.altera.com
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© 2006 Altera Corporation 47
Summary
DSP Builder tool improves productivity
System-level DSP design and FPGA design integrated
into one platform: Simulink
WiMAX DUC and DDC application example
DSP Builder-based IQ time multiplexed and multi-
antenna designs
Use FIR compiler and NCO compiler IP
Design methodology significantly reduces the development time for different standards
Highly optimized and cost-efficient designs
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Thank You Q & A