Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon)...

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Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intel lon.com Richard Newman Haniph Latchman (Univ. of Florida) [email protected]

Transcript of Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon)...

Page 1: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

Efficient Framing and ARQ for High-Speed PLC Systems

Srinivas Katar

Larry Yonge

(Intellon)[email protected]

Richard Newman

Haniph Latchman

(Univ. of Florida)[email protected]

Page 2: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

PLC Evolution in a Nutshell

• > 5 yrs ago: Low speed control applications• 1-5 yrs ago: Medium speed data transfer• Now + future: High speed AV, BPL

Page 3: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

QoS Goals for AV PLC

• Data speeds - must sustain application rates of – 6 Mbps per SDTV connection– 24 Mbps per HDTV connection

• Must be QEF (quasi-error-free) for video• Must meet latency requirements (10 ms for

voice, 300 ms for video)

Page 4: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

PLC MAC

• High attenuation => CS but no CD• Per-channel adaptation => Virtual Carrier

Sense• VCS => Broadcast delimiters• Broadcast => high fixed OH per MPDU• High PHY rates => concatenation• Impulse noise….

Page 5: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

Framing Processes

Page 6: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

Powerline Characteristics

• High attenuation• Periodic noise floor variations• Isolated impulse noise• Periodic impulse noise• Continuous impulse noise

Page 7: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

Powerline Attenuation Example

Typical Frequency Response

Page 8: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

Powerline Noise Examples

Dimmer switch

Hair dryer

Page 9: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

Channel Adaptation and MAC Framing

• Impulse noise power is high• Adapting channel to eliminate impulse

noise effects may be impossible• Even when possible, it may reduce data

rate excessively• Hence, need robust ARQ mechanism

Page 10: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

MAC Framing Requirements

• High efficiency absent errors• Ability to cope with errors from impulse

noise• Efficient retransmission• Privacy

Page 11: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

MAC Framing Strategies• 1 MSDU per MPDU - low efficiency

– 25% efficiency sans errors for 1518 B enet pkt

• Require concatenation of MSDUs

• Even with concatenation, single acknowledgement per MPDU too inefficient– <8% for 24 FEC blocks at 10% FER– <30% for 24 FEC blocks at 5% FER

• Require partial delivery to handle inevitable impulse errors

Page 12: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

Viable MAC Framing Strategies

• Viable = concatenation and partial delivery

• Simple Concatenation• Concatenation with demarcation• 2-level framing

Page 13: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

Simple Concatenation

Page 14: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

Simple Concatenation

• Framing– MSDU sequence number (SN)– MSDU Length (Len)– MSDU Frame Check Sequence (FCS)

• Advantages– Low, low overhead– Simplicity

• Disadvantages– MPDU padding to fit PPDU– Loss of all data following FEC block error

Page 15: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

Concatenation with Demarcation

Page 16: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

Concatenation with Demarcation• Framing

– add Header Check Sequence (HCS) to resynchronize after FEC block error

– ID within MPDU (for bitmap Selective ACK)

• Advantages– Can recover data after FEC block error– Selective retransmission of MSDUs

• Disadvantages– More complex– still pad– single FEC block error can corrupt two MSDUs

Page 17: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

2-Level Framing2-LevelFraming

Page 18: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

2-Level Framing• Framing per MSDU - Length• Framing per FEC block

– FCS per FEC block– FEC block SN– MSDU boundary flag and offset

• Advantages– Selective retransmission of FEC blocks– Padding may be avoided– simplifies memory management

• Disadvantages– Complexity

Page 19: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

Framing Efficiency Metrics

• Ratio of total bits of data successfully delivered to total bits sent

• Bits sent includes framing overhead bits and retransmissions

• Ignore MPDU overheads (same for all and system dependent)

• Assume fixed size FEC blocks• Assume FEC block errors independent

Page 20: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

Simple Concatenation Efficiency

fec

msdu

mf

feck

mf

fecN

k

kSC LN

L

L

Lkp

L

Lkpp

111

1

• p = FEC Block error rate• k = location of first error

• Lfec = Length of FEC Block

• Lmf = Length of MAC Frame

• Lmsdu = Length of MSDU

• N = number of FEC Blocks

Page 21: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

2-Level Framing Efficiency

• p = FEC Block error rate

• Lfec = Length of FEC Block

• LOH,sb,2L = per FEC Block overhead

• Lmsdu = Length of MSDU

• N = number of FEC Blocks

fec

msdu

fec

LsbOHfecL LN

L

L

LLp 2,,

2 1

Page 22: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.
Page 23: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.
Page 24: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.
Page 25: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

MSDU length = 1518 bytes (Ethernet)

Page 26: Efficient Framing and ARQ for High-Speed PLC Systems Srinivas Katar Larry Yonge (Intellon) srinivas.katar@intellon.com Richard Newman Haniph Latchman (Univ.

Conclusions• Fixed overheads in PLC and wireless

communications require concatenation when PHY rates are high

• Simple concatenation methods suffer from poor retransmission options

• 2-Level framing method solves these problems, is highly efficient; efficiency independent of MPDU length