EEM16 Lecture 3 UCLA

8/14/2019 EEM16 Lecture 3 UCLA

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EEM16/CSM51A:

Logic Design of Digital Systems

Lecture #3Design of Combinational Systems

Prof. Danijela Cabric

Fall 2013


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Dual: Product of Sums (PoS) Form

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Maxterms

For a boolean function of n variables x1, , xn,

a sum term in which each of the n variables

appears once (either complemented, oruncomplemented) is called a maxterm

Examples


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Indexing Maxterms

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Maxterm Mjindexed by integerj=i=0,,n-1xi2i


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Example: E(x2, x1, x0) = M0M5M6 =

M(0,5,6)


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Example: Table Product of Sums

(Maxterms)

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Conversion Among Canonical Forms

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Universal Set of Gates

A set of gates using which any combinational system

can be built

Example: {AND, OR, NOT}

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More Examples of Universal Sets

{AND, NOT} and {OR, NOT}

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Another Universal Set: {NAND}

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Mixed Logic Notation

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Analysis of Gate Networks

Functional analysis Obtain I/O switching expressions

Obtain a tabular representation of the binary function (if

few variables)

Define high-level input and output variables

use codes to related them to bit-vectors

Obtain a high-level specification of the system

Network characteristics input load factors

fan-out factors

delays12


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Obtain Switching Expressions

Assign names to each connection in the

network

Write switching expressions for each gate

output

Substitute all internal names to obtain

external outputs in terms of external input

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Example Gate Network for Analysis

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Analysis of Networks with NOT,

NAND, and NOR

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Another Example: A NOR Network

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Design optimization

Important real-life design criteria Delay: the time from inputs changing to new correct stable output

Size: area taken by the circuit (proxy: # of transistors)

Other criterion: power, reliability,

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Two Level Networks

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Two types

AND-OR network: Sum of Products

OR-AND network: Product of Sums

Inputs in complemented and uncomplemented forms


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Two-level networks with Different Costs for

f(x2, x1, x0) = one-set(3, 6, 7)4

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Minimal Two-Level Networks

Goal: minimum area minimum # of

transistors

in real life, wires also cost area

Algebraic definition:fewest # of

literals and terms

Each literal and term translates to a

gate input, each of which translates to

two transistors

Inverters ignored

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Minimal Expressions

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Graphical Representation of Switching

Functions: Karnaugh Maps (or K-Maps)

2-dimensional arrays of cells representswitching functions or expressions

n variables 2ncells

Each cell represents a minterm

cell i = assignment i

minterms differing in one variable are ajacent

adjacency condition

any set of 2radjacent rows or columns: assignments

differ in r variables

Useful graphical aid in simplifying expressions22


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K-Maps

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K-Maps (n=1,2,3)

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K-maps (n=4)

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K-maps (n=5)

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Representation of Switching Functions

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Rectangles of 1 and 2 Cells and Sum of

Products

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Rectangle of 4 Cells and Sum of Products

Product term of n-2 literals rectangle of four adjacent 1-cells

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Product term of n-s literals rectangle of 2

s

adjacent 1-cells

EEM16 Lecture 3 UCLA

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