EECS 713 HOMEWORK ASSIGNMENT #2 (170 POINTS)

Design a pseudorandom noise (PN) generator with length 127 Using each of the following technologies (data sheets provided), design a pseudorandom noise generator with a sequence length of 127.

1. FACT (National Semiconductor Advanced CMOS: 74AC devices in DIP package) 2. FAST TTL (Texas Instruments F series TTL: 74F devices in DIP package) 3. 100K ECL (Fairchild 300 series ECL: DIP package) 4. 10G GaAs (GigaBit Logic 10G series: the fastest version in type “C” package) 5. UPG GaAs (NEC Logic)

For each design, provide: a timing diagram for all signals (10 points per technology 5 technologies) estimates of currents from each supply source, a complete list of materials (parts

list), a list of all assumptions made (10 points per technology 5 technologies) For the CMOS and ECL designs (only), provide: a complete schematic showing all pin connections

(10 points per technology 2 technologies) For each technology, determine (10 points per technology 5 technologies) if high-speed design rules should be applied, and the maximum usable clock

frequency. Assumptions used throughout include- for CMOS (FACT) and TTL (FAST) assume a 2-ns risetime (Tr) each trace is 2 inches in length; printed-wiring board (PWB) composed of FR-4 in stripline configuration; assume the worst case timing for all devices, over all temperatures.

Be sure to include the propagation delay through the traces in the timing analysis

Basic circuit arrangement

Technology

Item Points possible

CMOSFACT

TTLFAST

ECL100K

GaAs10G

GaAsUPG TOTALS

Timing diagram 5 X 10 each

Current estimatesList of materials, assumptions

5 X 10 each

Schematics 2 X 10 each

High-speed design rules apply ?Maximum usable clock frequency

5 X 10 each

TOTAL 170

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13�0

1�0

14�5

ns

MR

toQ

n

�Voltage

Range

5�0

is5�0

Vg

0�5

V

AC

Opera

ting

Requirem

ents

Sym

bol

Para

mete

rV

CC�

(V)

74A

CT

74A

CT

Units

TA

ea

25�C

TA

eb

40�C

CL

e50

pF

toa

85�C

CL

e50

pF

Typ

Guara

nte

ed

Min

imum

t SSet-U

pTim

e�H

IGH

orLO

W5�0

0�5

7�0

8�0

ns

AorB

toC

P

t HH

old

Tim

e�H

IGH

orLO

W5�0

0�0

1�5

1�5

ns

CP

toA

orB

t WPuls

eW

idth

�H

IGH

orLO

W5�0

0�5

7�0

8�0

ns

CP

toM

R

t REC

Recovery

Tim

e5�0

0�5

2�0

2�0

ns

MR

toC

P

�Voltage

Range

5�0

is5�0

Vg

0�5

V

Capacitance

Sym

bol

Para

mete

rTyp

Units

Conditio

ns

CIN

InputC

apacitance

4�5

pF

VC

Ce

OPEN

CPD

Pow

erD

issip

ation

45�0

pF

VC

Ce

5�0

V

Capacitance

4

© 2

000

Fai

rchi

ld S

emic

ondu

ctor

Cor

pora

tion

DS

0105

82w

ww

.fairc

hild

sem

i.com

Aug

ust 1

989

Rev

ised

Aug

ust 2

000

100307 Low Power Quint Exclusive OR/NOR Gate

1003

07L

ow

Po

wer

Qu

int

Exc

lusi

ve O

R/N

OR

Gat

e

Gen

eral

Des

crip

tio

nT

he 1

0030

7 is

mon

olith

ic q

uint

exc

lusi

ve-O

R/N

OR

gat

e.T

he F

unct

ion

outp

ut is

the

wire

-OR

of a

ll fiv

e ex

clus

ive-

OR

outp

uts.

All

inpu

ts h

ave

50 k

Ω p

ull-d

own

resi

stor

s.

Fea

ture

s■

Low

Pow

er O

pera

tion

■20

00V

ES

D p

rote

ctio

n

■P

in/fu

nctio

n co

mpa

tible

with

100

107

■V

olta

ge c

ompe

nsat

ed o

pera

ting

rang

e =

−4.2

V to

−5.

7V

■A

vaila

ble

to in

dust

rial g

rade

tem

pera

ture

ran

ge

(PLC

C p

acka

ge o

nly)

Ord

erin

g C

od

e:

Dev

ices

als

o av

aila

ble

in T

ape

and

Ree

l. S

peci

fy b

y ap

pend

ing

the

suffi

x le

tter

“X”

to th

e or

derin

g co

de.

Lo

gic

Sym

bo

l

Pin

Des

crip

tio

ns

Lo

gic

Eq

uat

ion

Co

nn

ecti

on

Dia

gra

ms

24-P

in D

IP

28-P

in P

LC

C

Ord

er N

um

ber

Pac

kag

e N

um

ber

Pac

kag

e D

escr

ipti

on

1000

307P

CN

24E

24-L

ead

Pla

stic

Dua

l-In-

Line

Pac

kage

(P

DIP

), J

ED

EC

MS

-010

, 0.4

00 W

ide

1000

307Q

CV

28A

28-L

ead

Pla

stic

Lea

d C

hip

Car

rier

(PLC

C),

JE

DE

C M

O-0

47, 0

.450

Squ

are

1000

307Q

IV

28A

28-L

ead

Pla

stic

Lea

d C

hip

Car

rier

(PLC

C),

JE

DE

C M

O-0

47, 0

.450

Squ

are

Indu

stria

l Tem

pera

ture

Ran

ge (

−40°

C to

+85

°C)

Pin

Nam

esD

escr

ipti

on

Dna

–Dne

Dat

a In

puts

FF

unct

ion

Out

put

Oa–

Oe

Dat

a O

utpu

ts

Oa–

Oe

Com

plem

enta

ry

Dat

a O

utpu

ts

F=

(D1a

⊕ D

2a)

+ (D

1b⊕

D2b

)+

(D1c

⊕ D

2c)

+(D

1d⊕

D2d

)+

(D1e

⊕ D

2e).

ww

w.fa

irchi

ldse

mi.c

om2

100307

Ab

solu

te M

axim

um

Rat

ing

s(N

ote

1)R

eco

mm

end

ed O

per

atin

gC

on

dit

ion

s

No

te 1

: T

he “

Abs

olut

e M

axim

um R

atin

gs”

are

thos

e va

lues

bey

ond

whi

chth

e sa

fety

of

the

devi

ce c

anno

t be

gua

rant

eed.

The

dev

ice

shou

ld n

ot b

eop

erat

ed a

t th

ese

limits

. th

e pa

ram

etric

val

ues

defin

ed i

n th

e E

lect

rical

Cha

ract

eris

tics

tabl

es a

re n

ot g

uara

ntee

d at

the

abs

olut

e m

axim

um r

atin

g.T

he “

Rec

omm

ende

d O

pera

ting

Con

ditio

ns”

tabl

e w

ill d

efin

e th

e co

nditi

ons

for

actu

al d

evic

e op

erat

ion.

No

te 2

: E

SD

test

ing

conf

orm

s to

MIL

-ST

D-8

83, M

etho

d 30

15.

Co

mm

erci

al V

ersi

on

DC

Ele

ctri

cal C

har

acte

rist

ics

(Not

e 3)

VE

E=

−4.2

V to

−5.

7V, V

CC

= V

CC

A=

GN

D, T

C=

0°C

to +

85°C

No

te 3

: T

he s

peci

fied

limits

rep

rese

nt t

he “

wor

st c

ase”

val

ue f

or t

he p

aram

eter

. S

ince

the

se v

alue

s no

rmal

ly o

ccur

at

the

tem

pera

ture

ext

rem

es,

addi

tiona

lno

ise

imm

unity

and

gua

rdba

ndin

g ca

n be

ach

ieve

d by

dec

reas

ing

the

allo

wab

le s

yste

m o

pera

ting

rang

es. C

ondi

tions

for

test

ing

show

n in

the

tabl

es a

re c

ho-

sen

to g

uara

ntee

ope

ratio

n un

der

“wor

st c

ase”

con

ditio

ns.

DIP

AC

Ele

ctri

cal C

har

acte

rist

ics

VE

E=

−4.2

V to

−5.

7V, V

CC

= V

CC

A=

GN

D

Sto

rage

Tem

pera

ture

(T

ST

G)

−65°

C to

+15

0°C

Max

imum

Jun

ctio

n Te

mpe

ratu

re (

TJ)

+150

°CV

EE P

in P

oten

tial t

o G

roun

d P

in−7

.0V

to +

0.5V

Inpu

t Vol

tage

(D

C)

VE

E to

+0.

5V

Out

put C

urre

nt (

DC

Out

put H

IGH

)−5

0 m

A

ES

D (

Not

e 2)

≥200

0V

Cas

e Te

mpe

ratu

re (

TC

)

Com

mer

cial

0 °C

to +

85°C

Indu

stria

l−4

0°C

to +

85°C

Sup

ply

Vol

tage

(V

EE)

−5.7

V to

−4.

2V

Sym

bo

lP

aram

eter

Min

Typ

Max

Un

its

Co

nd

itio

ns

VO

HO

utpu

t HIG

H V

olta

ge−1

025

−955

−870

mV

VIN

=VIH

(M

ax)

Load

ing

with

VO

LO

utpu

t LO

W V

olta

ge−1

830

−170

5−1

620

mV

or V

IL (

Min

)50

Ω to

−2.

0V

VO

HC

Out

put H

IGH

Vol

tage

−103

5m

VV

IN=

VIH

(M

in)

Load

ing

with

VO

LCO

utpu

t LO

W V

olta

ge−1

610

mV

or V

IL (

Max

)50

Ω to

−2.

0V

VIH

Inpu

t HIG

H V

olta

ge−1

165

−870

mV

Gua

rant

eed

HIG

H S

igna

l

for

All

Inpu

ts

VIL

Inpu

t LO

W V

olta

ge−1

830

−147

5m

VG

uara

ntee

d LO

W S

igna

l

for

All

Inpu

ts

I ILIn

put L

OW

Cur

rent

0.50

μAV

IN=

VIL

(M

in)

I IHIn

put H

IGH

Cur

rent

D2a

–D2e

250

μAV

IN=

VIH

(M

ax)

D1a

–D1e

350

I EE

Pow

er S

uppl

y C

urre

nt−6

9−4

3−3

0m

AIn

puts

Ope

n

Sym

bo

lP

aram

eter

TC

= 0°

CT

C=

+25°

CT

C=

+85°

CU

nit

sC

on

dit

ion

sM

inM

axM

inM

axM

inM

ax

t PLH

Pro

paga

tion

Del

ay

0.55

1.90

0.55

1.80

0.55

1.90

nst P

HL

D2a

–D2e

to O

, O

t PLH

Pro

paga

tion

Del

ay0.

551.

700.

551.

600.

551.

70ns

t PH

LD

1a–D

1e to

O, O

Fig

ures

1, 2

t PLH

Pro

paga

tion

Del

ay1.

152.

751.

152.

751.

153.

00ns

t PH

LD

ata

to F

t TLH

Tra

nsiti

on T

ime

0.35

1.20

0.35

1.20

0.35

1.20

nst T

HL

20%

to 8

0%, 8

0% to

20%

3w

ww

.fairc

hild

sem

i.com

100307

Co

mm

erci

al V

ersi

on

(C

ontin

ued)

PL

CC

AC

Ele

ctri

cal C

har

acte

rist

ics

VE

E=

−4.2

V to

−5.

7V, V

CC

= V

CC

A=

GN

D

Ind

ust

rial

Ver

sio

n

PL

CC

DC

Ele

ctri

cal C

har

acte

rist

ics

(Not

e 4)

VE

E=

−4.2

V to

−5.

7V, V

CC

= V

CC

A=

GN

D, T

C=

−40°

C to

+85

°C

No

te 4

: T

he s

peci

fied

limits

rep

rese

nt t

he “

wor

st c

ase”

val

ue f

or t

he p

aram

eter

. S

ince

the

se v

alue

s no

rmal

ly o

ccur

at

the

tem

pera

ture

ext

rem

es,

addi

tiona

lno

ise

imm

unity

and

gua

rdba

ndin

g ca

n be

ach

ieve

d by

dec

reas

ing

the

allo

wab

le s

yste

m o

pera

ting

rang

es. C

ondi

tions

for

test

ing

show

n in

the

tabl

es a

re c

ho-

sen

to g

uara

ntee

ope

ratio

n un

der

“wor

st c

ase”

con

ditio

ns.

PL

CC

AC

Ele

ctri

cal C

har

acte

rist

ics

VE

E=

−4.2

V to

−5.

7V, V

CC

= V

CC

A=

GN

D

Sym

bo

lP

aram

eter

TC

= 0°

CT

C=

+25°

CT

C=

+85°

CU

nit

sC

on

dit

ion

sM

inM

axM

inM

axM

inM

ax

t PLH

Pro

paga

tion

Del

ay0.

551.

700.

551.

600.

551.

70ns

Fig

ures

1, 2

t PH

LD

2a–D

2e to

O, O

t PLH

Pro

paga

tion

Del

ay0.

551.

500.

551.

400.

551.

50ns

t PH

LD

1a–D

1e to

O, O

t PLH

Pro

paga

tion

Del

ay1.

152.

551.

152.

551.

152.

80ns

t PH

LD

ata

to F

t TLH

Tran

sitio

n T

ime

0.35

1.10

0.35

1.10

0.35

1.10

nst T

HL

20%

to 8

0%, 8

0% to

20%

Sym

bo

lP

aram

eter

TC

=−4

0°C

TC

= 0°

C t

o +

85°C

Un

its

Co

nd

itio

ns

Min

Max

Min

Max

VO

HO

utpu

t HIG

H V

olta

ge−1

085

−870

−102

5−8

70m

VV

IN=

VIH

(Max

)Lo

adin

g w

ith

VO

LO

utpu

t LO

W V

olta

ge−1

830

−157

5−1

830

−162

0m

Vor

VIL

(Min

)50

Ω to

−2.

0V

VO

HC

Out

put H

IGH

Vol

tage

−109

5−1

035

mV

VIN

= V

IH(M

in)

Load

ing

with

VO

LCO

utpu

t LO

W V

olta

ge−1

565

−161

0m

Vor

VIL

(Max

)50

Ω to

−2.

0V

VIH

Inpu

t HIG

H V

olta

ge−1

170

−870

−116

5−8

70m

VG

uara

ntee

d H

IGH

Sig

nal f

or A

ll In

puts

VIL

Inpu

t LO

W V

olta

ge−1

830

−148

0−1

830

−147

5m

VG

uara

ntee

d LO

W S

igna

l for

All

Inpu

ts

I ILIn

put L

OW

Cur

rent

0.50

0.50

μAV

IN=

VIL

(Min

)

I IHIn

put H

IGH

Cur

rent

D2a

–D2e

250

250

μAV

IN=

VIH

(Max

)

D1a

–D1e

350

350

I EE

Pow

er S

uppl

y C

urre

nt−6

9−3

0−6

9−3

0m

AIn

puts

Ope

n

Sym

bo

lP

aram

eter

TC

=−4

0°C

TC

=+2

5°C

TC

=+8

5°C

Un

its

Co

nd

itio

ns

Min

Max

Min

Max

Min

Max

t PLH

Pro

paga

tion

Del

ay0.

451.

700.

551.

600.

551.

70ns

Fig

ures

1, 2

t PH

LD

2a–D

2e to

O, O

t PLH

Pro

paga

tion

Del

ay0.

451.

500.

551.

400.

551.

50ns

t PH

LD

1a–D

1e to

O, O

t PLH

Pro

paga

tion

Del

ay1.

052.

551.

152.

551.

152.

80ns

t PH

LD

ata

to F

t TLH

Tran

sitio

n T

ime

0.35

1.10

0.35

1.10

0.35

1.10

nst T

HL

20%

to 8

0%, 8

0% to

20%

ww

w.fa

irchi

ldse

mi.c

om4

100307

Test

Cir

cuit

ry

No

tes:

VC

C, V

CC

A=

+2V

, VE

E=

−2.5

V

L1 a

nd L

2 =

equa

l len

gth

50Ω

impe

danc

e lin

es

RT

= 50

Ω te

rmin

ator

inte

rnal

to s

cope

Dec

oupl

ing

0.1

μF fr

om G

ND

to V

CC

and

VE

E

All

unus

ed o

utpu

ts a

re lo

aded

with

50Ω

to G

ND

CL

= F

ixtu

re a

nd s

tray

cap

acita

nce

≤ 3

pF

FIG

UR

E 1

. AC

Tes

t C

ircu

it

Sw

itch

ing

Wav

efo

rms FIG

UR

E 2

. Pro

pag

atio

n D

elay

an

d T

ran

siti

on

Tim

es

© 2

000

Fai

rchi

ld S

emic

ondu

ctor

Cor

pora

tion

DS

0098

80w

ww

.fairc

hild

sem

i.com

July

198

8

Rev

ised

Aug

ust 2

000

100341 Low Power 8-Bit Shift Register

1003

41L

ow

Po

wer

8-B

it S

hif

t R

egis

ter

Gen

eral

Des

crip

tio

nT

he 1

0034

1 co

ntai

ns e

ight

edg

e-tr

igge

red,

D-t

ype

flip-

flops

with

ind

ivid

ual

inpu

ts (

Pn)

and

out

puts

(Q

n) f

or p

aral

lel

oper

atio

n, a

nd w

ith s

eria

l inp

uts

(Dn)

and

ste

erin

g lo

gic

for

bidi

rect

iona

l sh

iftin

g.

The

fli

p-flo

ps

acce

pt

inpu

t da

ta

ase

tup

time

befo

re t

he p

ositi

ve-g

oing

tra

nsiti

on o

f th

e cl

ock

puls

e an

d th

eir

outp

uts

resp

ond

a pr

opag

atio

n de

lay

afte

rth

is r

isin

g cl

ock

edge

.

The

circ

uit

oper

atin

g m

ode

is d

eter

min

ed b

y th

e S

elec

tin

puts

S0

and

S1,

whi

ch a

re i

nter

nally

dec

oded

to

sele

ctei

ther

“pa

ralle

l en

try”

, “h

old”

, “s

hift

left”

or

“shi

ft rig

ht”

asde

scrib

ed i

n th

e T

ruth

Tab

le.

All

inpu

ts h

ave

50 k

Ω p

ull-

dow

n re

sist

ors.

Fea

ture

s■

35%

pow

er r

educ

tion

of th

e 10

0141

■20

00V

ES

D p

rote

ctio

n

■P

in/fu

nctio

n co

mpa

tible

with

100

141

■V

olta

ge c

ompe

nsat

ed o

pera

ting

rang

e =

−4.2

V to

−5.

7V

■A

vaila

ble

to in

dust

rial g

rade

tem

pera

ture

ran

ge

Ord

erin

g C

od

e:

Dev

ices

als

o av

aila

ble

in T

ape

and

Ree

l. S

peci

fy b

y ap

pend

ing

the

suffi

x le

tter

“X”

to th

e or

derin

g co

de.

Lo

gic

Sym

bo

l

Pin

Des

crip

tio

ns

Co

nn

ecti

on

Dia

gra

ms

24-P

in D

IP/S

OIC

28-P

in P

LC

C

Ord

er N

um

ber

Pac

kag

e N

um

ber

Pac

kag

e D

escr

ipti

on

1003

4SC

M24

B24

-Lea

d S

mal

l Out

line

Inte

grat

ed C

ircui

t (S

OIC

), J

ED

EC

MS

-013

, 0.3

00 W

ide

1003

41P

CN

24E

24-L

ead

Pla

stic

Dua

l-In-

Line

Pac

kage

(P

DIP

), J

ED

EC

MS

-010

, 0.4

00 W

ide

1003

41Q

IV

28A

28-L

ead

Pla

stic

Lea

d C

hip

Car

rier

(PLC

C),

JE

DE

C M

O-0

47, 0

.450

Squ

are

1003

41Q

CV

28A

28-L

ead

Pla

stic

Lea

d C

hip

Car

rier

(PLC

C),

JE

DE

C M

O-0

47, 0

.450

Squ

are

Indu

stria

l Tem

pera

ture

Ran

ge (

−40°

C to

+85

°C)

Pin

Nam

esD

escr

ipti

on

CP

Clo

ck In

put

S0,

S1

Sel

ect I

nput

s

D0,

D7

Ser

ial I

nput

s

P0–

P7

Par

alle

l Inp

uts

Q0–

Q7

Dat

a O

utpu

ts

ww

w.fa

irchi

ldse

mi.c

om2

100341

Tru

th T

able

H=

HIG

H V

olta

ge L

evel

L=

LOW

Vol

tage

Lev

elX

= D

on’t

Car

e=

LOW

-to-

HIG

H T

rans

ition

Lo

gic

Dia

gra

m

Fu

nct

ion

Inp

uts

Ou

tpu

ts

D7

D0

S1

S0

CP

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

Load

Reg

iste

rX

XL

LP

7P

6P

5P

4P

3P

2P

1P

0

Shi

ft Le

ftX

LL

HQ

6Q

5Q

4Q

3Q

2Q

1Q

0L

Shi

ft Le

ftX

HL

HQ

6Q

5Q

4Q

3Q

2Q

1Q

0H

Shi

ft R

ight

LX

HL

LQ

7Q

6Q

5Q

4Q

3Q

2Q

1

Shi

ft R

ight

HX

HL

HQ

7Q

6Q

5Q

4Q

3Q

2Q

1

Hol

dX

XH

HX

Hol

dX

XX

XH

No

Cha

nge

Hol

dX

XX

XL

3w

ww

.fairc

hild

sem

i.com

100341

Ab

solu

te M

axim

um

Rat

ing

s(N

ote

1)R

eco

mm

end

ed O

per

atin

gC

on

dit

ion

s

No

te 1

: T

he “

Abs

olut

e M

axim

um R

atin

gs”

are

thos

e va

lues

bey

ond

whi

chth

e sa

fety

of

the

devi

ce c

anno

t be

gua

rant

eed.

The

dev

ice

shou

ld n

ot b

eop

erat

ed a

t th

ese

limits

. T

he p

aram

etric

val

ues

defin

ed i

n th

e E

lect

rical

Cha

ract

eris

tics

tabl

es a

re n

ot g

uara

ntee

d at

the

abs

olut

e m

axim

um r

atin

g.T

he “

Rec

omm

ende

d O

pera

ting

Con

ditio

ns”

tabl

e w

ill d

efin

e th

e co

nditi

ons

for

actu

al d

evic

e op

erat

ion.

No

te 2

: E

SD

test

ing

conf

orm

s to

MIL

-ST

D-8

83, M

etho

d 30

15.

Co

mm

erci

al V

ersi

on

DC

Ele

ctri

cal C

har

acte

rist

ics

(Not

e 3)

VE

E=

−4.2

V to

−5.

7V, V

CC

= V

CC

A=

GN

D, T

C=

0°C

to +

85°C

No

te 3

: T

he s

peci

fied

limits

rep

rese

nt t

he “

wor

st c

ase”

val

ue f

or t

he p

aram

eter

. S

ince

the

se v

alue

s no

rmal

ly o

ccur

at

the

tem

pera

ture

ext

rem

es,

addi

tiona

lno

ise

imm

unity

and

gua

rdba

ndin

g ca

n be

ach

ieve

d by

dec

reas

ing

the

allo

wab

le s

yste

m o

pera

ting

rang

es. C

ondi

tions

for

test

ing

show

n in

the

tabl

es a

re c

ho-

sen

to g

uara

ntee

ope

ratio

n un

der

“wor

st c

ase”

con

ditio

ns.

DIP

AC

Ele

ctri

cal C

har

acte

rist

ics

VE

E=

−4.2

V to

−5.

7V, V

CC

= V

CC

A=

GN

D

No

te 4

: T

he p

ropa

gatio

n de

lay

spec

ified

is fo

r th

e sw

itchi

ng o

f a s

ingl

e ou

tput

. Del

ays

may

var

y up

to 0

.40

ns if

mul

tiple

out

puts

are

sw

itchi

ng s

imul

tane

ousl

y.

Sto

rage

Tem

pera

ture

(T

ST

G)

−65°

C to

+15

0°C

Max

imum

Jun

ctio

n Te

mpe

ratu

re (

TJ)

+150

°CV

EE P

in P

oten

tial t

o G

roun

d P

in−7

.0V

to +

0.5V

Inpu

t Vol

tage

(D

C)

VE

E to

+0.

5V

Out

put C

urre

nt (

DC

Out

put H

IGH

)−5

0 m

A

ES

D (

Not

e 2)

≥200

0V

Cas

e Te

mpe

ratu

re (

TC

)

Com

mer

cial

0 °C

to +

85°C

Indu

stria

l−4

0°C

to +

85°C

Sup

ply

Vol

tage

(V

EE)

−5.7

V to

−4.

2V

Sym

bo

lP

aram

eter

Min

Typ

Max

Un

its

Co

nd

itio

ns

VO

HO

utpu

t HIG

H V

olta

ge−1

025

−955

−870

mV

VIN

= V

IH (

Max

)Lo

adin

g w

ith

VO

LO

utpu

t LO

W V

olta

ge−1

830

−170

5−1

620

mV

or V

IL (

Min

)50

Ω to

−2.

0V

VO

HC

Out

put H

IGH

Vol

tage

−103

5m

VV

IN=

VIH

(M

in)

Load

ing

with

VO

LCO

utpu

t LO

W V

olta

ge−1

610

mV

or V

IL (

Max

)50

Ω to

−2.

0V

VIH

Inpu

t HIG

H V

olta

ge−1

165

−870

mV

Gua

rant

eed

HIG

H S

igna

l

for

all I

nput

s

VIL

Inpu

t LO

W V

olta

ge−1

830

−147

5m

VG

uara

ntee

d LO

W S

igna

l

for

all I

nput

s

I ILIn

put L

OW

Cur

rent

0.50

μAV

IN=

VIL

(M

in)

I IHIn

put H

IGH

Cur

rent

240

μAV

IN=

VIH

(M

ax)

I EE

Pow

er S

uppl

y C

urre

ntIn

puts

OP

EN

−157

−75

mA

VE

E=

−4.2

V to

−4.

8V

−167

−75

mA

VE

E=

−4.2

V to

−5.

7V

Sym

bo

lP

aram

eter

TC

= 0°

CT

C=

+25°

CT

C=

+85°

CU

nit

sC

on

dit

ion

sM

inM

axM

inM

axM

inM

ax

f MA

XM

ax C

lock

Fre

quen

cy40

040

040

0M

Hz

Fig

ures

2, 3

t PLH

Pro

paga

tion

Del

ay0.

901.

901.

002.

001.

002.

10ns

Fig

ures

1, 3

t PH

LC

P to

Out

put

(Not

e 4)

t TLH

Tra

nsiti

on T

ime

0.35

1.30

0.35

1.30

0.35

1.30

nsF

igur

es 1

, 3t T

HL

20%

to 8

0%, 8

0% to

20%

t SS

etup

Tim

eD

n, P

n0.

650.

650.

65ns

Fig

ure

4S

n1.

601.

601.

60

t HH

old

Dn,

Pn

0.80

0.80

0.80

ns

Sn

0.60

0.60

0.60

t PW

(H)

Pul

se W

idth

HIG

HC

P2.

002.

002.

00ns

Fig

ure

3

ww

w.fa

irchi

ldse

mi.c

om4

100341

Co

mm

erci

al V

ersi

on

(C

ontin

ued)

SO

IC a

nd

PL

CC

AC

Ele

ctri

cal C

har

acte

rist

ics

VE

E=

−4.2

V to

−5.

7V, V

CC

= V

CC

A=

GN

D

No

te 5

: T

he p

ropa

gatio

n de

lay

spec

ified

is fo

r th

e sw

itchi

ng o

f a s

ingl

e ou

tput

. Del

ays

may

var

y up

to 0

.40

ns if

mul

tiple

out

puts

are

sw

itchi

ng s

imul

tane

ousl

y.

No

te 6

: O

utpu

t-to

-Out

put S

kew

is d

efin

ed a

s th

e ab

solu

te v

alue

of t

he d

iffer

ence

bet

wee

n th

e ac

tual

pro

paga

tion

dela

y fo

r an

y ou

tput

s w

ithin

the

sam

e pa

ck-

aged

dev

ice.

The

spe

cific

atio

ns a

pply

to

any

outp

uts

switc

hing

in t

he s

ame

dire

ctio

n ei

ther

HIG

H-t

o-LO

W (

t OS

HL)

, or

LO

W-t

o-H

IGH

(t O

SL

H),

or

in o

ppos

ite

dire

ctio

ns b

oth

HL

and

LH (

t OS

T).

Par

amet

ers

t OS

T a

nd t P

S g

uara

ntee

d by

des

ign

Sym

bo

lP

aram

eter

TC

= 0°

CT

C=

+25°

CT

C=

+85°

CU

nit

sC

on

dit

ion

sM

inM

axM

inM

axM

inM

ax

f MA

XM

axim

um C

lock

Fre

quen

cy42

542

542

5M

Hz

Fig

ures

2, 3

t PLH

Pro

paga

tion

Del

ay0.

901.

701.

001.

801.

001.

90ns

Fig

ures

1, 3

t PH

LC

P to

Out

put

(Not

e 5)

t TLH

Tra

nsiti

on T

ime

0.35

1.20

0.35

1.20

0.35

1.20

nsF

igur

es 1

, 3t T

HL

20%

to 8

0%, 8

0% to

20%

t SS

etup

Tim

eD

n, P

n0.

550.

550.

55ns

Sn

1.50

1.50

1.50

Fig

ure

4t H

Hol

d Ti

me

Dn,

Pn

0.70

0.70

0.70

nsS

n0.

500.

500.

50

t PW

(H)

Pul

se W

idth

HIG

HC

P2.

002.

002.

00ns

Fig

ure

3

t OS

HL

Max

imum

Ske

w C

omm

on E

dge

PLC

C O

nly

Out

put-

to-O

utpu

t Var

iatio

n20

020

020

0ps

(Not

e 6)

Clo

ck to

Out

put P

ath

t OS

LHM

axim

um S

kew

Com

mon

Edg

eP

LCC

Onl

y

Out

put-

to-O

utpu

t Var

iatio

n20

020

020

0ps

(Not

e 6)

Clo

ck to

Out

put P

ath

t OS

TM

axim

um S

kew

Opp

osite

Edg

eP

LCC

Onl

y

Out

put-

to-O

utpu

t Var

iatio

n25

025

025

0ps

(Not

e 6)

Clo

ck to

Out

put P

ath

t ps

Max

imum

Ske

wP

LCC

Onl

y

Pin

(S

igna

l) T

rans

ition

Var

iatio

n25

025

025

0ps

(Not

e 6)

Clo

ck to

Out

put P

ath

5w

ww

.fairc

hild

sem

i.com

100341

Ind

ust

rial

Ver

sio

n

PL

CC

DC

Ele

ctri

cal C

har

acte

rist

ics

(Not

e 7)

VE

E=

−4.2

V to

−5.

7V, V

CC

= V

CC

A=

GN

D, T

C=

−40°

C to

+85

°C

No

te 7

: T

he s

peci

fied

limits

rep

rese

nt t

he “

wor

st c

ase”

val

ue f

or t

he p

aram

eter

. S

ince

the

se v

alue

s no

rmal

ly o

ccur

at

the

tem

pera

ture

ext

rem

es,

addi

tiona

lno

ise

imm

unity

and

gua

rdba

ndin

g ca

n be

ach

ieve

d by

dec

reas

ing

the

allo

wab

le s

yste

m o

pera

ting

rang

es. C

ondi

tions

for

test

ing

show

n in

the

tabl

es a

re c

ho-

sen

to g

uara

ntee

ope

ratio

n un

der

“wor

st c

ase”

con

ditio

ns.

PL

CC

AC

Ele

ctri

cal C

har

acte

rist

ics

VE

E=

−4.2

V to

−5.

7V, V

CC

= V

CC

A=

GN

D

No

te 8

: T

he p

ropa

gatio

n de

lay

spec

ified

is fo

r th

e sw

itchi

ng o

f a s

ingl

e ou

tput

. Del

ays

may

var

y up

to 0

.40

ns if

mul

tiple

out

puts

are

sw

itchi

ng s

imul

tane

ousl

y.

Sym

bo

lP

aram

eter

TC

=−4

0°C

TC

= 0°

C t

o +

85°C

Un

its

Co

nd

itio

ns

Min

Max

Min

Max

VO

HO

utpu

t HIG

H V

olta

ge−1

085

−870

−102

5−8

70m

VV

IN=

VIH

(Max

)Lo

adin

g w

ith

VO

LO

utpu

t LO

W V

olta

ge−1

830

−157

5−1

830

−162

0m

Vor

VIL

(M

in)

50Ω

to −

2.0V

VO

HC

Out

put H

IGH

Vol

tage

−109

5−1

035

mV

VIN

= V

IH (

Min

)Lo

adin

g w

ith

VO

LCO

utpu

t LO

W V

olta

ge−1

565

−161

0m

Vor

VIL

(M

ax)

50Ω

to −

2.0V

VIH

Inpu

t HIG

H V

olta

ge−1

170

−870

−116

5−8

70m

VG

uara

ntee

d H

IGH

Sig

nal

for

all I

nput

s

VIL

Inpu

t LO

W V

olta

ge−1

830

−148

0−1

830

−147

5m

VG

uara

ntee

d LO

W S

igna

l

for

all I

nput

s

I ILIn

put L

OW

Cur

rent

0.50

0.50

μAV

IN=

VIL

(M

in)

I IHIn

put H

IGH

Cur

rent

240

240

μAV

IN=

VIH

(M

ax)

I EE

Pow

er S

uppl

y C

urre

ntIn

puts

OP

EN

−157

−75

−157

−75

mA

VE

E=

−4.2

V to

−4.

8V

−167

−75

−167

−75

mA

VE

E=

−4.2

V to

−5.

7V

Sym

bo

lP

aram

eter

TC

=−4

0°C

TC

=+2

5°C

TC

=+8

5°C

Un

its

Co

nd

itio

ns

Min

Max

Min

Max

Min

Max

f MA

XM

ax C

lock

Fre

quen

cy42

542

542

5M

Hz

Fig

ures

2, 3

t PLH

Pro

paga

tion

Del

ay0.

901.

801.

001.

801.

001.

90ns

Fig

ures

1, 3

t PH

LC

P to

Out

put

(Not

e 8)

t TLH

Tra

nsiti

on T

ime

0.30

1.90

0.35

1.20

0.35

1.20

nsF

igur

es 1

, 3t T

HL

20%

to 8

0%, 8

0% to

20%

t SS

etup

Tim

eD

n, P

n0.

600.

550.

55ns

Sn

1.70

1.50

1.50

Fig

ure

4t H

Hol

d T

ime

Dn,

Pn

0.90

0.70

0.70

ns

Sn

0.50

0.50

0.50

t PW

(H)

Pul

se W

idth

HIG

HC

P2.

002.

002.

00ns

Fig

ure

3

ww

w.fa

irchi

ldse

mi.c

om6

100341

Test

Cir

cuit

ry

No

te:

•V

CC

, VC

CA

=+2

V, V

EE

=−2

.5V

•L1

, L2

and

L3 =

equ

al le

ngth

50Ω

impe

danc

e lin

es

•R

T=

50Ω

term

inat

or in

tern

al to

sco

pe

•D

ecou

plin

g 0.

1 μF

from

GN

D to

VC

Can

d V

EE

•A

ll un

used

out

puts

are

load

ed w

ith 5

0Ω to

GN

D

•C

L=

Fix

ture

and

str

ay c

apac

itanc

e ≤

3 pF

FIG

UR

E 1

. AC

Tes

t C

ircu

it

No

te:

•F

or s

hift

right

mod

e pu

lse

gene

rato

r co

nnec

ted

to S

0 is

mov

ed to

S1.

•P

ulse

gen

erat

or c

onne

cted

to S

1 h

as a

LO

W fr

eque

ncy

99%

dut

y cy

cle,

whi

ch a

llow

s oc

casi

onal

par

alle

l loa

d.

•T

he fe

edba

ck p

ath

from

out

put t

o in

put s

houl

d be

as

shor

t as

poss

ible

.

FIG

UR

E 2

. Sh

ift

Fre

qu

ency

Tes

t C

ircu

it (

Sh

ift

Lef

t)

7w

ww

.fairc

hild

sem

i.com

100341

Sw

itch

ing

Wav

efo

rms FIG

UR

E 3

. Pro

pag

atio

n D

elay

an

d T

ran

siti

on

Tim

es

No

te:

t S is

the

min

imum

tim

e be

fore

the

tran

sitio

n of

the

cloc

k th

at in

form

atio

n m

ust b

e pr

esen

t at t

he d

ata

inpu

t.

t H is

the

min

imum

tim

e af

ter

the

tran

sitio

n of

the

cloc

k th

at in

form

atio

n m

ust r

emai

n un

chan

ged

at th

e da

ta in

put.

FIG

UR

E 4

. Set

up

an

d H

old

Tim

es