EECS 427 Lecture 22: Clock and Power Grid · EECS 427 F09 Lecture 22 1 Reminders • Project...
Transcript of EECS 427 Lecture 22: Clock and Power Grid · EECS 427 F09 Lecture 22 1 Reminders • Project...
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EECS 427Lecture 22: Clock and Power Grid
Readings: 10.3.3, WH 12.3, CBF Ch.24
EECS 427 F09 Lecture 22 1
Reminders
• Project completion by Monday Dec. 14Presentation in class: 1:40 3:30 ( 15 minutes per group)– Presentation in class: 1:40-3:30 (~15 minutes per group)
– Project demo in CSE 1620: 3:30-5:30 (~15 minutes per group)
– Voluntary individual contribution survey (Dec. 10 – 13)– HW5 (final report) due 7 pm– CAD9 due 7 pm
E t ffi h• Extra office hours
• Verify your grades on Monday
EECS 427 F09 Lecture 22 2
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Clocking
• Clock distribution metrics– Area, power, skew
• Clock network distribution types– Tree and grid, hybrid
• Clock skew and jitter from previous l
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lectures
Clocks: Power-Hungry
P = C Vdd2 f
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Not only is the clock capacitance large, it switches every cycle!
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Clock Distribution Metric: Area
• Clock networks consume silicon area (clock drivers, PLL etc ) and routing areaPLL, etc.) and routing area
• Routing area is most vital• Top-level metals are used to reduce RC delays
– These levels are precious resources (unscaled)– Power routing, clock routing, key global signals
• By minimizing area used, we also reduce wiring capacitance & power
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capacitance & power• Typical #’s: Intel Itanium – 4% of M4/5 used in clock
routing
Slew Rates
• To maintain signal integrity and latch performance, minimum slew rates are requiredminimum slew rates are required
• Too slow – clock is more susceptible to noise, latches are slowed down, eats into timing budget
• Too fast – burning too much power, overdesigned network, enhanced ground bounce
• Rule-of-thumb: Trise and Tfall of clock are each between 10-20% of clock period (10% - aggressive
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between 10 20% of clock period (10% aggressive target)– 1 GHz clock; Trise = Tfall = 100-200ps
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The Grid System
Driver
GCLK
Dri
ver
Driv
er
GCLK GCLK
• No matching
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Driver
GCLK
g• Large power (huge drivers)
Network Types: Grid
• Gridded clock distribution was common on earlier Pre-DEC Alpha microprocessors
• Advantages:– Skew determined by grid
density and not overly sensitive to load position
– Clock signals are available
drivers
Global
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Clock signals are available everywhere
– Tolerant to process variations
– Usually yields extremely low skew values
grid
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Grid Disadvantages• Huge amounts of wiring & power
– Wire cap largeWire cap large– Strong drivers needed – pre-driver cap large– Routing area large
• To minimize all these penalties, make grid pitch coarser– Skew gets worse– Losing the main advantage
D ’t d i l t th k b l
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• Don’t overdesign – let the skew be as large as tolerable
• Grids aren’t feasible for most designs due to power
Network Types: Tree
• Original H tree (Bakoglu)• Original H-tree (Bakoglu)– One large central driver
– Recursive H-style structure to match wirelengths
H l i id h
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– Halve wire width at branching points to reduce reflections
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H-Tree Problems
• Drawback to original tree concept– slew degradation along long RC paths– unrealistically large central driver
• Clock drivers can create large temperature gradients (ex. Alpha 21064 ~30° C)
– non-uniform load distribution
• Inherently non-scalable (wire resistance k k t )
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skyrockets)• Solution to some problems
– Introduce intermediate buffers along the way– Specifically at branching points
Buffered H-tree
• AdvantagesIdeally zero skew– Ideally zero-skew
– Can be low power (depending on skew requirements)
– Low area (silicon and wiring)– CAD tool friendly (regular)
• Disadvantages
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g– Sensitive to process
variations– Local clocking loads are
inherently non-uniform
CLK
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Realistic H-tree
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[Restle98]
Balancing a Tree
S t h iCon: Routing area
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Some techniques:
a) Introduce dummy loads
b) Snaking of wirelength to match delays
often more valuable than silicon
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Network of choice in high-performance
• Globally – Tree• Why?• Power
requirements are reduced compared to global grid– Smaller routing
requirements, frees up global tracks
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• Trees are easily balanced at the global level– Keeps global skew
low (with minimal process variation)
Summary
• Getting the clock everywhere on a die at the t ti i diffi ltexact same time is difficult
– Requires a lot of power to reduce skew (big drivers, wide wires, etc.)
• Balanced H-trees are in common use– Design automation tools exist to synthesize these
trees
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• Clocks must be robust to variations/noise, have sharp slew rates, not create too much heat, plus other constraints
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Power Distribution
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Stability Requirement
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IR Drop
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IR Drop Problem
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Technology Trends
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Performance Degradation
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Reduced Noise Margins
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Dealing with IR Drop
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Electromigration
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Electromigration
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Ldi/dt
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Dealing with Ldi/dt
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Summary
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