EECS 373 Midterm · 4. Briefly explain what the volatile keyword in C does and why it is necessary,...

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EECS 373 Midterm Winter 2013

Name: ____________________________________ unique name: _______________

Sign the honor code:

I have neither given nor received aid on this exam nor observed anyone else doing so.

___________________________________

Scores:

# Page Points

2 /15

3 /20

4 /12

5 /13

8 /10

9 /15

10 /15

Total /100

NOTES: 1. Closed book/notes.

2. There are 10 pages including this one.

3. Calculators are allowed, but no PDAs, Portables, Cell phones, etc.

4. Don’t spend too much time on any one problem.

5. You have about 80 minutes for the exam.

6. Be sure to show work and explain what you’ve done when asked to do so.

Getting partial credit without showing work will be rare.

7. Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs,

NANDs, NORs, XORs and XNORs as well as NOT gates.

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1. Fill-in-the-blank or circle the best answer. [15 points, -3 per wrong or blank answer, minimum 0]

a) A 10 MHz clock with a duty cycle of 40% is high for ____40_________ ns per cycle.

b) When an ISR “A” can interrupt another (running) ISR “B”, A is said to be able to PREEMPT / override / nest / remove B.

c) Set-up and/or hold time matter in embedded systems primarily because:

the hold time impacts the processor’s clock period.

the set-up time impacts the processor’s ability to use timers.

INPUTS NOT SYNCHRONIZED TO OUR LOCAL CLOCK RUN THE RISK OF VIOLATING THEM.

they have a significant impact on interrupt latency.

d) One interesting feature of our ISA is that:

R11 is used as a dedicated frame pointer

there is no way to use an immediate with more than 4 bits

MANY INSTRUCTION ENCODINGS CAN ONLY USE REGISTERS R0-R7.

e) In the following text, the blank should be replaced with UNIFIED / global / V6T2 / function.

Two slightly different syntaxes are supported for ARM and THUMB instructions. The default, divided, uses the old style where ARM and THUMB instructions had their own, separate syntaxes. The new, _________ syntax, which can be selected via the .syntax directive, and has the following main features:

Immediate operands do not require a # prefix.

The IT instruction may appear, and if it does it is validated against subsequent conditional affixes. In ARM mode it does not generate machine code, in THUMB mode it does.

For ARM instructions the conditional affixes always appear at the end of the instruction. For THUMB instructions conditional affixes can be used, but only inside the scope of an IT instruction.

f) Say we were using an APB bus that had 20 bits for the address and 32 bits for the data. If

the bus were running at 10MHz, the most bandwidth you could expect to get over the bus would be about 10 / 20 / 32 / 40 / 64 Mbytes/sec.

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2. Write an ARM assembly language procedure that implements the following C function in an EABI-

compliant manner and conforms to the following signature. Clearly comment your code so we can figure out what you are doing and what value each register holds. Poorly commented/unclear code will get points removed. [20 points]

uint32 XYbob(uint32 x, uint32 y, uint32 bob[])

{

uint32 mary[10];

fill(mary,x,y); // function moves data into the array mary

if(bob[x]>=mary[y])

return(x);

else

return(y);

}

XYbob:

push {r4,r5,r6,lr}

sub sp, #40 //subtract 40 from sp, making room for mary[]

mov r4, r0 //r4=x

mov r5, r1 //r5=y

mov r6, r2 //r6=bob[]

mov r0, sp // \ Get the arguments for the call to

mov r1, r4 // > “fill” in the right places.

mov r2, r5 // /

bl fill

lsl r0, r4, #2 // r0=4*x

lsl r1, r5, #2 // r1=4*y

ldr r0,[r6,r0] // r0=bob[x]

ldr r1,[sp,r1] // r1=mary[y]

cmp r0, r1

mov r0, r4 // put x into r0, don’t change flags

bhs done // if unsigned greater or same, r0 is correct.

mov r0, r5 // otherwise get y into r0.

done:

add sp, #40 // remove local variable. (Need to do this or

// the pop below will get wrong values!

pop{r4,r5,r6,pc} // We’re done here.

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3. Consider the ARM assembly found below. Assume that r3=0x88AACCDD, r1=0x00002000, and all

other registers and memory locations are initialized to zero. You should assume the processor is in little-endian mode.

str r3, [r1],1

ldrsh r5, [r1,1]!

orr r5, r5, 0xF

strh r3, [r1,-1]

ldr r3, [r1]

What are the values of these registers? You must write your answers as 8-digit hex numbers if you wish to receive credit! [12 points, 4 each, no partial credit]

r1=___0X00002002_______

r3=___0X000088CC_______

r5=___0XFFFF88AF_______

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4. Briefly explain what the volatile keyword in C does and why it is necessary, i.e. what could happen if you forget to use it? [8 points]

The volatile keyword tells the complier that the data could be changed or used by something

other than this program. That basically means that the complier can’t do certain optimizations

that eliminate a load or store to this location. This is key when working with memory-mapped

I/O. Without this keyword, the complier might optimize away a line like

while (a!=0){}

under the assumption that if a!=0, it can just busy wait forever as a won’t be changing. That’s

pretty bad when “a” is an input device. By the same token, a complier will often optimize away

the write to a variable if that variable isn’t read from ever again. But if it’s volatile, the complier

will know it _must_ do the write.

If a MMIO location isn’t declared volatile, lots of bad things could happen. The infinite loop

above and optimizing away writes to output-only memory locations (and thus not updating the

device correctly) being among them.

One note: in class I claimed this should tell the complier not to cache the variable. I’m now

unsure if this is ever the case… Certainly gave credit to those who said it was.

5. Briefly explain why having a “capture” option on a timer is useful. [5 points]

Basic idea is that the timer will store the timer’s current value in a “capture register” when a

certain event occurs. This would allow an ISR or other program to find out exactly what the

timer’s value was when that event occurred. The other basic option is to throw an interrupt and

have the ISR read the value in the timer. The problem with that is that the timer’s value will

likely have changed by the time the ISR does that read. You can get more accuracy on

measuring an event’s occurrence with a capture register.

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Anemometer design

Your task is to design the measurement system for a hand-held anemometer. The

device measures wind speed with a traditional rotating cup system. Wind speed is

determined by measuring the rotation period, scaling and displaying accordingly.

You will likely find it helpful to read the rest of the exam before solving any of the

following parts.

To make the measurement, you have at your disposal a simplified Smart Fusion kit

and a hardware timer.

Interface to the APB bus

The kit has the following APB3 bus interface. The signal names are shown in bold. The ABP3 bus signals

follow APB3 timing and protocol. Read and write cycles are provided on the next page. PSEL is

configured to be “1” when memory locations 0x40050000-0x40050007 are accessed.

As shown, this system has a single interrupt that can be generated. It is level-sensitive and is named

“INT”.

SmartFusion Level Sensitive Interrupt: INT

APB Write Data: PWDATA (32 bits)

APB Read Data: PRDATA (32 bits)

APB Peripheral Write: PWRITE

Peripheral Address: PADDR (8 bits)

Peripheral Select: PSEL

Bus Clock: PCLK

Bus Ready: PREADY

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Hardware Timer

The hardware timer will become the value on TDI if TWE is high on the positive edge of the timer clock.

Otherwise the counter will increment every cycle. If the counter reaches its maximum value it wraps

around to zero (i.e. it is a modulo counter). The current value of the timer is always available on TDO.

APB Timing diagram

The following diagrams are provided as a reminder of the APB timing with no wait states.

Timer Timer Data In: TDI (32 bits)

Timer Data Out: TDO (32 bits)

Timer Write Enable: TWE

Timer Clock: TC

ABP3 Read Timing

ABP3 Write Timing

EECS 373 Midterm · 4. Briefly explain what the volatile keyword in C does and why it is necessary,...

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