EECS 240 Analog Integrated Circuits Lecture 2: CMOS Technology...
Transcript of EECS 240 Analog Integrated Circuits Lecture 2: CMOS Technology...
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 1
EECS 240EECS 240AAnalog Integrated Circuitsnalog Integrated Circuits
Lecture 2: CMOS Technology and Lecture 2: CMOS Technology and Passive DevicesPassive Devices
Ali M. Niknejad and Bernhard E. Boser© 2006
Department of Electrical Engineering and Computer Sciences
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 2
CMOS TechnologyCMOS Technology
• Why look at it (again)?• Key issues:
1. Perspective– Device dimensions– Device performance metrics, e.g.:
– Current efficiency– Speed– Gain– Noise
2. “Short-channel characteristics”– Square-law model– Models for circuit simulation– Design
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 3
TodayToday’’s Lectures Lecture
• CMOS cross-section
• Passive devices– Resistors– Capacitors
• Next time: MOS transistor
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 4
CMOS ProcessCMOS Process
• EECS240 0.18µm 1P6M CMOS– Minimum channel length: 0.18µm– 1 level of polysilicon– 6 levels of metal (Cu)– 1.8V supply
• Other choices– Shorter channel length (90 nm / 1V)– Bipolar, SiGe HBT– SOI
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 5
Supply VoltageSupply Voltage
0
1
2
3
4
5
1 0.8 0.5 0.35 0.25 0.18 0.12 0.08 0.06
Feature Size [µm]
Sup
ply
Vol
tage
[V]
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 6
CMOS Cross SectionCMOS Cross Section
Metal
Poly
p- substrate
n- well
p+ diffusion
n+ diffusion
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 7
DimensionsDimensions
700mµ
6.5nm≥ 0.35µm
1.2mµ
200nm
Drawing is not to scale!
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 8
DevicesDevices
• Active– NMOS, PMOS– NPN, PNP– Diodes
• Passive– Resistors– Capacitors– Inductors
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 9
ResistorsResistors
• No provisions in standard CMOS• Resistors are bad for digital circuits
– Minimized in standard CMOS• Sheet resistance of available layers:
• Example: 100kΩ poly resistor 1µm wide by 20,000µm long
60 mΩ/5 Ω/5 Ω/
1 kΩ/
AluminumPolysiliconN+/P+ diffusionN-well
Sheet resistanceLayer
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 10
Process OptionsProcess Options
• Available for many processes• Add features to “baseline process”• E.g.
– Capacitor option (MIM, 2 level poly, channel implant)– Low VTH devices– “High voltage” devices (3.3V)– EEPROM– Silicide stop option– …
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 11
SilicideSilicide TechnologyTechnology
• Implants used to lower resistance of source/drain and polysilicon.
• Titanium Silicide (TiSi2) is widely used salicide(self-aligned silicide), has low resistivity (13-17 mΩ-cm) with melting point of 1540˚C. Another widely used silicide is CoSi2.
• Platinum Silicide (PtSi) is a highly reliable contact metallization between the silicon substrate and the metal layers (Al).
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 12
Silicide Block OptionSilicide Block Option
• Non-silicided layers have significantly larger sheet resistance
• Resistor nonidealities:– Temperature coefficient: R = f(T)– Voltage coefficient: R = f(V)
5050
-500-500
30,000
5050
500500
20,000
-800200
15001600
-1500
10018050
1001000
N+ polyP+ polyN+ diffusionP+ diffusionN-well
BC [ppm/V]VC [ppm/V]TC [ppm/oC]@ T = 25 oC
R/ [Ω/ ]Layer
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 13
Resistor ExampleResistor Example
Goal: R = 100 kΩ, TC = 1/R x dR/dT = 0
Solution: combination of N+ and P+ poly resistors in series
( ) ( )( )
squares 4.444kΩ801
1
squares 200kΩ201
1
11
0
==−
=
==−
=
⇒∆+++=∆++∆+=
CN
CPP
CP
CNN
CPPCNN
R
PN
CPPCNN
TTRR
TTRR
TTRTRRRTTRTTRR
44 344 2143421
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 14
Voltage CoefficientVoltage Coefficient
Example:Diffusion resistor
Applied voltage modulates depletion width(cross-section of conductive channel)
Well acts as a shield
p- substrate
n- well
p+ diffusion
n+ diffusion
R
V1 V2 VB
( ) ( )
−
++−+−+≈
−=
BCCo
Co VVVBVVVTTR
IVVR
2251 2121
21
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 15
Resistor MatchingResistor Matching• Types of mismatch
– Systematic (e.g. contacts)– Run-to-run variations– Random variations between devices
• Absolute resistor value– E.g. filter time constant, bias current (BG reference)– ~ 15 percent variations (or more)
• Resistor ratios– E.g. opamp feedback network– Insensitive to absolute resistor value– “unit-element” approach rejects systematic variations
(large area for non-integer ratios)– Process gradients– 0.1 … 1 percent matching possible with careful layout
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 16
Resistor LayoutResistor LayoutExample: R1 : R2 = 1 : 2
gradient
R1
0.5 * R2 - ∆R
0.5 * R2 + ∆R
Dummy
Dummy
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 17
Resistor Layout (cont.)Resistor Layout (cont.)Serpentine layout for large values:
Better layout (mitigates offset due to thermoelectric effects):
See Hastings, “The art of analog layout,” Prentice Hall, 2001.
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 18
MOSFETsMOSFETs as Resistorsas Resistors
• Triode region (“square law”):
• Small signal resistance:
• Voltage coefficient:
DSTHGSDSC VVVV
RR
V−−
=∂∂
=11
DSTHGSDSDS
THGSoxD VVVVVVV
LWCI >−
−−= for
2µ
( )
( )DSTHGS
THGSox
DSTHGSoxDS
D
VVVVV
LWC
R
VVVLWC
VI
R
>>−−
≈
−−=∂∂
=
for 1
1
µ
µ
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 19
MOS ResistorsMOS Resistors
Example: R = 1 MΩ • Large R-values realizable in small area• Very large voltage coefficient
• Applications:– MOSFET-C filters: (linearization)
Ref: Tsividis et al, “Continuous-Time MOSFET-C Filters in VLSI,” JSSC, pp. 15-30, Feb. 1986.
– Biasing: (>1GΩ)Ref: Geen et al, “Single-Chip Surface-Micromachined Integrated Gyroscope with 50o/hour Root Allen Variance,” ISSCC, pp. 426-7, Feb. 2002.
( )
( )
1
0
2
V5.0V21
1
2001
V2MΩ1VµA100
1
1
1
−
=
==
−=
=××
=
−=
−≈
THGSVVC
THGSox
THGSox
VVV
VVRCLW
VVLWC
R
DS
µ
µ
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 20
Resistor SummaryResistor Summary
• No or limited support in standard CMOS– Costly: large area (compared to FETs)– Nonidealities:
• Large run-to-run variations• Temperature coefficient• Voltage coefficients (nonlinear)
• Avoid them when you can– Especially in critical areas, e.g.
• Amplifier feedback networks• Electronic filters• A/D converters
– We will get back to this point
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 21
Capacitor ApplicationsCapacitor Applications
• Large value– Bypass capacitors– Frequency compensation
• High accuracy, linearity– Feedback & sampling networks– Filters
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 22
Capacitor OptionsCapacitor Options
BigBig~ 1000Junction capacitors
120Poly-substrate
50Metal-poly
30Metal-substrate
302050Metal-metal
25101000Poly-poly (option)
BigHuge5300Gate
TC [ppm/oC]VC [ppm/V]C [aF/µm2]Type
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 23
MOS CapacitorMOS Capacitor
• High capacitance in inversion:– Linear region– Strong inversion
• SPICE:
IC
VVVIC
=→==
=
11
ω
ω
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 24
MOS CapacitorMOS Capacitor
• High non-linearity, temperature coefficient
• Useful only for non-critical applications, e.g.
– (Miller) compensation capacitor– Bypass capacitor (supply, bias)
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 25
PolyPoly--Poly CapacitorPoly Capacitor
• Applications:– Feedback networks– Filters (SC and continuous time)– Charge redistribution DACs & ADCs
• Cross-section• Bottom- and top-plate parasitics• Shields
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 26
Capacitor LayoutCapacitor Layout
• Unit elements• Shields:
• Etching• Fringing fields
• “Common-centroid”• Wiring and interconnect parasitics
Ref.: Y. Tsividis, “Mixed Analog-Digital VLSI Design and Technology,” McGraw-Hill, 1996.
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 27
Metal CapacitorsMetal Capacitors
• Available in all processes(with at least 2 levels of metalization)
• Large bottom plate parasitic– Often loads amplifier
increased load adds power dissipation
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 28
MIM CapacitorsMIM Capacitors
• Many processes have add-on options such as a MIM capacitor.
• This is simply a metal-insulator-metal (MIM) structure situated in the oxide layers. The insulator is a very thin layer (~25 nm), resulting in high density and relatively low back-plate parasitics.
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 29
Custom Custom ““MOMMOM”” CapacitorsCapacitors
• Metal-Oxide-Metal capacitor. Free with modern CMOS.
• Use lateral flux (~Lmin) and multiple metal layers to realize high capacitance values
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 30
MOM Capacitor Cross SectionMOM Capacitor Cross Section
• Use a wall of metal and vias to realize high density.
• Use as many layers as possible. Use fewer layers to minimize back-plate parasitics.
• Reasonably good matching and accuracy.
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 31
Commercial Commercial BiCMOSBiCMOS ProcessProcess
www.ibm.com/chips/techlib/techlib.nsf/techdocs/FE154539B8C4C01687256CD9007346D7/$file/180-nmCMOS3-24-04.pdf
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 32
Typical 180nm CMOSTypical 180nm CMOS
• Leff < L• High volage IO
devices• High voltage
device has thick oxide
www.ibm.com/chips/techlib/techlib.nsf/techdocs/FE154539B8C4C01687256CD9007346D7/$file/180-nmCMOS3-24-04.pdf
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 33
Triple Well OptionTriple Well Option
• Many modern process have a triple well (deep well) option that allows NFETs to be isolated from the substrate. Older notation: twin-well.
• This provides better immunity from digital noise in a mixed signal circuit.
p-sub
n-welldeep n-well
p-well
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 34
Isolation OptionsIsolation Options
www.ibm.com/chips/techlib/techlib.nsf/techdocs/FE154539B8C4C01687256CD9007346D7/$file/180-nmCMOS3-24-04.pdf
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 35
Bipolar DevicesBipolar Devices
www.ibm.com/chips/techlib/techlib.nsf/techdocs/FE154539B8C4C01687256CD9007346D7/$file/180-nmCMOS3-24-04.pdf
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 36
PassivesPassives
www.ibm.com/chips/techlib/techlib.nsf/techdocs/FE154539B8C4C01687256CD9007346D7/$file/180-nmCMOS3-24-04.pdf
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 37
Distributed EffectsDistributed Effects
• Can model IC resistors as distributed RC circuits.
• Transmission line analysis yields the equivalent 2-port parameters.
• Inductance negligible for small IC structures up to ~10GHz.
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 38
Effective ResistanceEffective Resistance
• Rsh = 100 Ω/□, Cx=3.45×10-5 F/m2• 10kΩ resistor drops to 5kΩ at 1 GHz ! (W=5µ)• High frequency resistance depends on W. Need
distributed model for accurate freq response.
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 39
Capacitor QCapacitor Q
• Current density in capacitor plates drops due to vertical displacement current.
• Must analyze the distributed RC circuit…
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 40
Capacitor ImpedanceCapacitor Impedance
• For a capacitor contacted at one side, we can show that
• We can simplify this for small structures
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 41
Double Contact Double Contact StrucutreStrucutre
• Instead of doing distributed analysis, we can guess the current distribution as linear and quickly calculate the effective resistance.
• For a double contact case, the resistance drops by 4 times.
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 42
• Once in the domain of RF circuits, now inductors are finding applications in wideband design (e.g. shunt peaking).
• By proper design, the bandwidth of the RC circuit can be boosted by 85% (20% peaking).
OnOn--Chip InductorsChip Inductors
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 43
Spiral InductorsSpiral Inductors
• These inductors are small (0.1-10 nH) and are used widely in RF circuits.
• Use top metal for high Q and high self resonance frequencies. Very good matching and accuracy.
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 44
MultiMulti--Layer InductorsLayer Inductors
• By taking advantage of multiple metal layers and mutual coupling, we can realize very large inductors (~ 100 nH).
Top view 3D view (not to scale)
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UC Berkeley EECS 240 Copyright © Prof. Ali M Niknejad
EECS 240EECS 240AAnalog Integrated Circuitsnalog Integrated Circuits
Lecture 3: Lecture 3: MOS Transistor MOS Transistor Models for Analog DesignModels for Analog Design
Ali M. Niknejad and Bernhard E. Ali M. Niknejad and Bernhard E. BoserBoser©© 20062006
Department of Electrical Engineering and Computer SciencesDepartment of Electrical Engineering and Computer Sciences
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UC Berkeley EECS 240 2 Copyright © Prof. Ali M Niknejad
OutlineOutline
MOSFET DC I/V ModelSquare law modelShort Channel EffectsBSIM models
MOSFET Small-Signal ModelTransconductanceOutput ResistanceCapacitances
MOSFET CV Model
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UC Berkeley EECS 240 3 Copyright © Prof. Ali M Niknejad
Why is modeling important?Why is modeling important?Analog circuits employ transistors in a continuous manner where the precise currents, voltages, and charges need to be correctly calculated. Digital circuits by contrast have a “margin” of error.Analog models are our window into the physical device and process. We like to do experiments with “SPICE”rather than pay for actual Si. This is too expensive, time consuming, and often difficult. MOS transistor models can be categorized as follows (T.R. Viswanathan)
Bush Model: A MOSFET is a switchClinton Model: A MOSFET is a current source and a switchKerry Model: A MOS transistor is described by the BSIM equations !
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UC Berkeley EECS 240 4 Copyright © Prof. Ali M Niknejad
Why not Square Law?Why not Square Law?
The square law model is well known and widely used but unfortunately grossly inappropriate for short channel transistorsFor one this model does not address the important transition region of operation, moderate inversion, between strong inversion and weak inversion.It’s good to review the assumptions behind this simple model in order to identify potential problems.
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UC Berkeley EECS 240 5 Copyright © Prof. Ali M Niknejad
Humble Origin of Square Law ModelHumble Origin of Square Law Model
Assume all current flow in transistor is due to drift (as opposed to diffusion). This implicitly assumes that we are in strong inversion.
Now assume uniform current flow at the surface (charge-sheet, quasi-static assumption) which implies that
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UC Berkeley EECS 240 6 Copyright © Prof. Ali M Niknejad
Gradual Channel ApproximationGradual Channel Approximation
Now we assumed (unstated) that in the MOS transistor the variation in the field is only in the x-direction. We have assumed that the vertical field does not affect the flowcarriers in the channel. This is the gradual channel approximation.In practice we know that the concentration of carriers is due to the vertical field. At the source we have
So in a position x in the channel
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UC Berkeley EECS 240 7 Copyright © Prof. Ali M Niknejad
Constant Mobility and ThresholdConstant Mobility and Threshold
To make life easy, let’s assume the threshold voltage VT(x)=VT is a constant.Also, assume that the mobility µ is a constant along the channel and independent of bias.
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UC Berkeley EECS 240 8 Copyright © Prof. Ali M Niknejad
Square Law SummarySquare Law Summary
We have derived the simple square law model under the following assumptions:
MOSFET is like a non-linear resistor with a continuous channel from source to drainVertical field determines charge densityLateral field determines drift currentNeglect diffusion currentsNeglect variation in threshold voltage along channelAssume the mobility is a constant as a function of lateral and vertical fieldsMore assumptions that are too complicated to mention !
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UC Berkeley EECS 240 9 Copyright © Prof. Ali M Niknejad
A Real Transistor !!!A Real Transistor !!!
Does this look like the “textbook” long-channel transistor?
Ultra-thin Gate DielectricDirect Tunneling Current
Quantum Effect
Pocket ImplantReverse short channel effect
Abnormal DIBL effectSlower output resistance scaling with L
(10x gds)
Gate ElectrodeGate DepletionQuantum Effect
Short Channel EffectsVelocity Saturation and Overshoot
Source-end Velocity LimitUnified Current Saturation
S/D EngineeringS/D resistances
S/D leakage
Retrograde DopingBody effect
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UC Berkeley EECS 240 10 Copyright © Prof. Ali M Niknejad
Doping / High Field EffectsDoping / High Field Effects
For deeply scaled devices, the dimensions are small enough such that ~1V exerts a considerable electric field (force) on the carriers. This results in velocity saturation and impact ionization. The surface effective mobility is also considerably lower and a function of the gate bias.The drain/channel region is a high field region where the usual 1D and quasi-2D approximations fail to predict the actual influence of the drain and body on the inversion layer.In order to provide adequate performance, the doping profile of a modern FET is complicated and leads to complicated geometry variations in the threshold voltage.The non-uniform doping also complicates the output resistance of the device.
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UC Berkeley EECS 240 11 Copyright © Prof. Ali M Niknejad
Saturation?Saturation?
Where does saturation come from?Well, we know that as we increase the drain voltage, eventually we will “pinch-off” the channel, in other words the density of carriers will be driven to zero (depletion) near the drain end of the transistor. This happens when
Now the drain cannot “communicate” with the channel and we expect the MOSFET behavior to be independent of the drain voltage. The current therefore will increase and “saturate” at a value of Vds = Vgs-VT.
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UC Berkeley EECS 240 12 Copyright © Prof. Ali M Niknejad
High Field RegionHigh Field Region
So any “extra” drain voltage drop, beyond Vdsat = Vgs-Vtmust be dropped across this depletion region. The growth and of this region with drain voltage gives rise to channel length modulation (output impedance).Since the drain depletion region is small, for large values of Vds the lateral electric field in this region can be quite large. Even though there are no mobile carriers in this region, the current flow in the MOSFET does not cease. The carriers in fact travel through this region at the velocity saturated speed vsat. Since vsat < ∞ there is a small finite density of free carriers in this region.
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UC Berkeley EECS 240 13 Copyright © Prof. Ali M Niknejad
Bulk ChargesBulk Charges
In our simple derivation, we assumed that the body charge (immobile) is fixed by the value at the source. In reality the background charge increases as we move towards the drain due to the reverse bias. This results in overestimation of the inversion charge and hence current.In reality we have an good expression for the body charge
The square root is inconvenient, as it results in 3/2 powers under integration. We need a better approximation (maybe linear) to give a simple saturation current expression.
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UC Berkeley EECS 240 14 Copyright © Prof. Ali M Niknejad
Approximation of Body ChargeApproximation of Body Charge
Previously we assumed that the constant line expression. A slightly more accurate expression is to assume a Taylor series expansion at the source. This gives us the more accurate equation. If we use this as a fitting parameter, we get the best model.
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UC Berkeley EECS 240 15 Copyright © Prof. Ali M Niknejad
Output ResistanceOutput Resistance
As noted the variation in the depletion region width at the pinch-off point modulates the channel length
If this effect is a small perturbation, we can assume that it responds linearly to the drain voltage, or
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UC Berkeley EECS 240 16 Copyright © Prof. Ali M Niknejad
Output Resistance MechanismsOutput Resistance Mechanisms
In reality all effects active simultaneouslyCLM only for relatively low fieldsDIBL dominates for high fieldsHot carrier impact ionization dominates for large Vds
Source: BSIM3v3 Manual
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UC Berkeley EECS 240 17 Copyright © Prof. Ali M Niknejad
CLM/DIBLCLM/DIBL
The Channel Length Modulation (CLM) model is derived by assuming a pseudo two-dimensional model for the potential in the drain regionDrain Induced Barrier Lowering (DIBL) accounts for the “drain” control of the channel. In an ideal transistor, only the front-gate controls the gate. In a real transistor, the channel potential depends additionally on the back-gate and the drain junction.Drain control is minimized by using long channel transistors, or by minimizing the drain junction depth.In practice, it’s convenient to assume that the threshold voltage varies linearly with the drain voltage.
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UC Berkeley EECS 240 18 Copyright © Prof. Ali M Niknejad
SCBESCBE
Substrate Current Body Effect (SCBE) accounts for energetic electrons (“hot” electrons) created near the drain region due to the high electric fields (> 0.1 MV/cm).These hot electrons have enough energy so that when they collide with the lattice they knock off electrons from the Si atoms (impact ionization). This creates electron/hole pairs leading to a substrate current Isubthat flows into the substrate from the drain terminal.
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UC Berkeley EECS 240 19 Copyright © Prof. Ali M Niknejad
Velocity SaturationVelocity Saturation
Initially drift velocity increases linearity with fieldFor high fields, the velocity saturatesFor some materials there is a peak (not Si), but saturated velocity is best for SiFor Si, this is modeled by the following equation:
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UC Berkeley EECS 240 20 Copyright © Prof. Ali M Niknejad
Effective MobilityEffective Mobility
Mobility is not constant along the channel. An effective mobility can be used to correct for this
The mobility varies as a function of the average vertical electric field
A strong electric field tends to push carriers close to the surface where enhanced scattering lowers mobility
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UC Berkeley EECS 240 21 Copyright © Prof. Ali M Niknejad
Low Field Mobility Low Field Mobility
It is observed that at low fields the mobility drops. The explanation is that the inversion layer “shields” the carriers from the background dopants. Thus there is considerable Coulomb scattering for low fields.
2 4 6 8 100
1x102
2x102
3x102
4x102
5x102
6x102
123K
173K
300K
Hol
e M
obilit
y(cm
2 /Vs)
Qinv(x1012/cm2)
data model model w/o C.S.
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UC Berkeley EECS 240 22 Copyright © Prof. Ali M Niknejad
Quantum EffectsQuantum Effects
The inversion charge profile is usually derived by solving Poisson’s equation. This results in the peak of the charge at the surface.If Schrödinger's equation is solved simultaneously, we find the charge density to peak away from the surface The position of the peak varies with applied gate bias.
Source: http://www.silvaco.com/products/vwf/atlas/quantum3d/quantum_br.html
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UC Berkeley EECS 240 23 Copyright © Prof. Ali M Niknejad
Quantum Quantum PolysiliconPolysilicon DepletionDepletion
Since the gate is not a perfect conductor, but also a semiconductor with doping NGATE, we observe a bias dependent depletion region Xp. This is in direct analogy with the surface charge position.The effective oxide thickness is thus larger than ToxThis reduces our gate drive even further.
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UC Berkeley EECS 240 24 Copyright © Prof. Ali M Niknejad
Quantum Effects in CVQuantum Effects in CV
The actual CV curve seen on the right shows drastically lower oxide capacitance due to the quantum confinement.The capacitance varies with bias in the real device.For large Tox, these effects are negligible, but for deeply scaled technology it is quite noticeable.
Source: R. Dutton and C.-H. Choi
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UC Berkeley EECS 240 25 Copyright © Prof. Ali M Niknejad
NonNon--Uniform DopingUniform Doping
The doping concentration in a modern FET has two important variations.The doping is non-uniform in the vertical direction due to “channel” threshold implant.The doping is non-uniform in the lateral direction, with higher concentration near the source drain (SDE). In addition, there is often a halo implant. Source: R. Dutton and C.-H. Choi
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UC Berkeley EECS 240 26 Copyright © Prof. Ali M Niknejad
SubSub--Threshold RegionThreshold Region
The square law model assumes that the current is zero until the threshold and then magically it starts increasing. Of course this is a fantasy. In reality the current flow is observed to increase exponentially for voltages near the threshold voltage. This is easy to explain if we view the MOSFET as a lateral BJT.
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UC Berkeley EECS 240 27 Copyright © Prof. Ali M Niknejad
““BJTBJT”” Weak Inversion ModelWeak Inversion Model
Assume that all the current is due to diffusion rather than drift. In other words, the potential along the channel varies negligibly but the carrier density varies linearly.Since the source-channel junction is reverse biased, it acts like a diode. By Boltzmann statistics we know that only a small fraction (the “tail”of the distribution) of carriers have sufficient energy to be injected from the source to the channel.Once in the channel, carriers will recombine or diffuse either into the drain (or into the substrate).If we increase the gate voltage, the channel potential follows almost linearly. This is only true in weak inversion because once we hit strong inversion, the channel potential is “pinned”.As the barrier to injection is lowered, an exponential increase in current flow is observed due to the Boltzmann distribution.
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UC Berkeley EECS 240 28 Copyright © Prof. Ali M Niknejad
Channel Potential in Weak InversionChannel Potential in Weak Inversion
There’s no explicit base terminal but the potential of the “base” is controlled indirectly through the capacitive divider formed by Cox and Cdep.
Using the capacitive divider, we see that
Note that n > 1 is the non-ideality factor of the channel control.
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UC Berkeley EECS 240 29 Copyright © Prof. Ali M Niknejad
Exponential Current FlowExponential Current Flow
We can now just borrow our equations from the BJT and write that
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UC Berkeley EECS 240 30 Copyright © Prof. Ali M Niknejad
Weak InversionWeak Inversion
Weak inversion (sub-threshold) like BJTn > 1: base controlled by capacitive divider
0.18µm CMOS: n ~ 1.5
“slow”:“large” CGS for “little” current drive (see later)
Moderate or weak inversion increasingly common:Low powerSubmicron L means “high speed” even in weak inversion
Poor matching:VTH mismatch amplified exponentiallyAvoid in mirrors
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UC Berkeley EECS 240 31 Copyright © Prof. Ali M Niknejad
Moderate InversionModerate Inversion
Weak inversion: current flow is predominately due to diffusionStrong inversion: current flow is predominately due to driftModerate inversion: both drift and diffusion contribute to the current. Closed form equations for this region don’t exist.
weak strong
mod
erat
ein
vers
ion
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UC Berkeley EECS 240 32 Copyright © Prof. Ali M Niknejad
Patching Models: Smoothing FunctionsPatching Models: Smoothing Functions
We have good models for weak inversion and strong inversion. Why not just interpolate in between?Here is an example interpolation model (EKV)
In strong inversion we have
In weak inversion we have
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UC Berkeley EECS 240 33 Copyright © Prof. Ali M Niknejad
BSIM ModelsBSIM Models
The Berkeley Short-channel IGFET Models (BSIMS) are the industry standard models for modern CMOS devices.They include many equations and parameters to model the complications in a real NFET or PFET device. A practical model card has 40-100 parameters and requires advanced software and extraction expertise to extract.BSIM3v3 is the model for this course. It’s widely available from most foundries.BSIM4 is an enhanced BSIM model that includes the holistic thermal noise model, substrate network, stress, and gate current.
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UC Berkeley EECS 240 34 Copyright © Prof. Ali M Niknejad
BSIM BSIM ““Hand CalculationHand Calculation”” ModelsModels
Requires many (many (many …)) assumptions.Assumptions:
VT is given Operate in strong-inversion.Mobility model of mobmod = 2 is used (also applicable to other mobmod with slightly lower accuracy)Bulk charge effect not significant in short channel devices.Channel length modulation is the main contribution to rout.
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UC Berkeley EECS 240 35 Copyright © Prof. Ali M Niknejad
Effects to be includedEffects to be included
Mobility degradation
Velocity saturation
Define:ox
d tUAu = mobility degradation coefficient
1V5.0 −≈du for tox=10nm
02UvE satC = critical E-field for velocity saturation
V/cm102 4×≈CE (typical value)
Define:
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UC Berkeley EECS 240 36 Copyright © Prof. Ali M Niknejad
Strong Inversion CurrentStrong Inversion Current
( ) ( )( )
−
++
−+−=
TGc
d
TGdTGDsat
VVLEu
VVuVVV11
1
( ) ( )
+−+
=
+−+
−−=
LEVVVu
I
LEVVVu
VVVVL
WCI
C
DTGd
longDlin
C
DTGd
DD
TGoxDlin
1
1
1
12 )(0
µ
( )( ) ( )
−
++
=
−
++
−=
TGC
d
longDsat
TGC
d
TGoxDsat
VVLEuI
VVLEu
VVL
WCI11
1112
)(
2
0µ
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UC Berkeley EECS 240 37 Copyright © Prof. Ali M Niknejad
Equations of DerivativesEquations of Derivatives
Required parameters
( ) ( )[ ]( ){ }( )[ ]( )
( ) ( )[ ]( ){ }( )[ ]TGdCLMlongDsat
TGTGdDsatD
TGTGdCLMox
TGTGdDsatDout
VVulPILVVVVuVVVVVVuWlPC
LVVVVuVVr
−+−−++−
=
−−+−−++−
=
11
112
)(
20
2
µ
joxxtl 3=with
( ) ( ) ( )
−
++
+−
=
+
−=
TGC
dTG
Dsat
longDsat
Dsat
TG
Dsatmsat
VVLEuVV
II
IVV
Ig11
111)(
W, L, TOX, U0, UA, VSAT, VTH0, PCLM, XJ
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UC Berkeley EECS 240 38 Copyright © Prof. Ali M Niknejad
Fitting ResultsFitting Results
0.00
1.00
2.00
3.00
4.00
5.00
6.00
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.0
Full BSIM3
Hand calculation
VG (V)
I D(m
A) VD=1.8V
VD=0.1V
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.0
I D(m
A)VD (V)
VG=2.0V
VG=1.0V
FullBSIM3
Hand calculation
Parameter detail: TSMC 0.18µm processtox: 4.1nm, W=10µm, VT0=0.39V
Comparison between full and simplified model
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UC Berkeley EECS 240 39 Copyright © Prof. Ali M Niknejad
Weakness of Model First DerivativesWeakness of Model First Derivatives
0.00
1.00
2.00
3.00
4.00
5.00
6.00
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VG (V)
g m(m
A/V
)
Full BSIM3
Hand calculation
VD=1.8V
VD=0.1V
linear region
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VD (V)
Rout(kΩ
)
Full BSIM3
Hand calculation
linear region
VG=2.0V
VG=1.0V
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UC Berkeley EECS 240 40 Copyright © Prof. Ali M Niknejad
““Hand ModelHand Model”” ConclusionConclusion
Not easy to do. Even “simple” model is not convenient.Output resistance is key in analog design (for gain) but this is very difficult to model.Missing important regions such as moderate inversion.Can do better with a smoothing function to include these regions of operation.In this class we’ll learn to rely on the simulator in conjunction with some pretty simple small-signal models to do design.
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UC Berkeley EECS 240 41 Copyright © Prof. Ali M Niknejad
Surface Potential ModelsSurface Potential Models
The BSIM family of models rely on “threshold” voltage to include many important short-channel effects.Due to source referencing, BSIM models suffer from an inherent asymmetry that leads to discontinuity about Vds=0.Bulk referenced models (such as EKV) solve this problem. Many “Next Generation” models use a surface potential formulation rather than threshold voltage.These models are more complicated an implicit by nature but have the advantage that they describe the long channel transistor behavior very well. In fact, many claim this is a “physical” model for this reason.MOS11, HiSIM, and SP (now PSP) are all examples of surface potential models.
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 1
EECS 240EECS 240AAnalog Integrated Circuitsnalog Integrated Circuits
Lecture 4: SmallLecture 4: Small--Signal Models for Signal Models for Analog DesignAnalog Design
Ali M. Niknejad and Bernhard E. Boser© 2006
Department of Electrical Engineering and Computer Sciences
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 2
MOSFET Models for DesignMOSFET Models for Design• SPICE (BSIM)
– For verification– Device variations
• Hand analysis– Square law model– Small-signal model
• Challenge– Complexity / accuracy tradeoff– How can we accurately design when large signal models
suitable for hand analysis are off by 50% and more?
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 3
Device VariationsDevice Variations• Run-to-run parameter variations:
– E.g. implant doses, layer thickness– Affect VTH, µ, Cox, R , …– How model in SPICE?
• Nominal / slow / fast parameters– E.g. fast: low VTH, high µ, high Cox, low R– Combine with supply extremes– Pessimistic but numerically tractable
improves chances for working Silicon
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 4
Threshold Voltage VThreshold Voltage VTHTH• Strong function of L• Use long channel for VTH
matching
• Process variations– Run-to-run– How characterize?– Slow/nominal/fast– Both worst-case &
optimistic
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 5
VVTHTH Design ConsiderationsDesign Considerations• Approximate Values (L = 0.5µm)
VTHN = 600mV γn=0.5 rt-VVTHP = -700mV γp=0.4 rt-V
• Back-Gate Bias
e.g. VSB = 400mV ∆VTHN = 110mV• Variations:
– Run-to-run: +/- 50mV (very process dependent)– Device-to-device: σ = 2mV (L > 1µm, common-centroid)– Use insensitive designs
• diff pairs, current mirrors• value of VTH unimportant (if < VDD)
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 6
Device Parameters for DesignDevice Parameters for Design
• Region: moderate or strong inversion / saturation– Most common region of operation in analog circuits– XTR behaves like transconductor: voltage controlled
current source• Key design parameters
– Large signal• Current ID power dissipation• Minimum VDS available signal swing
– Small signal• Transconductance gm speed / voltage gain• Capacitances CGS, CGD, … speed• Output impedance ro voltage gain
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 7
Low Frequency ModelLow Frequency Model• A Taylor series expansion of small signal current gives
(neglect higher order derivatives)
• Square law model:
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 8
TransconductanceTransconductance• Using the square law model we have three equivalent
forms for gm in saturation
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 9
Weak Weak InvesionInvesion ggmm• In weak inversion we have bipolar behavior
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 10
TransconductanceTransconductance
weakinversion
strong inversion
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 11
TransconductanceTransconductance (cont)(cont)• The transconductance increases linearly with Vgs – VT but
only as the square root of Ids. Compare this to a BJT that has transconductance proportional to current.
• In fact, we have very similar forms for gm
• Since Vdsat >> Vt, the BJT has larger transconductance for equal current.
• Why can’t we make Vdsat ~ Vt ?
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 12
SubthresholdSubthreshold AgainAgain……
• In fact, we can make Vgs – Vt very small and operate in the sub-threshold region. Then the transconductance is the same as a BJT (except the non-ideality n factor).
• But as we shall see, the transistor fT drops dramatically if we operate in this region. Thus we typically prefer moderate or strong inversion for high-speed applications.
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 13
µµCCoxox • Square law:
• Extracted values strong function of ID
– Low IDweak inversion
– Large IDmobility reduction
• Do not use µCox for design!
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 14
TransconductorTransconductor EfficiencyEfficiency
• A good metric for a transistor is the transconductancenormalized to the DC current. Since the power dissipation is determined by and large by the DC current, we’d like to get the most “bang” for the “buck”.
• From this perspective, the weak and moderate inversion region is the optimal place to operate.
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 15
Efficiency gEfficiency gmm/I/IDD• High efficiency is
good for low power
• Higher gm/ID at low VGS
• Approaches BJT for VGS < VTH
gm/IC = 1/Vt ~ 40 V-1
• NMOS / PMOS about same
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 16
Efficiency gEfficiency gmm/I/IDD• Let’s define
e.g. V* = 200mV gm/ID = 10 V-1
• Square-law devices: V* = VGS-VTH = Vdsat
*22 :law SquareVI
VVIg D
THGS
Dm =−=
*2 2*
VIg
gIV
D
m
m
D =⇔=
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 17
SPICE Charge ModelSPICE Charge Model• Charge conservation
• MOSFET:– 4 terminals: S, G, D, B– 4 charges: QS + QG + QD + QB = 0 (3 free variables)– 3 independent voltages: VGS, VDS, VSB– 9 derivatives: Cij = dQi / dVj, e.g. CG,GS ~ CGS– Cij != Cji
Ref: HSPICE manual, “Introduction to Transcapacitance”, pp. 15:42, Metasoft, 1996.
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 18
Small Signal CapacitancesSmall Signal Capacitances
CjDBCjDB + CCB/2CjDBCDB
CjsB + 2/3 CCBCjsB + CCB/2CjSBCSB
00CGC // CCBCGB
ColCGC/2 + ColColCGD
2/3 CGC + ColCGC/2 + ColColCGS
Strong inversionsaturation
Strong inversionlinear
Weak inversion
WLx
C
WLCC
d
SiCB
oxGC
ε=
=
mfF/ 48.0mfF/ 24.0
mfF/ 3.5 2
µµ
µ
===
olP
olN
ox
CCC
0.35u Process
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 19
MOS Capacitance ExampleMOS Capacitance Example
fF24fF265µmfF3.5
5.0100
22
==
==
==
=
WCCWLCCt
C
LW
olNol
oxgc
ox
SiOoox
εε
fF157
fF157:triode
21
21
=+=
=+=
olgcgd
olgcgs
CCC
CCC
fF24fF24
:ldsubthresho
==
==
olgd
olgs
CCCC
fF24fF201
:saturation
32
==
=+=
olgd
olgcgs
CCCCC
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 20
LayoutLayout
HSPICE geo = 0 (default)
HSPICE geo = 3
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 21
Extrinsic MOS CapacitancesExtrinsic MOS Capacitances• Source/drain diffusion junction capacitance:
• Example: W/L = 100/0.5, VSB = VDB = 0V, Ldiff = 1µm
( ) ( )
bisube
Sij
j
Sibc
m
b
jswjswm
b
jj
Nqx
xC
VV
CVC
VV
CVC
Φ==
+
≅
+
≅
00
0
00
00
2 with
1
and
1
εεεε39.0
V51.0µmfF49.0
µmfF85.0
20
20
==
=
=
n
bn
jswn
jn
mV
C
C
48.0V93.0µmfF48.0
µmfF1.1
20
20
==
=
=
n
bn
jswn
jn
mV
C
C
AS = AD = 100µm2, PS = PD = 102µmCjn = 85fF Cjswn = 50fF Cbc = 58fF
Strong Inversion –Saturation: Csb = 173fF Cdb = 135fFLinear region: Csb = 164fF Cdb = 164fF
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 22
High Frequency Figures of MeritHigh Frequency Figures of Merit• Unity current-gain bandwidth
• This is related to the channel transit time:• For degenerate short channel device
(Long channel model)
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 23
Efficiency gEfficiency gmm/I/ID D versus versus ffTT
Speed-Efficiency Tradeoff
NMOS faster than PMOS
0.35u Process
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 24
Weak Inversion Frequency Weak Inversion Frequency ResponseResponse
• The gate capacitance in weak inversion is given by
• IM is the maximum achievable current in weak inversion so the factor ( ) < 1
Ref: Tsividis, Operation and Modeling of the MOS Transistor
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 25
Device ScalingDevice Scaling
0
10
20
30
40
50
60
-0.1 0.0 0.1 0.2 0.3 0.4 0.5VGS-VTH [V]
f T [G
Hz]
0.18µm
0.25µm
0.35µm
0.5µm
Short channel devices are significantly faster!
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 26
Device FigureDevice Figure--ofof--MeritMerit
Peak performance for low VGS-VTH (V*)
0
50
100
150
200
250
300
350
400
-0.1 0.0 0.1 0.2 0.3 0.4 0.5
VGS-VTH [V]
f T⋅g
m/I D
[GH
z/V]
0.18µm
0.25µm
0.35µm
0.5µm
-
EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 27
Output Resistance Output Resistance rroo
Hopeless to model this with a simple equation(e.g. gds = λ ID)
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 28
OpenOpen--loop Gain aloop Gain av0v0
• More useful than ro• Represents maximum attainable gain
from a transistor
• Simulation Notes:• Use feedback to bias Vds = Vgs• Use relatively small gain (100) for• Fast DC conversgence
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 29
Gain, aGain, av0v0 = g= gmm rroo
• Strong tradeoff:av0 versus VDS range
• Create such plots for several device length’for design reference
L = 0.18µm
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 30
Long Channel GainLong Channel Gain
L av0
like long channel device
L = 0.35µm
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 31
Technology TrendTechnology Trend
0
10
20
30
40
50
60
70
80
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VDS [V]
g m⋅r o
0.18µm
0.25µm
0.35µm
0.5µm
Short channel devices suffer from reduced per transistor gain
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 32
Transistor Gain DetailTransistor Gain Detail
For practical VDS the effect the “short-channel” gain penalty is less severe(remember: worst case VDS is what matters!)
0
5
10
15
20
25
30
35
40
45
0.0 0.1 0.2 0.3 0.4
VDS [V]
gm⋅r
o
0.18µm
0.25µm
0.35µm
0.5µm
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 33
Saturation Voltage Saturation Voltage vsvs V*V*• Saturation voltage
– Minimum VDS for “high” output resistance– Poorly defined: transition is smooth in practical devices
• “Long channel” (square law) devices:– VGS – VTH = Vdsat = Vov = V*– Significance:
• Channel pinch-off• ID ~ V*2• Boundary between triode and saturation• ro “large” for VDS > V*• CGS, CGD change• V* = 2 ID / gm
• “Short channel” devices:– All interpretations of V* are approximations– Except V* = 2 ID / gm (but V* ≠ Vdsat)
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 34
Design ExampleDesign ExampleExample: Common-source amp av0 > 70, fu = 100MHz for CL = 5pF
• av0 > 70 L =0.35µm
•
• High fT (small CGS): V* = 200mV
•
mS14.32 =≈ Lum Cfg π
µA3142
*==
VgI mD
-
EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 35
Device SizingDevice Sizing
• Pick L 0.35µm• Pick V* 200mV• Determine gm 3.14mS
• ID = 0.5 gm V* 314µA
• W from graph (generate with SPICE)
W = 10µm (314µA /141µA)= 22µm
• Create such graphs for several device lengths for design reference
141uA
NMOS
-
EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 36
Common Source SimsCommon Source Sims
• Amplifier gain > 70 • Amplifier unity gain frequency is “dead on”• Output range limited to 0.6 V – 1.5 V to maintain gain
(about 0.45V swing)
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 37
Small Signal Design SummarySmall Signal Design Summary• Determine gm (from design objectives)
• Pick L– Short channel high fT– Long channel high ro, av0
• Pick V* = 2ID/gm– Since V* is approximately the saturation voltage– Small V* large signal swing– High V* high fT– Also affects noise (see later)
• Determine ID (from gm and V*)
• Determine W (SPICE / plot)
• Accurate for short channel devices key for design
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 38
Device Sizing ChartDevice Sizing Chart
Generate these curves for a variety of L’s and device flavors (NMOS, PMOS, thin oxide, thick oxide, different VT)
-
EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 39
Device Parameter SummaryDevice Parameter Summary
• Obtain from L, ID• Self loading (CGS, CDB, …)
W
• Cutoff frequency, fT phase margin, noise• Intrinsic transistor gain (av0)
L
• Current efficiency, gm/ID• Power dissipation (ID)• Speed (gm)• Cutoff frequency, fT phase margin, noise• Headroom, VDS,min
V*
Circuit ImplicationsDevice Parameter
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 1
EECS 240EECS 240AAnalog Integrated Circuitsnalog Integrated Circuits
Lecture 5: Electronic NoiseLecture 5: Electronic Noise
Ali M. Niknejad and Bernhard E. Boser© 2006
Department of Electrical Engineering and Computer Sciences
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 2
Electronic NoiseElectronic Noise• Why is this important?
• Signal-to-noise ratio– Signal Power Psig ~ (VDD)2– Noise Power Pnoise ~ kBT/C– SNR = Psig / Pnoise
• Technology Scaling– VDD goes down SNR down– Or C up Power up
• Low Power means understanding noise
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 3
Types of Types of ““NoiseNoise””• Interference (“human” made, not “fundamental”)
– Signal coupling• Capacitive• Inductive• Substrate• bond wires
– Supply noiseSolutions:
Fully differential circuitsLayout techniques
• Device noise – Caused by discreteness of charge– “fundamental” – thermal noise– “manufacturing process related” – flicker noise
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 4
Noise in AmplifiersNoise in Amplifiers
• All electronic amplifiers generate noise. This noise originates from the random thermal motion of carriers and the discreteness of charge.
• Noise signals are random and must be treated by statistical means. Even though we cannot predict the actual noise waveform, we can predict the statistics such as the mean (average) and variance.
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 5
Thermal Noise of a ResistorThermal Noise of a Resistor• Origin: Brownian Motion
– Thermally agitated particles– E.g. ink in water, electrons in a conductor
• Random use statistics to describe
• Available noise power:
– Noise power in bandwidth B delivered to a matched load– Example: B = 1Hz PN = 4 x 10-21W = -174 dBm– Reference: J.B. Johnson, “Thermal Agitation of Electricity in
conductors,” Phys. Rev., pp. 97-109, July 1928.
TBkP BN =
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 6
Resistor Noise ModelResistor Noise Model
R
Rvn
Noisy resistormodel
PN
RvTBkP nBN 4
2
==
TRBkv Bn 42 =
Mean square noise voltage:
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 7
Thermal NoiseThermal Noise• Present in all dissipative elements (resistors)• Independent of DC current flow• Random fluctuations of v(t) or i(t)
– Instantaneous noise is unpredictable– Result of many random, superimposed collisions– Relaxation time constant τ ~ 0.17ps– Consequences:
• Zero mean• Gaussian amplitude distribution (pdf)• Power spectral density “white” up to about 1/τ = 2π x 1000 GHz
– kBT = 4 x 10-21 J (T = 290K = 16.9oC)
• Example:R = 1kΩ, B = 1MHz 4µV rms or 4nA rms or 4nV/rt-Hz
RTBki
TRBkv
Bn
Bn
44
2
2
=
=
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 8
Noise of Passive NetworksNoise of Passive Networks• Capacitors, Inductors
• Noise calculations– Instantaneous voltages add– Power spectral densities add– RMS voltages do NOT add
• Example: R1+R2 in series
• Generalization to arbitrary RLC networks
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 9
Noise in DiodesNoise in Diodes• Shot noise
– Zero mean– Gaussian pdf– Power spectral density– Proportional to current– Independent of temperature
• Example: ID = 1mA, B = 1MHz 17nA rms
• Shot noise versus thermal noise (rd = Vt/ID)Thermal equilibrium
fqIi Dn ∆= 22
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 10
BJT NoiseBJT Noise
fqIi
ffIKfqIi
fTrkv
Cc
BBb
bBb
∆=
∆+∆=
∆=
2
2
4
2
12
2
α
• The collector and base shot noise are partially correlated.• The base resistance contributes thermal noise.• Note that ro does not contribute noise. It’s not a physical
resistor.
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 11
FET NoiseFET Noise• In addition to the extrinsic physical resistances in
a FET (rg, rs, rd), the channel resistance also contributes thermal noise.
• The channel conductance is calculated by
• The noise injection is a distributed process. The net sum of the noise injection gives (note γ)
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 12
More Fundamental ExpressionMore Fundamental Expression
• A more fundamental equation is derived [Tsividis] results in the above equation
• In nonsaturation with Vds = 0, the device is a resistor so the thermal noise is given by
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 13
• In saturation, the drain current is given by
• For a long channel model, you can substitute gm for the above factor. In practice the form involving inversion charge is more accurate and used by SPICE/BSIM.
Strong Inversion NoiseStrong Inversion Noise
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 14
Weak InversionWeak Inversion
• The origin of noise in weak inversion is shot noise. So the result should be ~ 2qIDS.
• But using the expression for inversion charge in weak inversion we get the same result! (similar to a diode)
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 15
Thermal Noise for Short ChannelsThermal Noise for Short Channels• Thermal noise (strong inversion)
– Drain current (use gds0 not gm)γ = 2/3 for small fields (long L)can be 1-2 or even larger for short L
• Since the expression with gm is convenient for input referred noise calculations, it is often used. The expression with gds0 is more accurate and should be used. The factor α captures the drop in gm for a short channel device.
• Gate induced noise (142/242 topic)• Gate current (leakage shot noise)• No noise from ro (not physical resistor)• Extrinsic noise sources (drain/source/gate resistance)
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 16
FET Noise ModelFET Noise Model
• The resistance of the substrate also generates thermal noise. In most circuits we will be concerned with the noise due to the channel and the input gate noise due to Rg
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 17
1/f Noise1/f Noise• Flicker noise
– Kf,NMOS = 2.0 x 10-29 AFKf,PMOS = 3.5 x 10-30 AF
– Strongly process dependent (also model)• Example: ID = 10µA, L = 1µm,
– Cox = 5.3fF/µm2, fhi = 1MHz
flo = 1Hz 722pA rmsflo = 1/year 1082pA rms
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 18
1/f Noise Corner Frequency1/f Noise Corner Frequency• Definition (MOS)
• Example:– V* = 200mV, γ = 1
NMOS PMOSL = 0.35µm 192kHz 34kHzL = 1.00µm 24kHz 4kHz
2
*
2
2
2
8
114
41
4
LV
CTkK
LCTkK
gTkCLIK
f
fgTkff
CLIK
oxrB
f
Ig
oxrB
f
mrBox
Dfco
mrBcoox
Df
Dm
γ
γ
γ
γ
=
=
=
∆=∆
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 19
SPICE Noise AnalysisSPICE Noise Analysis
Slope …
100/1
1000/10
50/2
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 20
Noise CalculationsNoise Calculations• Output spectral noise density• Method:
1) Small-signal model2) All inputs = 0 (linear superposition)3) Pick output vo or io4) For each noise source vx, ix
Calculate Hx(s) = vo(s) / vx(s) (… io, ix)5) Total noise at output is
• Tedious but simple …
( ) ( )∑ ==x
xjfsxTonfvsHfv 22
22
, )( π( ) ( )fSfv nTon =2 , :notationsimpler
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 21
Example: Common SourceExample: Common Source
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 22
Simulation ResultSimulation Result
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 1
EECS 240EECS 240AAnalog Integrated Circuitsnalog Integrated Circuits
Lecture 6: Noise AnalysisLecture 6: Noise Analysis
Ali M. Niknejad and Bernhard E. Boser© 2006
Department of Electrical Engineering and Computer Sciences
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 2
Input Equivalent NoiseInput Equivalent Noise
• Two-port representation• Fictitious noise sources• Effect of source resistance• Correlation
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 3
Equivalent Noise GeneratorsEquivalent Noise Generators
• Any noisy two port can be replaced with a noiseless two-port and equivalent input noise sources
• In general, these noise sources are correlated. For now let’s neglect the correlation.
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 4
Finding the Equivalent GeneratorsFinding the Equivalent Generators
• The equivalent sources are found by opening and shorting the input and equating the noise.
• For a shorted input, the input current flows through the short and the output is due only to the input noise.
• For an open input, the dangling voltage does not contribute to the output noise.
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 5
Role of Source ResistanceRole of Source Resistance
• If Rs = 0, only the voltage noise vn is important. Likewise, if Rs = ∞, only the current noise in is important.
• Amplifier Selection: If Rs is large, then select an amp with low in (MOS). If Rs is low, pick an amp with low vn (BJT).
• For a given Rs, there is an optimal vn/in ratio.• Alternatively, for a given amp, there is an optimal Rs.
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 6
Total Output NoiseTotal Output Noise
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 7
New Equivalent GeneratorNew Equivalent Generator
• We see that the total noise can be lumped into one equivalent voltage once Rs is known.
• Be careful! Up to now we ignored the correlation.
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 8
Optimum Source ImpedanceOptimum Source Impedance
• For a given two-port (amplifier), what’s the optimum source impedance? Find the total output noise and find the minima for Rs to find Ropt.
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 9
Correlated Noise SourcesCorrelated Noise Sources• Let’s partition the input noise current into two
components, a component correlated (“parallel”) to the noise voltage and a component uncorrelated (“perpendicular”) of the noise voltage
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 10
Equivalent Noise Voltage (Equivalent Noise Voltage (corcor))
• Since the above expression is the sum of two uncorrelated noise voltages, we have
• Now we can continue as before to find
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 11
Noise and FeedbackNoise and Feedback• Ideal feedback:
– No increase of input referred noise– No decrease of SNR at output
• Practical feedback: increased noise– Noise from feedback network– Noise gain from elements outside feedback loop
• System level: feedback can mitigate noise problems– E.g. under-damped accelerometer
Ref: M. Lemkin and B. E. Boser, “A Three-Axis Micromachined Accelerometer with a CMOS Position-Sense Interface and Digital Offset-Trim Electronics,” IEEE J. Solid-State Circuits, vol. SC-34, pp. 456-468, April 1999.
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 12
Ideal FeedbackIdeal Feedback
Order of summation irrelevant:
Circuits are identical
Σ -a
f
Vi Vovn
Σ -a
f
Vi Vovn
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 13
Ideal Feedback and NoiseIdeal Feedback and Noise
• It’s clear that the ideal feedback network does not alter the noise of the system. Real feedback elements, though, have noise.
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 14
Example: Shunt FeedbackExample: Shunt Feedback• Shunt feedback samples the output
voltage and subtracts from the input current. It’s thus most effective in a trans-resistance amplifier configuration.
• The action of the feedback is to lower the input and output impedance. In a typical implementation, the resistor RFadds thermal noise to the input.
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 15
Shunt FB AnalysisShunt FB Analysis
• To find the equiv input noise voltage, we short the input (and thus the noise current).
• The output noise is clearly given by the two-port voltage gain squared. Even though we don’t think of this as a voltage amplifier, we can still use the trans-resistance gain since iin = vin/Zin
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 16
Shunt FB Equiv Voltage NoiseShunt FB Equiv Voltage Noise
• The voltage gain does not change with feedback since we are voltage driving the circuit.
• Since the input current is independent of the feedback noise current, it does not alter the output noise.
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 17
Shunt FB Equiv Noise CurrentShunt FB Equiv Noise Current
• If we leave the input terminal open-circuited, then the input voltage noise for the equiv circuit is disabled. For the real circuit, though, the input noise is active through RF.
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 18
Shunt Noise CurrentShunt Noise Current• Suppose the closed-loop gain of the circuit is
given by Zcl ≈ RF. Then we have
• For the full circuit, let α represent the input current division between the two-port and the feedback network. If the two-port output imepdance is small, we have α =Zin/(Zin + RF) ≈ 1
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 19
Shunt Current (cont)Shunt Current (cont)
• The first two terms are pretty obvious. The last term requires a small calculation as shown below
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 20
SeriesSeries--Shunt FeedbackShunt Feedback
• In a feedback voltage amplifier, open-circuit the input to find the equivalent input noise. It’s clear from the above figure that
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 21
SeriesSeries--Shunt Shorted InputShunt Shorted Input
• Assuming high/low input/output impedance, the current in develops a voltage across RE||RF.
• The noise voltages due to RE and RF generate an input that is readily calculated by voltage division.
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 22
SeriesSeries--Shunt Noise VoltageShunt Noise Voltage
• We compute the transfer function from each noise source to the output using superposition. Let Acl represent the closed-loop voltage gain
• The above can be simplified to
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 23
SeriesSeries--Shunt Voltage (cont)Shunt Voltage (cont)• Since the same closed-loop gain is used for the
equivalent noise generator, we have
• If the loop gain and closed-loop gain is large, we have
• Which means that the noise of RE dominates.
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 24
Feedback SummaryFeedback Summary
• For quick approximations, simply consider the loading effect of the feedback network on the input and associate a noise to this element.
• For shunt-shunt feedback, the loading at the input is RF. Since the input is a current, represent this as an input noise current.
• For series-shunt feedback, the loading is RF||RE(short the output). Since the input is a voltage, we associate a noise voltage with this element.
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 25
Example: NonExample: Non--Inverting AmpInverting AmpExample:
• Decreasing Ro reduces noise but increases feedback current
a = inf
R1
R2
in1
in2
vnVi
Vo
vx = vi - vn
( )
( )
434212
4
1
2
2
21
2122
21
22
1212
1
212
1
nfbv
oBn
nnnieq
nnx
xnnx
o
fTRkv
RRRRiivv
RiiRRv
viiRvRv
∆+≅
+
++=
−−
+=
+
+−=
( )
22
0
2
01
HznV40
10100kΩ
1
=
∆
===
−=
fv
ARR
ARR
nfb
v
o
vo
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 26
Example: Inverting AmplifierExample: Inverting Amplifier
inf
R2
R1vn
ViVo
{
2
0
2
2
2
212
2
2
1
1
2122
1
21
1
2
11
0
+=
+=
+=
++−=
−
vn
n
nieq
n
A
io
Av
RRRv
RR
RRRvv
RRRv
RRvv
v
Example:
11 :1.0
1.1 :10
2 :1
2
2
0
2
2
0
2
2
0
=−=
=−=
=−=
n
ieqv
n
ieqv
n
ieqv
v
vA
v
vA
v
vA
Noise from R1, R2 ignored.
Note: R1 is outside feedback loop signal and noise have different gains to output.
22nieq vv ≠
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 27
Example: MOS S&HExample: MOS S&H• Sampling noise:
• Noise bandwidth:
( )
( )
CTk
dffvv
sRCTRkfv
B
onoT
Bon
=
=
+=
∫∞
0
22
22
114
RCff
RCB
CTkTRBk
oo
BB
ππ
21 ith w
241
4
===
=
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 28
Sampling NoiseSampling Noise
• “kT/C” noise• Application: ADC, SC circuits, …• Aliasing• Variance of noise sample• Spectral density of sampled noise
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 29
SPICE VerificationSPICE Verification
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 30
Useful IntegralsUseful Integrals
41
41
1
411
2
02
2
2
02
2
2
0
Qdfs
Qs
s
Qdfs
Qs
df
o
oo
o
o
oo
oso
ω
ωω
ω
ω
ωω
ω
ω
=++
=++
=+
∫
∫
∫
∞
∞
∞
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 31
Example 4: CS AmplifierExample 4: CS Amplifier
( )
FL
B
voL
B
LmL
B
LLLm
LB
LLLm
LBoT
LL
Lm
LBon
nC
Tk
AC
Tk
RgC
Tk
CRRg
RTk
dfCsR
RgR
Tkv
CsRRg
RTkfv
=
+=
+=
+=
+
+=
+
+=
∫∞
321
321
41
3214
11
3214
13214
2
0
222
22
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 32
SPICE CircuitSPICE Circuit
rms 98164
1
221100
10
34
322
1
VV
AC
Tkv
AkRmSg
AI
VIg
voL
BoT
vo
L
m
D
D
m
µ
µ
µ
=
+×=
+=
−=Ω=
==
= −
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 33
SPICE ResultSPICE Result
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 34
SignalSignal--ToTo--Noise RatioNoise Ratio• SNR
• Signal Powersinusoidal source
• Noise Powerassuming thermal noise dominates
• SNR = f(C)
noise
sig
PP
SNR =
221
peakzerosig VP −=
fB
noise nCTkP =
25.0 VPsig =
( )264 VPnoise µ=
( )dBSNR 9.8010122
645.0 6
2 =×== µ
4 ×↑C dBSNR 6 +↑
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 35
dB versus BitsdB versus Bits• Quantization “noise”
– Quantizer step size:– Box-car pdf– Variance:
• SNR of N-Bit sinusoidal signal– Signal power
– SNR
– 6.02 dB per Bit
12
2∆=QS
∆
2
22
21
∆= NsigP
[ ] dB 02.676.1
25.1 2
NSP
SNR NQ
sig
+=
×==14624
9816
508
dBN
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EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 36
SNR versus PowerSNR versus Power• 1 Bit 6dB 4x SNR• 4x SNR 4x C• Circuit bandwidth ~gm/C 4x gm• Keeping V* constant 4x ID, 4x W
• Thermal noise limited circuit:Each additional Bit QUADRUPLES power dissipation.E.g. 15 Bit noise-limited ADC dissipates 100mW
16 Bit redesign dissipates 400mW !
• Overdesign is very costly. We need design procedures that get us very close to the specifications.
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 37
Analog Circuit Dynamic RangeAnalog Circuit Dynamic Range• The biggest signal we can ever expect at the output of a circuit is
limited by the supply voltage, VDD. Hence (for sinusoids)
• The noise is
• So the dynamic range in dB is:
221)(max DD
VrmsV =
CTknrmsV Bfn =)(
[pF] in C with[dB] 7520log
[V/V] 8)(
)(
10
max
+
=
==
fDD
Bf
DD
n
nCV
TknCV
rmsVrmsVDR
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 38
Analog Circuit Dynamic RangeAnalog Circuit Dynamic Range• For integrated circuits built in modern CMOS processes, VDD < 3V and C
< 1nF (nf = 1)
– DR < 110dB (18 Bits)
• For PC board circuits built with “old-fashioned” 30V opamps and discrete capacitors of < 100nF
– DR < 140dB (23 Bits)– A 30dB (5 Bit) advantage!
• Note: oversampling ADCs break this barrier (cost: speed penalty)
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 39
““BigBig”” Noise ExampleNoise Example
• Cascoded common-source stage: what are the noise contributions from M1, M2?
• Simplified model for conclusive results:
– Lump parasitic capacitors– Feedback sets gain,
neglect roM1
M2
Cx CL
Vo
Vx
VBias
ViVG
CP
CF
CS
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 40
Example (cont.)Example (cont.)
M1
M2
Cx CL
Vo
Vx
VBias
ViVG
CP
CF
CS
( )
PSF
F
ogg
nnxmgmxxx
nxmgFoFLo
CCCCF
FvvviivgvgvsCv
ivgvsCvCCsv
++=
=
=−+++
=+−−+
with
:0 :
0 :
2121
22
Calculate noise transfer functions to amplifier output:
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 41
Example (cont.)Example (cont.)
M1
M2
Cx CL
Vo
Vx
VBias
ViVG
CP
CF
CS
( )
x
mp
FL
m
Leff
mu
uo
puo
oo
pnn
mo
Cg
FCCgF
CgF
Q
sQ
ssii
Fgv
2
11
2
2
2211
1
with
1
11
=
−+==
=
=
++
+−=
ω
ω
ωω
ωωω
ωωω
After some algebra …
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 42
Example (cont.)Example (cont.)
M1
M2
Cx CL
Vo
Vx
VBias
ViVG
CP
CF
CS
{
2
2
2
2
2
1
2
112
2
1
114
ooM
pm
m
Mm
bon
sQ
ss
gg
gFTk
fv
ωωω ++
+=∆
43421
Spectral noise density at amplifier output:
• Noise from M2:• Circular current at low frequency does
not reach amplifier output• At high frequency Cx short
• Cascode contributes little noise at low frequency
• At high frequency the noise contribution can be significant
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 43
Example (cont.)Example (cont.)
M1
M2
Cx CL
Vo
Vx
VBias
ViVG
CP
CF
CS
( ){
{{
+=
+=
+=
++
+=∆
=
=
∞∞
∫∫
2
1
1
2
2
1
2
12
2
22
2
2
2
21
2
1012
0
2
1
1
14
4
1
114
M
Leff
x
MLeff
b
p
u
m
m
Leff
b
p
o
m
mo
m
b
jfsooM
jfspm
m
Mm
bon
CFC
FCTk
gg
FCTk
ggQ
gFTk
sQ
ss
ggdf
gFTkdf
ffv
γ
ωωγ
ωωωγ
ωωω
γ
π
π4434421
Total noise at amplifier output:
• Total noise depends only on C!• M1 always contributes noise• Significant noise from M2 for “large” Cx
make Cx small (compared to CLeff)
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 44
Design ExampleDesign Example• Track & Hold amplifier for 16-Bit ADC (B=16)• fs = 100MHz ωu ~ 2π fsN
N = ln(2B) … based on settling, see later• Amplifier based on cascoded common-source, Av = -1• Choose
– L = 0.35µm– M1 and M2 same size (not necessarily ideal)– CF = CS = CGS (reasonable tradeoff)
F = 1/3– Maximum signal amplitude Vs (peak-to-peak)
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 45
Design EquationsDesign Equations
( )
( )
1
32
1
B
2
2
2*
2lnN 2
1
221
2
m
D
oxGS
Leff
m
su
Leff
GSx
Leff
s
B
gIV
WLCC
CgF
Nf
CCC
FCkT
V
DR
=
=
=
≅=
≈+
=
=
πωsolve
FCNfg
VTk
FC
Lsm
s
rBB
L
π2
28
1
2
2
≅
×≅
-
EECS 240 Lecture 5: Noise © 2006 A. M. Niknejad and B. Boser 46
Design ExamplesDesign Examples
13.4pF0.84pFCGS
10800µm675µmW
167mA10mAID
1300mS81mSgm
413pF26pFCL
0.1µm/µA0.1µm/µAW/ID
200mV200mVV*
1V1VVs
100MHz100MHzfs
1614B
16-Bit T&H14-Bit T&HParameter
-
EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 1
EECS 240EECS 240AAnalog Integrated Circuitsnalog Integrated Circuits
Lecture 7: Current SourcesLecture 7: Current Sources
Ali M. Niknejad and Bernhard E. Boser© 2006
Department of Electrical Engineering and Computer Sciences
-
EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 2
Bias Current SourcesBias Current Sources
• Applications• Design objectives
– Output resistance (& capacitance)– Voltage range (Vmin)– Accuracy– Noise
• Cascoding• High-Swing Biasing
-
EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 3
Current MirrorCurrent Mirror• Bias• Noise• Cascoding
-
EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 4
NoiseNoise
• M2 (and Iref!) can add noise– Choose small M (power penalty), or– Filter at gate of M1
• Current source FOMs– Output resistance Ro– Noise resistance RN– Active sources boost Ro, not RN
( )( )
oov
o
mN
NB
mB
mmB
ddon
rRMa
r
MgR
fR
Tk
fMgTkfgMgTk
iMii
=
-
EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 5
VVminmin versus Noiseversus Noise
MKIV
MgR
kVkV
D
mN
+=
+=
=×=
−
−
12
11
2...1 typ.*
1min
1
1
min
γ
γ
• Voltage required for large Ro (saturation): Vmin ~ V* (based on intuition from square-law model)
• Minimizing noise (for given ID):large RNlarge Vmin (k >> 1)
• At odds with signal swing(to maximize the dynamic range)
-
EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 6
BipolarBipolar’’ss, , GaAsGaAs, , ……
• BJT and RE contribute noise• Increasing RE lowers overall noise• BJT and MOS exhibit essentially same
noise / Vmin tradeoff• Lowest possible noise source is a
resistor (and large Vmin, VDD)
Q1Q2
RERE
io
Iref
Cbig
fRg
RgiRg
iiEm
EmRn
Emcnon ∆+
++
=44344214434421
ER
22
BJT
222
111
0 a) =EmRg
1 b) >>EmRg
fTgki mBon ∆= 22
fR
TkiE
Bon ∆=142
CC
t
mN II
Vg
R by set 22 ==
min
minmin
VVV
IVRR
satce
CEN
−==
KIVR
DMOSN 2
compare1
min,
−
=γ
( )02 =bi
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EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 7
CascodingCascoding
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EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 8
Output ResistanceOutput Resistance
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EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 9
RRout out = f(k)= f(k)
*11 kVVDS =
How choose k? Issues:
• Swing versus Ro• Large k useful only for large
Vmin simultaneously• Note: small or no penalty for
large k and small Vmin• typically choose k>1
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EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 10
HighHigh--Swing Cascode BiasingSwing Cascode Biasing• Need circuit for generating Vbias2
• Goal: Set Vbias such that VDS1 ≈ kV*– k > 1 (typical: 1