Single Electron Device Compatible with PSPICE and CMOS technology

BYMD S FAHAD & MAZIAR AMIRANI

DIVISION OF ELECTRICAL & COMPUTER ENGINEERINGSCHOOL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

LOUISIANA STATE UNIVERSITY

April 29, 2013

EE 7200: NanoelectronicsDr. A. Srivasrava

Contents• Introduction

• Single Electron Tunneling Transistor (SETT)

• Physical Structure of SETT:

• Operating principles

• Coulomb Blockade (CB)

• I-V Characteristics of typical SETT

• Simulating techniques

• Some SPICE models: Impulse Model

• Our Observation of Coulomb Blockade

• Present day Experimental Results

• Conclusion

Introduction

- TREMENDOUS PROGRESS in microelectronics has pushed the MOSFET dimension toward the 10-nm limits and motivated the interest for new devices that could perform at nanoscale according to International Technology Roadmap for Semiconductors figures of merit. In the near future it is then probable that CMOS will need to share its domination with fundamentally new devices[1].

- Power dissipation at nanoscale is getting intensified, hence ideas of next generation non-classical device i.e. carbon electronics, tunnel FET, Z2 FET, Single electron tunneling transistor, quantum dot devices are getting more and more attention for future R & D.1 Mahapatro et.al. “Analytical Modeling of Single Electron Transistor for Hybrid CMOS-SET Analog IC Design”, IEEE Tran Elec Dev., Vol. 51, No.11, Nov 2004.

Single Electron Tunneling Transistor (SETT)• With continuing advancement with nano scale device geometry,

special type of experimental observations are found, which were not reported before.

• Charge quantization effect in single electron transistor is one of such phenomena.

• Very promising and interesting candidate for future nanoelectronic circuits due to their ultra low power consumption and unique behavior.

• Realistic applications such as SET memory or programmable logic circuits is now becoming realistic with the advances in ULSI design.

• Promising candidate as compatible with CMOS fabrication processing and integration techniques.

Physical Structure of SETT:

• Structure of SET consists of a conductive island under gate contact separated from drain and source by tunneling junction.

• Transfer of a single electron in based upon the bias applied in the gate electrode.

• Capacitance effect from all these three terminals are account for the operation of the device.

(Y T Tan et al. 2003 J. Appl. Phys. 94 633)

Operating Principle

• Charge quantization effect is observed directly from the small dimension of single electron island.

• Minimum energy needed to transport a single electron to and from the island is

Where, (S.M.Sze, Kwok.N.Ng, “Phys of Semi Dev”, 3rd Ed. 2007, P-360)

Operating Principle (cont.)

• For experimental observation this needs to be:

• At room temperature Cz needs to be on the order of 10^-18 F for which island size needs to 1-2nm.

• Capacitor between the island and source and drain are characterized by tunneling resistance defined from the uncertainty principle that electron acts as particle on either side of the junction (~25.8KOhm):

Operating Principle (cont.)

• A SETT may also contain an optional second gate terminal, which is generally used to tune SET T Vgs bias.

• By changing potential on the gate electrode, the threshold voltage reduces or rises. The threshold voltage dependence on gate voltage is a periodic function with period e/Cg[2].

• As gate voltage increases to a certain value, electrons transit to the island, making one extra electron charge of dot. The average number of electrons in the island increases one by one as the gate voltage increases. 2(Bounouar et.al., “Single Electron Transistor Analytical

Model forHybrid Circuit Design” New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International, June 26-29, 2011)

Coulomb Blockade (CB)

• Minimum drain voltage (function of gate voltage) that turns on the current flow between the single electron island and source/drain.

• Expressed as Vcb.

• Expressed separately in two forms of tunneling:

a) Tunneling from source to island

b) Tunneling from island to drain (S.M.Sze, Kwok.N.Ng, “Phys of Semi Dev”, 3rd Ed. 2007, P-362)

Coulomb Blockade (CB) (cont.)

• Tunneling from source to drain

• Expression of Coulomb blockade:

• Negative Slope of this equation:

(S.M.Sze, Kwok.N.Ng, “Phys of Semi Dev”, 3rd Ed. 2007, P-364)

Coulomb Blockade (CB) (cont.)

• Tunneling from island to drain:

• Expresstion of Coloumb Blockade:

• The positive slope:

(S.M.Sze, Kwok.N.Ng, “Phys of Semi Dev”, 3rd Ed. 2007, P-364)

Coulomb Diamond

• Both positive and negative slope present on coulomb diamond.

• Hence SETT has both positive and negative transconductance based upon Vg.

• This is an unique feature from conventional transistor.

(S.M.Sze, Kwok.N.Ng, “Phys of Semi Dev”, 3rd Ed. 2007, P-364)

Condition when Coulomb blockade is absent

• The gate voltage at which multiple number (Ni) of tunneled transfer electron exists:

• This condition implies degeneracy: multiple Ni stands without exchnage of energy and means simultaneous tunnel of one electron from source to island and island to drain.

• This is the condition where Coulomb Blockade disappears.

I-V Characteristics of typical SETT

I-V curve in linear scale, v is Vg. I is Id

I-V curve in log scale

Simulating techniques:

• There are three simulation techniques:

• A) Monte-Carlo Simulation – uses orthodox theory of tunneling probability of electron transfer between island and drain/source. The Monte Carlo method achieves its results by stochastic integration. Many events taken together in average yield the correct result.

• B) Master Equation Solver - For very small circuits the Master Equation has its advantages over the Monte Carlo method. However as the circuits become complex, the method demands complex exponential matrix formulation.

• C) SPICE Macro Modeling - significantly faster than the typical single-electron simulator based on the Monte Carlo method or the Master Equation

SPICE model:

Implementing tunnel junction

-In Impulse model SET junctions are designed as a junction capacitor with a parallel current source.-When the junction voltage uj exceeds the critical voltage, which is defined as the minimal voltage across the junction needed for tunneling, Uj, the current source is triggered and current i(t) = ed(t - to) (delta function)will flow, and effectively one electron will be transferred from node (2) to node (1).

Haar et.al. “A SPICE model for single electronics” Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, p-868-871, vol.5, Dec 2002

SPICE Model (cont.)

Complete SPICE model

-Rectangular shape pulse is generated using a one shot function which consists of a flipflop and a delay function.- The flip-flop is hard programmed and the function is defined as:

Haar et.al. “A SPICE model for single electronics” Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, p-868-871, vol.5, Dec 2002

SPICE Model (Cont.)Junction Connected to Current source• Current source will charge the

capacitor with DC current Ib. Hence Uj will rise up.

• As soon as Uj (Uout)will try to cross the prefixed Ucr (critical voltage, coulomb blockade point[q^2/2Cz]), it will fall off and again process will start up.

• This incident indicates about a single electron tunneled through the barrier.Haar et.al. “A SPICE model for single electronics” Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, p-868-871, vol.5, Dec 2002

SPICE Model (other type) (Jia et.al.“SPICE implementation of a compact single electron tunneling transistor model”

Nanotechnology, 2004. 4th IEEE Conference on, pp-392-395, Aug 16-19, 2004)

Implemented Current Equation:

SETT Schematic

SETT SPICE model

Where, p is probability of a state having n number of extra electrons in it, Rd/Rs are tunneling resistance between two junctions, T is tunnleing rate

Conductance is calculated from the derivative:

Output the model: (Jia et.al.“SPICE implementation of a compact single electron tunneling transistor model” Nanotechnology, 2004. 4th IEEE Conference on, pp-392-395, Aug 16-19, 2004)

I-V curve: Simulated Inverter Curve:

Our Observation of Coulomb Blockade: (plot of Vg vs Vcb based on slide 10 and 11)

For Cg=1^-18F For Cg=5^-18F

Present day Experimental Results:

Fabricated Device Model:

(a) Schematic view of a sample. Device operation is described in the text. (b) (Left) Optical micrograph of a sample. (Right) SEM micrograph (before UG deposition) of the active device area, and schematics of an electrical measurement circuit (does not show VUG). Lower gates LGS, LGC, and LGD are poly-Si, and the conducting channel (S/D) is single-crystal Si. Channel and lower gates sit on top of the buried silicon oxide (BOX). The white arrow next to the finger gate indicates the gate length.

Kopinen et.al.” Fabrication and characterization of fully CMOS-compatible Si single electron device” IEEE Trans. Elec. Dev., Vol.60, No.1, 2013

Observed Coulomb Diamond:Output Characteristics:

-(LEFT)Coulomb diamonds measured at 30 mK for a SET device; N is the electron number. Charging energy Ec = 1.2 meV, drain capacitance Cd = 7 aF, and total capacitance of the island CΣ = 70 aF, extracted from the diamond data. The capacitance values for both LGS and LGD were about 5 aF.- Our plotted curve matches with the experimental observation.- (RIGHT) SET oscillations of a device at 2.2 K; vertical dashed lines (red or gray) are separated by a period of 12.9 mV. The data show good uniformity of the gate capacitance over 90 periods.

Kopinen et.al.” Fabrication and characterization of fully CMOS-compatible Si single electron device” IEEE Trans. Elec. Dev., Vol.60, No.1, 2013

Conclusion

-SPICE compatible model of single electron devices are in good agreement with both analytical formalism and fabricated experimetnal data.

- It is also more efficient and faster than Monte Carlo and Master Equation simulation techniques.

-Proper implementaion this models could lead to effective design and modeling of large scale single electron transistor based chip design.

Thank you