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CMOS/Overview

– Review• MOSFETs I/V operation and characteristics

summary

• 2nd order effects

• Scaling theory

• Short-channel effects

– CMOS processing technology

– Latch-Up

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CMOS/Objectives

– A basic understanding of MOSFETs• Why?

– MOSFET is the predominant VLSI device

– A basic understanding of CMOS processing technology

• Why?– Basic knowledge about CMOS processing technology is essential.

Understand effects like latch-up and on-chip transmission lines

– Many limitations imposed on performance of ICs are directly related to CMOS fabrication issues

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CMOS/Mosfets/Mosfet as a Switch– “MOSFET”

Metal Oxide Silicon Field Effect Transistor

– Symbol• Shown is a symbol for an n-type mosfet

– Operation as a switch• Voltage at gate VG is “high”:

Source and drain connected

• Voltage at gate VG is “low”:Source and drain isolated

– Questions:• Threshold voltage? Resistance between S

and D for On/Off? Speed?

Gate

Source Drain

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CMOS/Mosfets/Basic Structure

– Basic MOSFET Structure• Shown is a simplified structure of an n-type MOSFET (NMOS, NFET)• Fabricated on p-type substrate (“bulk”, “body”)• Device consists of

– two heavily-doped n-regions forming Source (S) and Drain (D)– a heavily-doped piece of polysilicon (“poly”, amorphous Si)– a thin layer of silicon oxide (SiO2) insulating the gate from the substrate.

Gate oxide thickness tox.

• Useful action of the device occursin the substrate region underthe gate oxide

• Symmetrie (S and D)• Mosfet idea was patented

1930 (Lilienfeld)well before BJT (Shockley, 1947, see above)

n+

B

p-substrate

S DG

n+p+

W

Leff

Ldrawn

Poly

Oxide

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CMOS/Mosfets/Mosfet IV Characteristics• Threshold voltage:

– Gate voltage Vg increases from zero. Gate and substrate form a capacitor. Holes in substrate are repelled from the gate area leaving negative ions behind. A negative space-charge region is created. The negative charge in the induced depletion region corresponds to the negative charge on the bottom plate of the gate-oxide capacitor. No current flows from D to S because no free charge carriers are available.

– As Vg increases so does the width of the depletion region and the potential at the oxide-silicon interface. The structure resembles two capacitors in series: the gate-oxide capacitor, and the depletion region capacitor.

– When the interface potential reachesa sufficiently positive value,electrons flow from the S to theinterface and on to the D. A “channel”of charge carriers is formed between Sand D, the transistor is “on”. Theinterface is “inverted”. Vg has reachedthe threshold voltage Vth.

– If Vg rises further the channel chargedensity increases further

n+ n+p+

p-substrate

Vd (0.1V)Vg

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CMOS/Mosfets/Mosfet IV Characteristics• Threshold voltage:

– In practice the turn-on phenomenon is a gradual function of Vg making it difficult to define the threshold voltage Vth unambiguously

– Threshold voltage Vth in semiconductor physics:The interface is “as much n-type as the substrate is p-type”

– “Native” threshold values may not be suitableThreshold-adjust implant into the channel area during device fabrication. Essentially alters Nsub near the oxide interface.

Cox

QdepVth FMS ++= φφ 20

=

ni

Nsub

q

kTF lnφ φF: Bulk potential

φMS: Contact potential between poly and bulkNsub: Substrate carrier concentrationni: Carrier concentration in undoped SiQdep: Charge in depletion regionCox: Gate-oxide capacitance per unit area

FSi NsubqQdep φε ⋅⋅⋅= 4

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CMOS/Mosfets/Mosfet IV Characteristics• What happens if Vd is increased?

– As the drain voltage increases, the voltage drop across the oxide near the drain terminal decreases. The induced inversion charge density near the drain decreases. As Vd increases to the point where the potential difference across the oxide at the drain terminal is equal to Vth the induced inversion charge density at the drain terminal is zero. For this condition the incremental channel conductance at the drain is zero, which means that the slope of Id vs Vd is zero (in theory…)

0 1 2 3 4 5 6

0.5

1

1.5

2

2.5

32.722

0

Id Vds 4 V⋅,( )

m A⋅

Id Vds 3 V⋅,( )

m A⋅

Id Vds 2 V⋅,( )

m A⋅

60 Vds

VthVgsVdssat −=

• If Vds<Vdssat

– Triode region, linear region

• If Vds>Vdssat

– Saturation region

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CMOS/Mosfets/Mosfet IV Characteristics• Mosfet I/V Characteristics in the triode region (linear region)

( )

−−⋅⋅= 2

2

1VdsVdsVthVgs

L

WCoxnId µ

µn: Mobility of electronsL: Effective channel lengthW: Channel width

• Deep triode region Vds<<Vgs-Vth

( )VdsVthVgsL

WCoxnId −⋅⋅= µ

( )VthVgsL

WCoxn

Ron−⋅⋅

=µ

1 In the deep triode region mosfet can operate as a resistor whose value is controlled by the overdrive voltage

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CMOS/Mosfets/Mosfet IV Characteristics• Mosfet I/V Characteristics in the saturation region

( )2

'2

1VthVgs

L


L’: Channel length to pinch-off point

• Transconductance gmA Mosfet in saturation produces a current in response to its gate-source voltage

constVdsVgs

Idgm

=

=δδ

( )VthVgsL

WCoxngm −⋅⋅= µ

IdL

WCoxngm ⋅⋅= µ2

VthVgs

Idgm

−= 2

n+ n+p+

p-substrate

VdsVgs

L'

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CMOS/Mosfets/Mosfet IV Characteristics• P-channel devices

np µµ of %50..25=

• Mobility of holes is less than mobility of electrons. PMOS devices suffer from lower “current drive”. Use NMOS wherever possible.

• NMOS and PMOS devices must be fabricated on the same wafer, i.e. the same substrate. One device must be placed in a “local substrate” or “well”. Typically the PMOS device is fabricated in an n-well. The n-well must be connected to a potential such that the S/D junction diodes of the PMOS transistor remain reverse-biased under all conditions. In most circuits the n-well is tied to the most positive supply voltage using a well-tie.

p+ p+ p+n+ n+ n+

p-substraten-well

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CMOS/Mosfets/2nd order effects– Body effect:

So far it was assumed that the substrate and the source were tied together (to ground). If the substrate voltage drops below the source voltage the threshold voltage Vth increases.

n+ n+p+

p-substrate

VdVg

Vb<0Cox

QdepVth FMS ++= φφ 20

( )FF VsbVthVth φφγ 220 −++=

γ: body-effect parameter

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CMOS/Mosfets/2nd order effects– Channel-Length Modulation

The length of the inverted channel gradually decreases as the potential difference between gate and drain increases.

LLL ∆−='

( )2

'2

1VthVgs

L


LL

L

L

∆+≈

1

'

1Vds

L

L ⋅=∆ λ

( ) ( )VdsVthVgsL

WCoxnId λµ +−⋅⋅≈ 1

2

1 2

λ: channel-length modulation coefficient

n+ n+p+

p-substrate

VdsVgs

L'

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CMOS/Mosfets/2nd order effects– Sub-threshold Conduction

So far it was assumed that mosfets turn off abruptly as Vgs drops below Vth. In reality a weak inversion layer still exists even for Vgs<Vth, and some current flows from D to S.

Vt

VgsIdId

⋅⋅≈

ζexp0

ζ: nonideality factor

Valid for Vds>200mV

With typical values for ζ, at room temperature Vgs must decrease by about 80mV for Id to decrease by one decade. Sub-threshold conduction is a serious challenge for further lowering operating voltages of ICs.Assume: Vcc=1V. Vth=0.32V. When Vgs is reduced from 0.32V to 0V the drain current decreases only my a factor of 104

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CMOS/Short-Channel Effects

• Comments– Equations covered so far provide acceptable accuracies for devices

with L>4um

– Status Quo (2002): L=0.13um and falling…

– Understanding of short-channel effects and improved models required so as to attain enough accuracy in simulations

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CMOS/Short-Channel Effects

• (Incomplete) List of short-channel effects:– Threshold voltage variation with channel length

Depletion regions associated with S/D junctions protrude into the channel yielding a lower Vth.

– Drain-induced barrier lowering (DIBL)Drain voltage affects Vth

– Mobility degradation with vertical fieldLarge Vgs leads to more carrier scattering and reduced mobility

– Velocity saturationMobility of carriers begins to drop as electric fields increase above 1V/um

– Hot carrier effectsHigh lateral electric fields cause “hot” carriers which may hit Si atoms near drain at high speeds creating impact ionisation (causing substrate and gate currents).

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CMOS/Short-Channel Effects/Scaling Theory– Scaling Theory, discussed by Dennard et al, 1974

Dennard et al recognised the tremendous potential of scaling MOS transistors

– Gordon Moore, 1975. Predictions:• Mosfet device dimensions scale down by a factor of 2 every 3

years

• #transistors/chip double every 1-2 years.

– Dennard: Constant-field scaling• Reduce all lateral and vertical dimensions by α (α>1)

• Reduce threshold voltage and supply voltage by α• Increase all doping levels by α

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CMOS/Short-Channel Effects/Scaling Theory– Results of constant-field scaling

• all electrical fields in the transistor remain constant• current capability of transistors drop by a factor of α• all capacitances (channel capacitances, S/D junction capacitances) decrease

by a factor of α• delay times decrease by a factor of α• dynamic power dissipation drops by decrease by a factor of α3 (!)• transconductance remains constant

– However:• Reduction of supply voltage reduces dynamic range (of analog circuitry)

Lower end of dynamic range is limited by thermal noise

• To restore dynamic range the transconductance must be increased by α2.• Sub-threshold conduction problems• Problems caused by short-channel effects

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CMOS/Short-Channel Effects/Scaling Theory

– Because of these problems: Constant-voltage scaling• leads to increased electric field strengths

– In practice:Mixture of constant-field and constant-voltage trends

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CMOS/Processing technology– Why MOS/CMOS?

Dimensions of MOS devices can be scaled down more easily than other transistor types

– Starting mid 1960’s: Shift from NMOS to CMOSMain reason: “Zero” static power dissipation

– CMOS technology was attractive because of the relative small number of masks (about 7)

– Modern CMOS processes:• about 200 process steps• about 25 masks

Number of masks heavily impacts unit price of the chip. Each mask costs n*$1k (total mask cost typ. $200k). Lithography is slow.

• up to 6 (and sometimes more) metal layers• Poly layers: 1 or 2 (standard) or more (non-standard, e.g. E2prom)• Today’s standard: n-well CMOS process with self-aligned polysilicon gates

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CMOS/Processing technology

Source: TSMC

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CMOS/Process steps– Process step: Wafer fabrication

• Czochralksi method:– Seed of crystalline Si is immersed in molten amorphous Si (1425°C).

Molten Si contains desired level of p-type doping.

– Seed is gradually pulled out while rotating (30-180mm/h)

– Result: Large single-crystal cylindrical ingot

• Ingot is sliced into thin wafers– Wafer sheet resistance: 50-200Ω– Initial wafer thickness: 500-1000µm

– Wafer diameter: 75-300mm (12 inch)

• Wafers are polished and etched to remove surface damages

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CMOS/Process steps– Process step: Grow thin layer of SiO2 on p-type wafer

• Place wafer in an oxidizing atmosphere at around 1000°C

• Unique property of Si: a very uniform oxide layer can be produced on the surface with little strain in the lattice

• Oxide layers can be very thin (e.g. 50Å=5nm), only a couple of atomic layers

• Oxide can be used as gate dielectric (TOX). Oxide can also grown thick (field oxide FOX) as a foundation for interconnect lines

• Oxide also serves as a protective coating during many process steps(like in this process step)

p-substrate

SiO2

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CMOS/Process steps– Process step: Lithography sequence for n-well

• Photolithography: Transfer circuit layout information to the waferLayout consists of polygons. Layout is first “written” to a transparant glass “mask” by a precisely controlled electron beam.

• Negative Photoresist (PR) depositionPR: A material whose etching properties change upon exposure to light. Negative PR “hardens” in regions exposed to UV light. Positive PR “hardens” in regions not exposed to UV light.

• Exposure to ultraviolet (UV) light using the n-well mask

• Selective etching. Etchant dissolves “soft” PR

p-substrate

Photoresist

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CMOS/Process steps– Process step: Create n-wells through ion implantation

• n-wells required for p-channel devicesn-channel devices will be fabricated directly in the native p-substrate

• Ion implantation: Selectively introduce dopants into the waferDoping atoms are accelerated as a high-energy focused beam, hitting the surface and penetrating the exposed areas. Doping level determined by intensity and duration of implantation.Retrograde profile: Peak of the doping concentration occurs well below the surface

p-substrate

Ion implantation n-type

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CMOS/Process steps– Process step: Remove PR and oxide layer

• n-well completed

• Note: Ion implantation damages the Si latticeSi lattice can be repaired through an annealing process. Annealing: Wafer is heated to 1000°C for 15-30min allowing the lattice bonds to form again. Annealing causes dopant diffusion in all directions (e.g. side diffusion of S/D regions). Therefore, wafer is annealed only once after all implantations have been completed

p-substraten-well

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CMOS/Process steps– Process step: Channel-stop implant (1)

• Channel-stop implant required to prevent parasitic mosfetsPrevents conduction between unrelated transistor sources and drains (and wells). Two n+ regions and the FOX from a transistor. FOX is thick, therefore transistor has a large Vth. Nonetheless, a sufficiently positive potential on the interconnect line will turn on the transistor slightly (causing a leakage path). Channel-stop implant raises Vth of parasitic transistor to a very large value.

• Create a stack of silicon oxide, silicon nitride, and positive PR

p-substraten-well

SiO2

Si3N4

PR (positive)

n+ n+ n+ n+

Gate M1 Gate M2

PolyInterconnect

Parasitic Inversion Layer

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• Lithography sequence for channel-stop implant (based on positive PR)

• “Active” mask is usedActive or diffusion areas include the source/drain regions and the p+ and n+ openings for the substrate and well ties

p-substraten-well

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• Perform channel-stop ion implantation

p-substraten-well

Channel-stop implant

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• Remove PR

• Thick oxide layer is grown in the exposed silicon areas producing the field oxide (FOX)FOX grows in areas where the silicon nitride layer is absent

p-substraten-well

FOXChannel-stop implant

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• Remove protective silicon nitride layer

• Remove protective thin oxide layer

• Result: Active areas are exposed

p-substraten-well

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CMOS/Process steps– Process step: Growth of gate oxide

• Growth of gate oxide serving as gate dielectric (TOX)The growth of the gate oxide is a very critical step in the process. It’s thickness tox determines a multitude of parameters of mosfets (current handling, transconductance, reliability). In order to achieve good matching of transistors extremely uniform thickness across the wafer is required. The oxide is therefore grown in a slow low-pressure CVD (chemical vapor deposition) process. Also, the cleanness of the silicon surface underneath the oxide affects the electrical behaviour of the mosfet.

p-substraten-well

TOX

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CMOS/Process steps– Process step: Threshold-adjust implant

• Threshold-adjust implant after photolithographic processThe “native” threshold voltage of transistors is typically far from the desired value (VTHN≈0V and VTHP ≈ -1V). A thin layer of dopants near the surface is implanted to adjust the native threshold voltage. Thresholds of both NMOS and PMOS transistors will become more positive.

p-substraten-well

Threshold-adjust implant

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CMOS/Process steps– Process step: Create polysilicon (poly) layer

• Deposit a layer of polysilicon on top of the gate oxidePolysilicon is noncrystalline (or “amorphous”) silicon because this layer grows on top of silicon dioxide, i.e. cannot form a crystal. Since polysilicon only serves as a conductor its amorphous nature is unimportant.

• Carry out “poly mask” lithography

p-substraten-well

Poly

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CMOS/Process steps– Process step: n-type implant (1)

• Deposit negative photoresist

• Photolithography using “N source/drain mask”After the photolithography all areas to receive an n+ implant are exposed. These areas consist of source and drain junctions of NMOS transistors, and the n-well ties.

p-substraten-well

Neg. PR

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• Ion implantationIon implantation forms the S/D regions of NMOS transistors and n-well ties. Note that the implant also dopes the polysilicon layer of the NMOS transistors, reducing its sheet resistance.

p-substraten-well

N-type implant

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• Remove PR

• Self-aligned structureThe sequence of creating the gates first prior to n-type implantation yields a self-aligned structure. The S/D regions are implanted at precisely the edges of the gate area. A small misalignment in lithography has no major effect (it simply makes one junction slightly narrower than the other).

p-substraten-well

n+ n+ n+

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CMOS/Process steps– Process step: p-type implant (1)

• Photolithography sequence using “P source/drain mask”After the photolithography all areas to receive an p+ implant are exposed. These areas consist of source and drain junctions of PMOS transistors, and the substrate ties.

• Ion implantationThe implant also dopes the polysilicon layer of the PMOS transistors, reducing its sheet resistance

p-substraten-well

P-type implant

n+ n+ n+

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CMOS/Process steps– Process step: p-type implant (2)

• Remove PR

• Basic transistor fabrication complete

• Remaining processing steps: “Back-end processing”

p-substraten-well

n+ n+ n+p+ p+ p+

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CMOS/Process steps– Process step: Silicidation (1)

• Creation of oxide spacerPurpose of Silicidation: Reduction of sheet resistance of doped polysilicon and S/D regions by about an order of magnitude. During silicidation active areas (S/D regions, substrate and well ties) are covered with a thin layer of highly conductive material (titanium silicide or tungsten). The silicidation process begins with creating an oxide spacer at the edges of the polysilicon gate such that the deposition of the silicide will not short the gate to the S/D regions.

p-substraten-well

n+ n+ n+p+ p+ p+

Oxide spacer

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CMOS/Process steps– Process step: Silicidation (2)

• SilicidationDeposition of conductive material through CVD process

p-substraten-well

n+ n+ n+p+ p+ p+

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CMOS/Process steps– Process step: Contact windows

• Cover wafer with a thick layer of oxideThickness: 300-500nm

• Lithography using the “contact mask”

• Plasma etchingFor increased reliability contacts to the gate polysilicon are not placed on top of the gate area

p+ p+ p+n+ n+ n+

p-substraten-well

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CMOS/Process steps– Process step: Metal interconnect 1 (1)

• Deposit layer of metal over the entire waferCommon metals: Aluminium or copper

p+ p+ p+n+ n+ n+

p-substraten-well

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• Photolithography sequence using “Metal 1 mask”

• Metal selectively etched

p+ p+ p+n+ n+ n+

p-substraten-well

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CMOS/Process steps– Process step: Via windows

• Cover wafer with a layer of SiN3

• Lithography using the “via mask”

• Plasma etching

p+ p+ p+n+ n+ n+

p-substraten-well

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• Deposit layer of metal over the entire wafer

p+ p+ p+n+ n+ n+

p-substraten-well

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• Photolithography sequence using “Metal 2 mask”

• Metal selectively etched

– Metal interconnect layers:• Two masks required for each additional metal layer: “via n mask” and “metal n mask”

• Reliability: Dimensions of contacts/vias cannot be changed by layout designer (to avoid “contact spiking”). If a large contact area is required, many small contacts/vias are used in parallel.

p+ p+ p+n+ n+ n+

p-substraten-well

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CMOS/Process steps– Process step: Passivation

• PassivationWafer is covered with a layer of “glass” or “passivation”, protecting the surface against damages caused by subsequent mechanical handling and dicing.

p+ p+ p+n+ n+ n+

p-substraten-well

Passivation

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CMOS/Process steps– Process step: Contact windows for bond pads

• Photolithography sequency

– Final processing steps:• Testing, dicing, packaging, bonding, testing.

p+ p+ p+n+ n+ n+

p-substraten-well

Bond pad

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CMOS/Sheet Resistance

W

LRs

Wh

L

A

LR =

⋅⋅=⋅= ρρ

ρ: Material resistivity in Ω mRs: Sheet resistance in Ω

hRs

ρ=

Sheet Resistances

Material Rs in ΩΩΩΩ

Metal (top layer) 0.05

Metal (lower layers) 0.1

Polysilicon (silicided) 6

Diffusion (n+, p+, silicided) 10

Polysilicon (doped) 30

Diffusion (n+, p+) 100

n-well 5k

NichromeMixed signal IC resistor material. Stable and laser-trimmable

several k

Polysilicon (undoped) several Meg

Wh L

To obtain the resistance of a conductor on a layer, multiply the sheet resistance Rs by the ratio L/W of the conductor.Note: Rs is a process parameter. Ratio L/W is a design parameter.

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CMOS/Process Example

Example process:

0.8um CMOS + HV module.

Data source: Process Parameter Spec

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CMOS/Latch-Up– Latch-Up: Destructive mechanisms in CMOS circuits

• Latch-Up is a parasitic circuit effect

• Result of the effect is a short-circuit between Vcc and GND lines, usually resulting in chip destruction (or at least system failure with the requirement of power down)

• Mechanism did not exist in early MOS technologies (NMOS, PMOS)

• Initially led to the lack of acceptance of early CMOS processes

• In current processes parasitic circuit elements are well understood and controlled by process innovations and circuit techniques

p+ p+ p+n+ n+ n+

p-substraten-well

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CMOS/Latch-Up/Physical Origin– Physical Origin

• Parasitic components Q1, Q2, R1, R2 shown below found in all CMOS circuits

• (Vertical) Q1 is associated with the PFET M1, the n-well, and the substrate

• (Lateral) Q2 is associated with the NFET M2, the substrate, and the n-well

– Observations:• Base of each bipolar transistor is connected to the collector of the other

• Bases of Q1 and Q2 see a non-zero resistance to Vcc and GND, resp.

p+ p+ p+n+ n+ n+

p-substrate

n-well

R2 R1Q1

Q2

GND D GND

M2 M1

Vcc D Vcc

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CMOS/Latch-Up/Physical Origin– Parasitic circuit redrawn

• Reveals a positive feedback loop around Q1 and Q2:– Current injected into node X

– V(X) rises and reaches “trigger point” (around 0.7V)

– Collector current of Q2 increases

– V(Y) falls

– Collector current of Q1 increases

p+ p+ p+n+ n+ n+

p-substrate

n-well

R2 R1Q1

Q2

GND D GND

M2 M1

Vcc D Vcc

GND GND

Vcc Vcc

Q2

R1

R2

Q1

node Xnode Y

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CMOS/Latch-Up/Feedback– Feedback loop

• If the loop gain is greater than or equal to unity, the phenomenon continues until both transistors turn on completely, drawing a large current from Vcc. The circuit is then “latched up”, equivalent to a short-circuit between Vcc and GND.

• The current drawn from Vcc is only limited by parameters of the parasitic components

• The current drawn is usually destructive to metal lines supplying the latched up circuitry

• The latched up condition will persist until– circuit destruction

– circuit powered down

GND GND

Vcc Vcc

Q2

R1

R2

Q1

node Xnode Y

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CMOS/Latch-Up/Causes– Various sources can trigger a “latch-up”

• The bases of Q1 and Q2 are capacitively coupled to the drains of M1 and M2. Large drain dV/dt’s can inject significant displacement currents into the n-well or substrate

• Forward biasing of source-bulk junction diodes (mosfets used in output stages, or input protection diodes). Notoriously dangerous: Driving inductive loads

• Ground-bounce (again forward biasing junction diodes)

• Transient conditions during chip power-up

• Apply signals to inputs while chip is powered down

• Radiation

GND GND

Vcc Vcc

Q2

R1

R2

Q1

node Xnode Y

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CMOS/Latch-Up/Prevention– Latch-Up Preventation

• Latch-up preventation is a challenge for both process engineers and circuit designers

• Process: Proper choice of doping levels and doping profiles as well as layout design rules to ensure a low value for parasitic resistances and the current gain of the bipolar transistors

• Layout: Substrate and n-well contacts with sufficiently small spacing (to minimise resistance)

• External circuitry: controlled start-up, external protection of IC inputs and outputs

• Technology design manual developed by foundry provides an extensive set of layout rules

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