EE365 Adv. Digital Circuit Design Clarkson University Lecture #6 Timing and Related Design...

EE365Adv. Digital Circuit Design

Clarkson University

Lecture #6

Timing and Related Design Considerations

Topics

• Signal Naming Conventions -Buses

• Timing Diagrams

• Data Book Reference

• Timing Specifications

• Timing Hazards

Rissacher EE365Lect #6

Buses• A group of digital signals which carry multi-bit

data• Shown on a block diagram with a single (or

double) line• Shown on a logic diagram (schematic) with a

single (sometimes heavier) line• Usually named using an indexed notation:

ADDR0, ADDR1, ADDR2, … or ADDR[7:0] or ADDR (7 downto 0)


Timing Diagrams• Graphical representation of circuit behavior

over time• May be used as a device specification

– illustrates device performance

• May be used as a module or system specification– identifies a requirement for system performance

• May be used as a tool in system analysis


Example Timing Diagram• Functional Timing Diagram

– assumes zero delays– simply demonstrates logic relations

ABC

w

A

C

B

W


Example Timing Diagram

• Functional diagram is useful for showing causal relationships

• This is often done with a curved arrow leading from an input transition to the resultant output transition

• Notice that transitions are shown as vertical lines, but in reality these always require a non-zero time for making a transition


Example Timing Diagram• Timing Diagram (more realistic)

– shows delays using typical or maximum values

ABC

w

A

C

B

W

tpHL tpLH


Propagation Delay

• The delay between an input transition and the resultant output transition is called propagation delay

• Propagation delay is measured between the centers of the transition time period


Propagation Delay• Propagation delay for an output

transition from high to low is tpHL

• Propagation delay for an output transition from low to high is tpLH

• Notice that these two times are not necessarily the same for the same device

• Notice the difference from Transition Times


Recall: Transition times


Data Book Reference


Timing Specifications

• Shows uncertainty in propagation delay

C

W

tpHL

min

max


Timing Specifications

• Shows uncertainty in signal value– used to show timing when signal value is

not relevant– used to show timing for bus signals


I/O Rate Considerations

• The inputs to the system can come at a certain rate if the expected logic function is to be accurately represented by the output

• Propagation Delays need to be considered


Timing Hazard

• Transient output behavior may not agree with predicted output due to delay differences

• A glitch is the presence of extra signal transitions which are not predicted from the logic equations


Static Hazards

• A static hazard is the possibility of a glitch when the output should not change

• A static-1 hazard is present if changing a single input variable may produce output transitions but the output logic function is high (1) independent of this change.


Example of a Static-1 Hazard

0 -> 1

1 -> 0

0

X'WA

XY'B'

YW'A'

F(X, Y, B, W, A)

Consider an input change from (X=1, Y=0, B=0, W= 1, A=1) to(X=0, Y=0, B=0, W= 1, A=1) - what happens ?If the propagation delay from along the path of gate U1a islonger than along the path of gate U1b, then F could go lowduring that extra delay.

U1a

U1b


Detection of Static-1 Hazards

• A properly designed OR-AND circuit will never have static-1 hazards

• An AND-OR circuit may have static-1 hazards

• These can be detected from a K-map• Check for adjacent minterms NOT

covered by the same product term (AND gate) in the actual realization


Detection of a Static-1 Hazard

WA \YB 00 01 11 1000 1 10111 1 1 1 110

WA \YB 00 01 11 1000 1 1 101 111 110 1

X = 0 X = 1

The static-1 hazard can be detected by noticing that there are two adjacent minterms (3) and (19) which are not covered by a common product term. It can be eliminated by including an additional product term in the realization.


Hazard Free Circuit

0 -> 1

1 -> 0

0

X'WA

XY'B'

YW'A'

F(X, Y, B, W, A)

U1a

U1b

1Y'B'WA

1


Static Hazards

• A static-0 hazard is present if changing a single input variable may produce output transitions but the output logic function is low (0) independent of this change.

• While hazards produce unexpected transitions and may be intermittent, proper design of synchronous sequential circuits should tolerate hazards.


Detection of Static-0 Hazards

• A properly designed AND-OR circuit will never have static-0 hazards

• An OR-AND circuit may have static-0 hazards

• Check K-map for adjacent maxterms NOT covered by the same sum term (OR gate) in the actual realization


In-Class Practice Problem

Correct any static-1 hazards in the following function (circle on map and write new F function)


In-Class Practice Problem


Dynamic Hazards

• A dynamic hazard is the possibility of a glitch when the output changes from low to high or high to low

• Since the output is supposed to change, the presence of a glitch means the output makes more than one transition– low high low high– high low high low


Dynamic Hazards

• Do not occur in properly designed two-level circuits

• What is “properly” designed ?– no first level gate has both true and

complement forms of the same signal as inputs


Hazards in Other Circuits

• NAND-NAND circuits - equivalent to AND-OR

• NOR-NOR circuits - equivalent to OR-AND

• Multi-level circuits – have more than two levels of logic (not

counting inverters)– may have static and/or dynamic hazards


Next Class

• Intro to MSI

• PLDs

• Decoders


EE365 Adv. Digital Circuit Design Clarkson University Lecture #6 Timing and Related Design...

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