ee321 chap02 computer top level - Abdelhakim Khouas
Transcript of ee321 chap02 computer top level - Abdelhakim Khouas
EE321Computer Architecture
Chap 02 : Top Level View of ComputerChap. 02 : Top Level View of Computer
Dr. Abdelhakim KhouasEmail : [email protected]
ab khouas@univ boumerdes [email protected] (ex. INELEC)
University M’hamed Bougara of Boumerdes
Course chapters
1. Review of Digital Design1. Review of Digital Design2. Top Level View of Computer3 Central Processing Unit (CPU)3. Central Processing Unit (CPU)4. Control Unit5 M5. Memory6. Instruction Set and Addressing Modes
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Readings
TextbookComputer Organization and Structure,Computer Organization and Structure,
Designing for Performance, By William Stallings 8th editionStallings, 8 edition
SectionsChapter 1, sections: 1.1 and 1.2Chapter 2 sections: 2 1 and 2 5Chapter 2, sections: 2.1 and 2.5Chapter 3, sections: 3.1 and 3.2
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Lecture Objectives
This lecture focuses on the basic structures u o u o ba u uused for computer component interconnection
A brief examination of the basic components and their interface requirementsA functional overviewIssue of performanceIssue of performance
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Lecture Outline
1 D fi iti1. Definitions2. Computer Evolution3. Computer Components
1. Central Processing Unit (CPU)g ( )2. Memory3. Input/Output (IO) Peripheralsp / p ( ) p4. System Buses
4. Computer Function4. Computer Function5. Performance Assessment
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1. Definitions
Computer Architecture pRefers to attributes of a computer visible to the programmer and that have a direct impact to onprogrammer and that have a direct impact to on the logical execution of a program
• Examples of architecture attributes: Instruction set, p ,number of bits, memory addressing modes
Computer OrganizationComputer OrganizationRefers to the operational units and their interconnections that realize the architecturalinterconnections that realize the architectural specifications
• Example: Multiply Unit
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Example: Multiply Unit
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1. Definitions
A computer is a complex system organized in aA computer is a complex system organized in a hierarchical system. At each system level:
The structure describes the way in which the components are interrelatedpThe function defines the operation of each individual component as part of the structureindividual component as part of the structure
• Computer Structure: CPU, Memory, BUS, I/O• CPU Structure: ALU Registers Control Unit Bus• CPU Structure: ALU, Registers, Control Unit, Bus• Control Unit Structure: Sequencing logic, registers,
decoders, memory control
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decoders, memory control
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1. Definitions
Computer top level structure
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Source: Computer Organization and Structure, by W. Stallings
2. Computer Evolution
1947: ENIAC (Electronic Numerical Integrator And1947: ENIAC (Electronic Numerical Integrator And Computer)
Fi t t d l d t P l i U i it 30First computer developed at Pensylvania University, 30 tons, 150 m2, 18 000 vacuum tubes, decimal machine, 20 10-bit accumulators, 5000 addition per second,20 10 bit accumulators, 5000 addition per second, programmed manually
1952: Von Newmann/Turing machine/ gDeveloped at Princeton Institute for Advanced Studies (i.e. IAS computer)Stored-program conceptPrototype of today general purpose computers
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2. Computer Evolution
1947: Transistor invented at Bell LaboratoryyMade computers a lot smaller and more efficient
1971: Intel 4004 4-bit processorpAll of the components of a processor on a single chip (1st
microprocessor)108 Khz 2300 transistors 10 m technology108 Khz, 2300 transistors, 10μm technology
1972: Intel 8008Fi t 8 bit iFirst 8-bit microprocessorFirst commercially available processor
1965: Moore’s Law1965: Moore s LawThe number of transistors and the frequency will double every 18 months
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every 18 months
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3. Computer Components
All contemporary computer design are based onAll contemporary computer design are based on concepts developed by Von Newman. Such a d i i f d t V Ndesign is referred to as Von Newmann architecture or Turing machine and is based on 3 key concepts:1 Data and instructions are stored on single read and1. Data and instructions are stored on single read and
write memory (RAM)2. The contents of the RAM are addressable by location2. The contents of the RAM are addressable by location3. Execution of instructions occurs in sequential (unless
explicitly modified) from one instr. to the next one
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p y )
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3. Computer Components
A i f i t ti ll dA program is a sequence of instructions called also a codea o a od
At top level, a computer consists of:1. Central Processing Unit (CPU)2 Memory2. Memory3. Input/Output (IO) peripherals4 S b f i i (d4. System buses for interconnections (data,
address, and control buses)
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3. Computer Components
Von Newmann architecture
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Source: Wikimedia
3. Computer Components
Harvard architectureUses two separate memories, data and program memorymemoryHarvard architecture is used in specific processors such as DSP (Digital Signal Processor) and insuch as DSP (Digital Signal Processor), and in mobile communication and image processing systemssystems
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3.1. CPU
The basic function performed by CPU isThe basic function performed by CPU is execution of a program
Program is a set of sequential instructions stored in memoryin memory
Each instruction is represented by:p y1. Operation code (opcode): specify the operation
to be performedp2. Operand: specify the reference to the inputs and
outputs of the operation
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3.1. CPU
CPU i i l d fCPU is mainly composed of: 1. Registersg2. Arithmetic and Logic Unit (ALU)3 Control Unit3. Control Unit4. Internal Bus
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3.1. CPU
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Source:: Introduction to Computer Architecture, A. MaacheCPU components
3.1. CPU
RegistersRegistersAre used to temporarily store data, addresses, and codes. A generic basic CPU should have:g1. General Purpose Registers (GPR)2. Program Counter (PC): it points to the address of the next
instructioninstruction3. Memory Address Register (MAR): it contains the address for
the next read and write to/from memory. PC is copied to this register to fetch next instruction (see also IOAR)this register to fetch next instruction (see also IOAR)
4. Memory Buffer Register (MBR or MDR): it contains the data to be written or read into/from memory (see also IOBR)
5 I t ti R i t (IR) it h ld th t i t ti5. Instruction Registers (IR): it holds the current instruction which is being executed
6. Accumulator (AC): it holds the result of the ALU
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3.1. CPU
ALUALU This unit carries out the actual operation on datap
Control UnitThis units fetches program instruction from memory (fetch cycle) and stores it in IR. The instruction is decoded by the decoder (decode cycle), which then asserts the internal control signals to the relevant parts of the CPU via the internal control bus
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3.1. CPU
Internal System BusyThe 3 CPU components described above are connected together using three buses:connected together using three buses:
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3.2. Memory
Memory module isMemory module is semiconductor devices that store binary information (instructions and data)( )
Memory is organized as array of locations, each location holds n ,bits (N words of n bits)Depth= nb. of locationsWidth=nb. of bits per locationSize (capacity) = depth x width
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Source: Computer Organization and Structure, by W. Stallings
3.2. Memory
Each location in the memory has an addressEach location in the memory has an address (also called pointer or reference)
The CPU can access to any location in the memory using its addressg
Two main types off memoryRead Only Memory (ROM): The CPU can only read data from the memoryRead/Write memory: The CPU can write and read any location of memory (also called RAM)
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a y ocat o o e o y (a so ca ed )
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Source: Computer Organization and Structure, by W. Stallings
3.2. Memory
Stack memoryStack memoryStack memory is R/W memory, but the CPU can only read the last saved data (also called Last-Inonly read the last saved data (also called Last-In First-Out memory)The CPU has a special register called Stack PointerThe CPU has a special register called Stack Pointer (SP) that contain the address of the last data saved in the stacksaved in the stackThe CPU uses PUSH instruction to save a data and POP instruction to read data from the stackPOP instruction to read data from the stackSP is updated automatically after PUSH and POP instructions
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st uct o s
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Source: Computer Organization and Structure, by W. Stallings
3.2. Memory
Memory mapT i ll i i h N bi dd li iTypically, in a computer with N-bit address lines, it is capable of addressing 2N memory locationsThe memory range is divided by the programmer (or hardware designer) into sections suited to specific roles (e.g. program section, data section, stack section, ROM, EEPROM, RAM, etc.) This memory range division is called Memory Map
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Source: Computer Organization and Structure, by W. Stallings
3.2. Memory
Example: Memory map of Z80 boardLocation Description0000 3FFF Monitor EEPROM U24 (?? KB)( )4000 5DFF User RAM U26, User Stack 5E00 5FFF Monitor Stack5E00 5FFF Monitor Stack6000 7FFF Expansion (already interfaced)8000 FFFF Unused
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Source: Computer Organization and Structure, by W. Stallings
3.3. I/O Peripherals
A computer is useless unless it communicates pwith the external world (I/O peripherals)
I t d l t f d t f th t idInput modules transfer data from the outside world to the CPU, it includes devices like: keyboard switches and ADCkeyboard, switches, and ADC Output modules transfer data from CPU to the outside world it includes devices like: displayoutside world, it includes devices like: display, printer, LEDs, DACFrom internal view of CPU I/O is functionallyFrom internal view of CPU, I/O is functionally similar to memory, each I/O device has a port with unique address to read and write to/from it
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unique address to read and write to/from it
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3.4. System Buses
A bus is a communication path between CPU andA bus is a communication path between CPU and other peripherals
All peripherals share same bus, with only one device using the bus at any timeusing the bus at any time
Devices are connected to the bus through tri-state bufferbuffer
A system bus consists of about 50 to hundreds of t li ith ti l f ti f hseparate lines, with particular function for each
line
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3.4. System Buses
Computers buses are divided into three main groups:1. Data Bus2. Address Bus2. Address Bus3. Control Bus
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Source: Computer Organization and Structure, by W. Stallings
3.4. System Buses
Data busProvide a bidirectional path for moving the data, it may consist of 32, 64, 128 or more bits (lines) referred as th d t b idththe data bus width
Address busProvide a unidirectional path to send addresses to memory and I/O devices. The width of this bus specifies the maximum memory capacity of thespecifies the maximum memory capacity of the system. A 16-bit address bus is capable of addressing 64K locations (Q: memory size ???)
Control busUsed to control the access to data and address buses
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4. Computer Function
Basic function performed by a computer isBasic function performed by a computer is execution of a program (code)
A program consists of a set of sequential instructions stored in memory
In its simplest form, instruction processing consists of two stepsp1. CPU reads the instruction from memory one at time
(fetch cycle)( y )2. CPU decodes and executes the instruction
(decode/execute cycle)
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4. Computer Function
Program executionProgram executionIt consists of repeating the process of fetch, and decode/execute cycles
Basic instruction cycle
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Source: Computer Organization and Structure, by W. Stallings
y
4. Computer Function
Fetch cycleFetch cyclePC register holds the next instruction to fetchCPU fetches instruction from memory location pointed by PC (Q: How many memory reads are needed to fetch the instruction ?)PC is incremented to point to the next instruction p(Q: PC = PC+??)Load current instruction into IR register (Q: WhatLoad current instruction into IR register (Q: What is the content of MAR and MBR registers at the end of fetch cycle?)
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of fetch cycle?)
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4. Computer Function
Decode/Execute cycleDecode/Execute cycleCPU decodes the fetched instructionCPU pe fo ms the eq i ed action (e g DataCPU performs the required action (e.g. Data transfer to fetch needed data and store result, data processing and control operation)data processing, and control operation)
Questions:How many memory reads are needed in execute cycle?How many memory writes?Give example of control operation instructions
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4. Computer Function
Example1: Hypothetical machine functionp ypConsider 16-bit hypothetical machine with the following
specs:I t ti 16 bit l (2b t )Instructions are 16-bit long (2bytes)Address bus is 12-bit longInstruction format provides 4 bits for the opcode and 12Instruction format provides 4 bits for the opcode and 12 bits for addressable memory Single data register called AC
l l f dPartial list of opcodes is:• ‘1H’ = 0001 = Load AC from memory location (Q: which
address?)• ‘2H’ = 0010 = Store AC to memory • ‘5H’ = 0101 = Add to AC the content of memory• ‘7H’ = Halt execution
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4. Computer Function
Example1: Hypothetical machine functionExample1: Hypothetical machine function
Characteristics of hypothetical
t
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Source: Computer Organization and Structure, by W. Stallings
computer
4. Computer Function
Example1: Hypothetical machineExample1: Hypothetical machine function1 Wh t i th i f AC IR MAR MBR
Adr. Data
... ...1. What is the size of AC, IR, MAR, MBR
and PC registers?2 What is the maximum nb of different
300H 1940H
301H 5941H
302H 2941H2. What is the maximum nb. of different opcodes?
3. What is the maximum directly dd bl ?
302H 2941H
303H 7940H
addressable space?4. Consider the memory content of the
table What is the size of the program
... ...
940H 0003H
941H 0002Htable. What is the size of the program at address 300H? Explain the execution of the program.
942H 0001H
... ...
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4. Computer Function
Example1: Hypothetical machine f ti
Adr. Data
... ...
function5. Give the content of registers PC, IR,
300H 1940H
301H 5941H
302 2941g , ,
MBR, MAR at the end of the execution of:
302H 2941H
303H 7940H
... ...
a) Fetch cycle of the 1st instruction,b) Execute cycle of the 1st instruction,
... ...
940H 0003H
941H 0005Hb) Execute cycle of the 1 instruction,c) Instruction cycle of the last instruction. 942H 0001H
... ...
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4. Computer Function
E l 1 H th ti l hiExample1: Hypothetical machine function
Adr. Data
... ...
Step 1: fetch of 1st instruction PC=300H
300H 1940H
301H 5941H
302H 2941HPC=300H• IR <--- [PC] = [300] = 1940H
St 2 t 1st i t ti
302H 2941H
303H 7940H
Step 2: execute 1st instruction• Opcode = 1H = LOAD to AC
... ...
940H 0003H
941H 0002H• Address = 940• AC <--- [940] = 0003H
942H 0001H
... ...
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4. Computer Function
Example1: Hypothetical machineExample1: Hypothetical machine function
Adr. Data
... ...
Step 3: fetch of 2st instruction PC=301H
300H 1940H
301H 5941H
302H 2941H• IR <--- [PC] = [301] = 5941H
Step 4: execute 2nd instruction
302H 2941H
303H 7940H
Step 4: execute 2 instruction• Opcode = 5H = ADD to AC• Address = 941
... ...
940H 0003H
941H 0002H• Address = 941• AC <--- AC+[941] = 0002+0003H
=0005H
942H 0001H
... ...
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0005H
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4. Computer Function
E l 1 H th ti l hiExample1: Hypothetical machine function
Adr. Data
... ...
Step 5: fetch of 3rd instruction PC=302H
300H 1940H
301H 5941H
302H 2941HPC=302H• IR <--- [PC] = [302] = 2941H
St 6 t 3 d i t ti
302H 2941H
303H 7940H
Step 6: execute 3rd instruction• Opcode = 2H = STORE AC
... ...
940H 0003H
941H 0005H• Address = 941• [941] <--- AC = 0005H
942H 0001H
... ...
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4. Computer Function
Example1: Hypothetical machine Adr. Data
... ...
functionStep 7: fetch of 4th instruction
300H 1940H
301H 5941H
302H 2941HStep 7: fetch of 4th instruction PC=303H
IR < [PC] [303] 7940H
302H 2941H
303H 7940H
• IR <--- [PC] = [303] = 7940H
Step 8: execute 4th instruction
... ...
940H 0003H
941H 0005H• Opcode = 7H = HALT program 942H 0001H
... ...
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4. Computer Function
Example 2: Program executionp gConsider a 16-bit CPU with 12-bit address bus, 16-bit data bus and single accumulator register namedbit data bus and single accumulator register named A. The CPU supports the opcodes given in table 1, the instruction format provides 4 bits for thethe instruction format provides 4 bits for the opcode and 12 bits for the operand. Consider the memory contents of table 2memory contents of table 2.
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4. Computer Function
Example 2: Program executionOpcode Mnemonic Description
0000 (0H) LDD Load to the accumulator the content of the memory y
1000 (8H) LDI Load to the accumulator the value of the operand
0001 (1H) STD Store the content of the accumulator
0010 (2H) ADD Add the content of the memory to the accumulator
1010 (AH) ADI Add the value of the operand to the accumulatorp
0011 (3H) MLD Multiply the content of the memory with the accumulator
1011( BH) MLI Multiply the value of the operand with the accumulator1011( BH) MLI Multiply the value of the operand with the accumulator
1111 (FH) HLT Stop execution
T bl 1 O d ti l li t
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Table 1: Opcodes partial list.
4. Computer Function Adr. Data
800H 080AH
Example 2: Program execution
800H 080AH
801H B010H
802H 280BHa p e og a e ecut o1. What is the range of 2’s complement
value that can be specified in the ADI
802H 280BH
803H 180CH
804H A001Ha u a a b p dinstruction?
2. Write and briefly explain the 805H 1809H
806H F80DHcorresponding assembly code of the program stored in memory location 800H
807H 080EH
808H 080EH800H.
3. What is the size of this program?4 Give the contents of registers A MAR
809H 0032H
80AH 000FH4. Give the contents of registers A, MAR,
MBR, PC, and IR after the execution of the fetch cycle of the first instruction.
80BH 0033H
80CH 0034H
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the fetch cycle of the first instruction.
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Table 2
4. Computer Function Adr. Data
800H 080AH
Example 2: Program execution
800H 080AH
801H B010H
802H 280BHp g5. Give the contents of registers A, MAR,
MBR, PC and IR after the execution of the
802H 280BH
803H 180CH
804H A001Hexecute cycle of the first instruction.
6. Give the contents of registers A, MAR, MBR PC and IR after the execution of the
805H 1809H
806H F80DHMBR, PC, and IR after the execution of the fetch cycle of the second instruction.
7. Give the contents of registers A, MAR,
807H 080EH
808H 080EHg , ,MBR, PC and IR after the execution of the second instruction.
8 Gi th t t ( l difi d
809H 0032H
80AH 000FH8. Give the memory contents (only modified
locations) after the execution of the program.
80BH 0033H
80CH 0034H
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Table 2
5. Performance Assessment
Key parameters to consider in evaluating fcomputer system performances:
SpeedSpeed CostSiSizeReliabilityPower consumption
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5. Performance Assessment
Clock speed and instructions per secondsClock speed and instructions per secondsOperations executed by the processor are governed by a system clockgoverned by a system clock
• 1 GHz processor receives 1 billion pulses per second• Processor frequency (clock rate) is fixed by the design• Processor frequency (clock rate) is fixed by the design
and physical layout of the processorThe execution of a given instruction involves aThe execution of a given instruction involves a certain number of clock cycles (from few cycles to a dozens cycles)y )When pipelining is used, multiple instructions are being executed simultaneously
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5. Performance Assessment
Instruction execution rateA common measure of performance for a processor is the rate at which instructions areprocessor is the rate at which instructions are executed, expressed as millions of instructions per second (MIPS) referred to as the MIPS ratesecond (MIPS), referred to as the MIPS rate
MIPS rate f6MIPS rate
10:
CPIf clock frequency
=×
: :
f clock frequencyCPI average clock cycles per instruction
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5. Performance Assessment
Instruction execution rateInstruction execution rateAnother common performance measure deals only with floating point instructions Floating pointwith floating-point instructions. Floating point performance is expressed as millions of floating-point operations per second (MFLOPS) defined aspoint operations per second (MFLOPS), defined as follows:
6MFLOPS rate10
number of executed floating - point operationexecution time
=×10execution time
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Summary
Computer ComponentsC t l P i U it (CPU)Central Processing Unit (CPU)MemoryInput/Output (IO) PeripheralsSystem BusesSystem Buses
CPURegisters: PC, AC, IR, MAR, MBR, and GPRALUControl unitInternal buses
Computer FunctionProgram executionFetch CycleyDecode cycle
Performance Assessment MIPS and MFLOPS
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MIPS and MFLOPS
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