EE2301 Experiment 01

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EXPERIMENT 1: INTRODUCTION TO LOGIC DESIGN

PURPOSE

The purpose of this lab is to introduce you to several aspects of digital logic design. Among thetopics discussed are documenting, building, and debugging digital logic circuits.

INTRODUCTION TO DIGITAL LOGIC

Digital logic has found widespread acceptance throughout industry in the design of many diverse

products. For instance, it is used in such devices as digital voltmeters, pocket calculators, digitalwatches, communication systems, and digital computers to name a few. In fact, digital circuitsare used extensively in nearly all fields involving electronic design. Digital logic's widespreadacceptance may be attributed to many factors, among which include its high reliability, its lowcost, and its amenability to modularization in the form of integrated circuits (IC's), resulting indesign simplification and a reduction in the number of components required to implementdevices.

Digital logic is based on the concept of discrete quantities, such as digits and alphabeticcharacters, as opposed to continuous quantities, such as voltages. The most prevalent digitallogic system in use today is the binary system. In this system there exist only two discrete

quantities or states. These states are referred to as on andoff, true andfalse, high andlow, ormost commonly as 0 (zero) and 1 (one). The main reason for this system's dominance is theadvantages it affords over other systems. Many components available for use in digital logicsystems naturally have only two states--lights, diodes, and switches, for example. Furthermore,it is much easier to distinguish between two states rather than among several. This leads to morereliable systems. Finally, systems based on binary logic are easier to implement.

The binary states could be represented in practical logic systems by a number of physicalquantities (or signals), such as an open or short circuit; an open or closed valve; the presence orabsence of fluid flow (as in fluid logic); high or low voltages; high or low pressure (as inpneumatic logic); and clockwise or counterclockwise magnetic fields (as in magnetic corememories). Many of these quantities are actually continuous in nature; hence, a range of valuesover which the quantity varies is used to represent each binary state.

The most commonly used physical binary logic system implementation, and the one that will beused in this manual, unless otherwise mentioned, is called transistor-transistor logic (TTL). Inthis system, the quantity of interest is HIGH or LOW voltage. TTL logic devices are powered bya single +5 volt power supply. Thus, all signal voltages can only range from 0 to 5 volts. Logic0 is represented by voltages between 0 and 0.8 volts, and logic 1 by voltages between 2.4 and 5


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volts. The region between 0.8 and 2.4 volts is called the threshold region. A pictorialrepresentation of this is given in Figure 1.1a. As an example, the interpretation of an arbitrarysignal in this system is illustrated in Figure 1.1b. Usually the signal in Figure 1.1b is idealized tothat shown in Figure 1.1c.

Figure 1.1 Representation of Binary Logic by Voltage Levels.

In this type of physical logic system, the higher voltages are usually chosen to correspond tologic 1 and the lower voltages to logic 0. This is called thepositive logic convention. If highervoltages are chosen to correspond to logic 0 and lower voltages to logic 1, we have the lesscommon negative logic convention. Note that the choice of logic notation (positive or negative)is merely an assignment of the two voltage levels (HIGH or LOW) to the logic states (0 or 1).Thus, either logic notation can be chosen to describe the same digital circuit. Positive logic willbe assumed throughout the rest of this manual unless otherwise mentioned.


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Two basic types of elements are used to manipulate logic signals and are also used as buildingblocks for larger more complex circuits: logic gates andflip-flops. Gates combine one or morelogic inputs and produce a specified logic output. Flip-flops are storage devices created fromgates using feedback, they can "store" logic values, i.e., they are memory devices. Circuit

networks comprised only of logic gates (no flip-flops and usually no feedback) are calledcombinational logic. (There are a few unusual cases of circuits containing feedback which arestill just combinational logic.) Circuits containing flip-flops, in addition to gates, are calledsequential circuits (networks).

Figure 1.2 Standard Gate Symbols and Truth Tables for Basic Two Input Logic Functions.


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commonly have a total of 14, 16, 18, 20, 24, 36, or 40 pins. The pin numbering scheme for 14-,16-, and 24-pin DIP IC's is shown in Figure 1.4. A notch in the package usually identifies pin 1.(Figure 1.4 shows a top view of the chips. Note that, when viewed from the top, pin 1 is to theleft of the notch and when viewed from the bottom, pin 1 is the right of the notch.)

Figure 1.4 IC Pin Numberings. (Top View)

IC's are classified not only by their logical functions, but also by theirlogic family. An IC's logicfamily is determined by the "basic circuit" upon which more complex circuits are based. Some

of the older logic families include TTL--Transistor-transistor logic, ECL--Emitter-coupled logic,MOS--Metal-oxide semiconductor logic, CMOS--Complementary metal-oxide semiconductor

logic, and I2L--Integrated-injection logic. In the lab we use a version of TTL logic called low-level Schottky, LS for short. Each logic family has its own particular characteristics andphysical binary logic system, i.e., chips from two different logic families may not havecompatible physical representations of binary 0 and 1; meaning some families of chips will usedifferent voltages to represent logic 0 and 1. Therefore, it may not be compatible to build a logiccircuit out of two or more families of chips.

Specification sheets for ICs list pertinent information regarding device use. These sheets areavailable in printed data manuals, but most manufacturers of ICs now have these specifications

available on the web. For example, the Texas Instrument web site for logic families is

http://focus.ti.com/logic/docs/logichome.tsp?sectionId=450&familyId=1&DCMP=TIHomeTracking&HQS=Other+OT+home_p_logicl

This site has specification sheets for TIs logic families. For example, if you follow the pathData Sheets, LS(under select a logic family), SN74LS00 and Download(under theDatasheet section), you will download a data sheet in pdf format for the 74LS00 IC. It is called


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a quad two-input NAND gate package. This IC contains four, two-input NAND gates, as thename implies. The 54 series number (military grade), 5400, or the 74 series number(commercial grade), 7400 indicate that the chip belongs to the TTL logic family. The pinassignments for the gate inputs, gate outputs, supply voltage, and ground pins are shown at the

top left for the 14-pin dual-in-line (DIP) package, the J package. (All the chips used in the 2301lab are in DIP packages, either 14-pin or 16-pin.) This chip is also available in other packages,e.g., a flatpack package, the fk package. (Another web site containing information on TTLchips is www.datasheet.in. The LS parts are in pages 7 and 8 of those parts with part numberstarting with 7.)

In addition to pin assignments, the specification sheet gives recommended operating parametersand characteristics for the chip. For example, we see in the Guaranteed Operating Ranges tablethat, for proper operation, the commercial grade 7400 chip's supply voltage, VCC, should range

between 4.75 and 5.25 V, and its temperature between 0 to 70 C. This table also gives themaximum output current, IOH, that can be sourced by a gate output when it is HIGH, and the

maximum output current, IOL, that can be sinked by a gate output when it is LOW. Note thesigns on these current values. By convention, current is positive if it is flowing into a terminal soIOH is a negative 0.4 mA and IOL is a positive 8.0 mA.

Also from the DC Characteristics over Operating Temperature Range table, we see that an inputsignal exceeding 2.0 volts, VIH, is guaranteed to be interpreted as HIGH, and one not exceeding

0.8 volts, VIL, as LOW. Similarly, an output is guaranteed to be at least 2.7 volts, VOH, for a

HIGH output and less than 0.5 volts, VOL, for a LOW output, when sinking 8.0 mA of current.

This table also specifies the current flow into an input when it is HIGH, IIH, and when it is

LOW, IIL. The output short circuit current IOS is the output current that flows from a HIGH

output that is connected directly to ground. The HIGH supply current ICCH is the total power

supply current per IC that flows when the outputs of the chip are HIGH. Similarly, ICCL is the

supply current per IC which flows when the outputs are LOW.

Another parameter of interest for gates in a logic family is the maximumfan-out. The maximumfan-out is the maximum number of gate inputs, within the same logic family, that can be drivenfrom (connected to) a gate output can drive before the output becomes overloaded, i.e., itproduces a voltage level outside a range for a valid logic level. For TTL logic, the maximumfan-out is equal to the ratio of IOL to the absolute value of IIL, so it is 20 for the LS family.

The minimum and maximum values given in a data sheet are guaranteed over the entiretemperature and supply voltage range indicated for the device. This implies that the device canoperate reliably under variable temperatures and supply voltages that occur in practical systems.

Finally, the data sheets specify the AC characteristics of the gates. When the input voltage to alogic gate changes, it takes time for this change to propagate to the output. The propagationdelay time is the time required for the output of a device to change after receiving an inputsignal. The turn-off delay tPLH is the time required for the gate output to switch from LOW to


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HIGH, measured relative to the time the gate input changes. The turn-on delay tPHL is the time

required for the gate output to switch from HIGH to LOW, measured relative to the time the gateinput changes.

CIRCUIT CONSTRUCTION

In order to protect the IC's pins and facilitate wiring, the IC's you use will be mounted in abreadboard. An extraction tool, available in the lab, should always be used to remove an ICfrom its socket; trying to remove them by hand often results in bent and broken IC pins.

All IC's should be mounted with the same orientation to facilitate wiring and debugging. It isnot advisable to reverse the orientation of some IC's to minimize wire lengths. Wiring is doneon the top side of the breadboard, i.e., on the same side that the ICs are inserted; hence, the

numbering scheme shown in Figure 1.4 gives the correct view.

Appendix A describes the functionality of the logic box available in the lab and how to connectthe logic box to the breadboard. The breadboard and ICs used in the experiments are available inlab kit available through the bookstore.

You should begin connecting your circuits by wiring power, ground, and all unused inputs ofgates (for gates having more inputs than needed) to an appropriate constant source. This makesthe first connections those that are least likely to change during debugging. Try to keep thewires as close to the surface of the board and as short as possible. Try not to cross too manywires, so that tracing and removal of the wires will be easier. Furthermore, a color code scheme

will greatly simplify debugging the circuit later. For example, all power supply wires could bered, all ground wires black, etc.

When you have finished wiring, examine each pin of each IC to verify its connection. Check allpins without any wires attached to see if they really should have no connection. Be sure todouble-check all power connections before applying power to the circuit. The 5 volt powersupply provided is short-circuit protected, so that shorting the power supply will merely shut itdown until the short circuit is removed. Thus, there is no need to worry about getting a shockfrom 5 volts. However, you should be concerned about damaging IC's by improper connections!The one sure way to irreparably damage an IC is to reverse power and ground. Most IC's havetheir ground pin in the lower-left hand corner and power in the upper right-hand corner, whenviewed from the bottom. Thus mounting an IC backwards will blow it out. But be alert, someIC's have power and ground in nonstandard locations.

Sometimes you will not damage an IC by shorting one of its outputs to ground. However, whena TTL output trying to maintain a LOW level is shorted to the 5 volt power supply, damage willresult. Shorting the outputs of CMOS gates to each other, power, or ground for a short period oftime is not damaging, but permanent damage may result after a few minutes. Also, if a signal is


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applied to a CMOS gate input that does not have its power and ground connected, damage mayresult.

Although TTL inputs may be tied directly to ground, they should never be connected directly to

the +5 volt power supply. If by some misfortune the voltage level at some input terminalexceeds that at the power supply terminal, the chip will be destroyed. Use either a logicbox TTLoutput to provide a HIGH level to a TTL input, or wire up a gate on your circuit to provide afixed HIGH level signal at its output to supply the TTL input. (The logic box TTL outputscontain a current limiting resistor in the connection to +5 volts.)

Above all, keep your wiring neat. A neatly wired circuit is much easier to debug and tends to bemore reliable. With messy wiring, removing or inserting one wire, besides being a difficultchore, can have unpredictable and untraceable effects--it can loosen other wires tangled with it inthe mess. In a neatly wired circuit, you (and the laboratory instructor) at least have a chance ofsuccessfully debugging the circuit.

DOCUMENTATION

The most important prerequisite for good design is good documentation. You should design anddocument your system completely before you build it, not while you build it. Thedocumentation should include complete circuit diagrams of your system, indicating the partnumbers, pin numbers, and physical locations of all the components.

Your documentation should generally consist of five parts: a block diagram, logic diagram, chiplayout, state diagram, and word description. The block diagram gives an overview of thefunctional modules comprising a complex system, while logic diagrams, in conjunction with thechip layout diagram, completely detail the system's construction. State diagrams aid inunderstanding any complex sequential control circuitry. Finally, the word description shouldconcisely explain the operation of the system and any assumptions made.

Not all five parts of the documentation are essential for every circuit. For example, simplecircuits containing less than 10 IC's may not need block diagrams. The circuit's operation couldreadily be assimilated from its logic diagram. Also, state diagrams are definitely not applicableto combinational circuits.

Block Diagrams

In complex systems involving many IC's, a block diagram is essential to attain a fundamentalunderstanding of the system's operation. It must indicate the major subsystems of the system,and the data and control paths between them. In very large systems, additional block diagramsof the individual subsystems may also be required, but there should always be one block diagramillustrating the entire system.


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The blocks in the diagram indicate functional modules of the system, not the individualcomponents that comprise it. For example, a 16-bit register implemented using four 4-bitregisters should be considered as one block rather than four individual blocks. It is looked uponas a 16-bit register by all the other modules in the system. The individual components

comprising it are not individually accessible by the other modules.

The separation of the system into major subsystems is not a well-defined process. There aremany ways to partition a system into subsystems. But essentially the partitioning reduces to acompromise between too much and too little detail. Too much detail, and the overall operationof the system is lost in a mass of details. Too little detail, and the fundamental operation of thesystem is inadequately depicted.

Figure 1.5 illustrates a block diagram. The double arrows indicate buses, i.e., multiple lines usedto carry signals, data or control, between modules. It is essential that the flow of control anddata between modules in block diagrams be indicated clearly. With control and status lines, theflow is usually in one direction, but lines carrying data, especially buses, are often bidirectional,i.e., the flow can be in both directions.

Figure 1.5 Example Block Diagram.

Logic Diagrams and Chip Layout

The logic diagrams and chip layout should give all the information needed to construct thesystem. The logic diagram should indicate every connection between the components. The chiplayout diagram should indicate the position, a reference number (such as U1, U2, etc.), and thepart number of each component used in the circuit. Figure 1.6 illustrates a logic diagram of a


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circuit. A corresponding chip layout diagram is shown in Figure 1.7. Note that NC stands for noconnection on the logic diagram.

On the logic diagram, the gates and flip-flops used in the circuit should be shown using the

standard symbols presented in the introduction to this lab. Each gate and flip-flop should belabeled with the reference number and part number of the IC containing it. In addition, the inputand output lines of the gates and flip-flops should be labeled with the corresponding pin numberson the IC. The gate number on the IC should also be labeled.

Figure 1.6 Logic Diagram for a Serial Adder.


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Figure 1.7 Chip Layout Diagram for a Serial Adder.

Other IC chips should be drawn as rectangles with labels inside denoting their reference and partnumbers. Also the names of the input and output pins should be labeled within the rectangle. Aswith gates and flip-flops, the input/output lines should be labeled with their corresponding pinnumbers on the IC to facilitate wiring the circuit. Note that normally power and ground pins forchips are not included in logic diagrams. It is assumed that you can look up their locations fromthe specification sheets of the IC's.

All input and output lines to the circuit must be labeled. It may be helpful to label other lines.

DEBUGGING

A circuit may sometimes work properly the first time it is turned on, but more likely it will notand, hence, will require debugging. Before power is applied to the circuit, the circuit should bechecked to see that it is wired correctly. Improper connections may irreparably damage thechips. (An ohmmeter can be used to check connections if available.) If a connection is missing,check to make sure that it is not simply the result of a misconnected wire by checking the routingof all the other wires leaving the two connection points involved. If, after you apply power,sparks fly, you smell something burning, or one of the chips becomes hot, immediately shut thepower off and recheck your circuit. Be aware that typically you will have prepared severalcircuits for the next week's lab and all are activated whenever power is applied.

Two types of errors will be detected in debugging: wiring errors and design errors. Both typesof errors may be detected by working backwards in the circuit from some point where theerroneous behavior was discovered. If a signal at any point does not have the expected behavior,


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then work back another level. Do not try to guess the trouble source; such a procedure usuallyjust leads to confusion since the problem is never where you expect it to be.

In the case of sequential circuits, the first thing you should do upon powering up is to get the

circuit into a known state and then examine all signals for their proper logic values. The nextcheck is to single-step the system clock and check that the proper state changes are made. Beparticularly alert to glitches in the combinational logic of your circuit that are clocked into theflip-flops. Finally you can debug the system at full speed.

The most common wiring errors are omitted and misplaced wires. An omitted wire results in afloating input to a device. A floating TTL input will show a voltage between 1.6 to 1.8 volts, inthe threshold region. Misplaced wires sometimes result in short circuits between outputs. Twoshorted TTL outputs trying to maintain opposite logic levels will produce an output voltage ofabout 0.6 volts and may cause damage to one of the driving gates.

The most common design errors involve floating unused inputs. Quite often when an input is notused, the designer forgets to make any connection to it. The result is usually an effective logic 1in TTL circuits however, you cannot depend on this and it is very poor design practice to leavean input unconnected. In CMOS circuits, the effective logic value of the input is indeterminate.Hence all unused inputs should be tied to an appropriate logic source.


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PRELAB

1. Read all of Lab 1 and Appendices A, B and C regarding the logicbox, breadboard,

interfacing the breadboard to the logicbox, oscilloscope, WaveStar software, and functiongenerator.

2. To acquire proficiency in the documentation of logic circuits, draw a complete logicand chip layout diagram for the logic circuit below (Figure 1.8). It is not essential that youunderstand the operation of this circuit, only the procedures for documenting it.

First, construct a complete logic diagram, labeling each gate with its reference and part number.Also be sure to indicate the pin numbers and double check to make sure they are labeledcorrectly. Next, construct a chip layout diagram. You need to consult the pin assignmentdiagrams in the data sheets to determine the chip sizes. Try to arrange the chips in an orderly

fashion so that those having connections between chips are as near as possible. (Since thebreadboards you will use in lab require that the chips be arranged in a single vertical column, usethis arrangement for this exercise.) Be sure to label each chip with its reference and partnumber.

If you have any questions regarding the procedures involved in drawing a logic diagram ordrawing a chip layout diagram, they can be answered in lab. Make sure to at least attempt tocomplete these drawings before lab, if no effort is evident, then no credit will be given.

Note when constructing the chip layout, you must adhere to the following restrictions:1) AND gates are available in one 74LS08 chip,2) XOR gates are available in one 74LS86 chip,3) Inverters are available in one 74LS04 chip, but4) The OR gate must be constructed using one AND gate and inverters as needed.

OUT1

OUT2

XY

Z

Figure 1.8 Schematic Diagram of Logic Circuit for Prelab.


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PROCEDURE

Before performing the procedures listed below, read the report section of the experiment toassure you make all required measurements and record all required data.

A. Documentation Check

1. Have your TA check your diagrams to ensure that they were done correctly. If youhave any questions regarding any aspect of the diagrams, ask your TA now.

B. Start-up

1. Familiarize yourself with the front panel controls on the oscilloscope available to you.

Refer to Appendix B on the Tektronix TDS360 oscilloscope for their functions. Before takingany measurements on the oscilloscope, reset it to its factory defaults, as outlined in Appendix B,Initial Turn-on Procedure.

2. Connect the oscilloscope probe to the signal generator. You do not need to connectthe generator to the logic box. Connect the probe directly to the red banana plug on the cablefrom the function generator and the probe's alligator clip to the black banana plug.

3. Set the function generator to produce a 5 volt amplitude, 1 kHz sinusoidal wave withno offset. The generator is activated by depressing the LINE pushbutton switch. The generatorshould be in the "normal" operating mode, indicated by the LED at the upper left hand corner. Ifnot, depress the pushbutton switch immediately below until normal mode is selected. Engage

the sine function pushbutton. Depress the FREQUENCY button and press the RANGE rockerswitch until the LED next to kHz is lit and the decimal point is one digit from the left in thedisplay. Adjust the FREQUENCY vernier until the display reads 1.00 kHz. Make sure theDUTY CYCLE vernier control is pressed in. Press the AMPLITUDE button and adjust theAMPLITUDE control until the display reads 5.00 volts. Make sure the offset switch is in its 12o'clock position. None of the attenuation or output mode pushbuttons should be engaged.

The HORIZONTAL SCALE and VERTICAL SCALE on the scope should be adjusted to

produce an appropriate trace. Since the frequency of the sine wave is 1 kHz, 500 s might be agood setting for the HORIZONTAL SCALE. (Recall 1 kHz corresponds to a period of 1/1000sec. = 1 ms) The five-volt amplitude of the waveform suggests that a 2 VOLTS/DIV for the

VERTICAL SCALE might be a good setting for VOLTS/DIV.

Also, it is a good idea to establish a ground potential reference level. To do this, press theVERTICAL MENU button and then press the softkey labeled COUPLING, on the bottom-left ofthe screen. A menu will then appear along the right side of the screen with three differentoptions, DC, AC, and GND, select GND. Adjust the trace by turning the VERTICALPOSITION knob so that the trace is at the desired ground reference level--usually the center ofthe screen. Each time the VOLTS/DIV dial is changed, a new ground reference level should be


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established. Observe how the trace moves vertically as the VOLTS/DIV dial is changed. TheHORIZONTAL POSITION knob may be used to center the trace horizontally on the display. Besure to return the coupling to DC to allow the DC input signals into the vertical amplifier.

Use the WaveStar software to acquire a picture of the oscilloscope display. This procedure isoutlined in Appendix B. After obtaining a satisfactory screen image, cutandpaste it into yourfinal report. Be sure to indicate the ground potential on the display. What is the peak to peakvoltage of the waveform? What is its period? Show how you arrived at these figures from thescope display and dial settings.

4. Add a 5 volt offset to the sine wave signal by depressing the OFFSET pushbutton onthe function generator and adjusting the OFFSET control until the display reads 5 volts. Recordthe display and appropriate vernier settings on the scope for both DC and AC couplings. Thesesettings can be found under the VERTICAL MENU. Reconcile the differences between thetraces under DC and AC coupling. Be sure to record your ground (0 volts) reference position.

5. Observe a 5 Hz triangle waveform with a 5 volt amplitude, 50% duty cycle, and nooffset under both AC and DC coupling. To view this, restore the OFFSET control to its 12o'clock position. Depress the triangle waveform pushbutton. Engage the FREQUENCYpushbutton and adjust the FREQUENCY vernier until the LED displays 5.00 Hz. You will needto adjust the HORIZONTAL SCALE knob until a clear triangle waveform appears. Note thatthe frequency of this waveform is much smaller than the previous 5 kHz wave. Again reconcilethe differences between the DC and AC coupled displays of the signal.

6. Set the function generator to produce a 10 kHz sine wave with a 5 volt amplitude,

50% duty cycle, and no offset. Set the HORIZONTAL SCALE to 50s. Adjust the TRIGGERLEVEL knob and observe the effects on the display. Also try pressing the TRIGGER MENU

pushbutton and then the SLOPE softkey at the bottom of the screen. Next change the EDGESLOPE control along the right side of the screen. How do these controls determine on whichpart of the cycle of a periodic input signal to trigger, i.e., where in the cycle the trace begins?

C. Logic Box Evaluation

1. Connect the logic box to the power supply, then connect the cable from the logic boxto the breadboard. If you have any questions about how this is done, consult your TA.

2. Insert a single 74LS00 chip on the breadboard. Connect power and ground to the chipand connect three of the four 2-input NAND gates as shown in the circuit below. Finally connect

the clock output from the logic box to the circuit input. Attach one probe from the oscilloscopeto the circuit input and the other probe to the circuit output. (Make sure that the groundconnector of the probe is connected to the logic ground i.e., the 74LS00 ground pin, not thepower supply ground.) Using the oscilloscope capture the circuit input and output waveforms fortwo different clock signals by selecting two different switch positions. Be sure to indicate theswitch position for each waveform.


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3. Attach an oscilloscope probe to Counter Output #3 from the logic box. Place thecounter in the free-running mode and capture the output waveform for both AC and DCcoupling. Place the counter in single-step mode and again capture the output waveform for bothAC and DC coupling.


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EXPERIMENT 1-- INTRODUCTION TO LOGIC DESIGN AND LAB

EQUIPMENT

FINAL REPORT

I. Turn in your Logic and Chip Layout Diagrams.

II. Measurements

a) Sketch the sine waveform observed in part B.3.

VOLTS/DIV_________________ TIME/DIV_________________

b) What is the peak to peak voltage of the waveform? What is its period? What is itsfrequency? Indicate how you determined these values from the above sketch.


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c) Record the waveforms observed in part B.4.

DC Coupling

AC Coupling


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d) The waveforms observed using AC and DC coupling are different. Explain why.

e) Sketch the waveforms observed on the oscilloscope in part B.5.

DC Coupling


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AC Coupling

f) Why is the AC coupled trace distorted?

g) From your observations in part B.6, explain how the TRIGGER LEVEL knob and theEDGE SLOPE softkeys determine where in the cycle of a periodic input signal the scope beginsthe trace.


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III. Analysis of Logic Box and Beardboard

a) Sketch the input and output waveforms obtained in part C.2 for the two different inputfrequencies.


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b) Sketch the circuit you constructed showing the pin numbers on each gate.

c) What are the frequencies of the input and output waveforms for the two inputfrequencies you selected? How do the input and output waveforms differ? Is this what wasexpected?

d) Sketch the waveforms obtained in part C.3. Identify the waveforms, i.e., counter wasfree-running or single stepping and the vertical channel of the scope was in DC or AC mode.


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e) Does the counter output behave as expected and what is its frequency? What voltageswere obtained at the counter output for a logic 0 and logic 1? (Remember that we are using apositive logic convention.)


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f) Explain how the counter output might be used to obtain the table of combinations for acombinational logic circuit.

EE2301 Experiment 01

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