Ee2258 Lab Manual New

8/13/2019 Ee2258 Lab Manual New

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EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

Ex. No.:1 STUDY OF BASIC DIGITAL ICS.

Date:

AIM:

To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR gates,J !!, R" !!, D!!#

AARATUS RE!UIRED:

S".No Na#e o$ t%e A&&a'at() S&e*+$+*at+o, !(a,t+t-

$# Digital IC trai%er &it $'# AND gate IC ()*+ $# OR gate IC ()' $)# NOT gate IC ()*) $

# NAND gate IC ()** $.# NOR gate IC ()*' $(# EX-OR gate IC ()+. $+# Co%%ecti%g /ires As re0uired

TEORY:

AND ate:

A% AND gate is the 1hysical reali2atio% of logical 3ulti1licatio% o1eratio%# It is a% electro%ic

circuit /hich ge%erates a% out1ut sig%al of 4$5 o%ly if all the i%1ut sig%als are 4$5#

OR ate:

A% OR gate is the 1hysical reali2atio% of the logical additio% o1eratio%# It is a% electro%ic circuit

/hich ge%erates a% out1ut sig%al of 4$5 if a%y of the i%1ut sig%al is 4$5#

NOT ate:

A NOT gate is the 1hysical reali2atio% of the co31le3e%tatio% o1eratio%# It is a% electro%ic

circuit /hich ge%erates a% out1ut sig%al /hich is the reverse of the i%1ut sig%al# A NOT gate is

also &%o/% as a% i%verter because it i%verts the i%1ut#

NAND ate:A NAND gate is a co31le3e%ted AND gate# The out1ut of the NAND gate /ill be 4*5 if all the

i%1ut sig%als are 4$5 a%d /ill be 4$5 if a%y o%e of the i%1ut sig%al is 4*5#

AND GATE

LOGIC DIAGRAM:

CA6E IN"TIT7TE O! TEC8NO9O:; 6age $


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A

Y0A.B

B

IN DIAGRAM OF IC 38 :

CIRCUIT DIAGRAM:

TRUT TABLE:

S".No INUT OUTUTA B Y0A.B

$# * * *'# * $ *# $ * *)# $ $ $

NOR ate:

A NOR gate is a co31le3e%ted OR gate# The out1ut of the OR gate /ill be 4$5 if all thei%1uts are 4*5 a%d /ill be 4*5 if a%y o%e of the i%1ut sig%al is 4$5#

CA6E IN"TIT7TE O! TEC8NO9O:; 6age '


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E4OR ate:

A% E


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LOGIC GATES:

$# Co%%ectio%s are give% as 1er the circuit diagra3

'# !or all the ICs (th1i% is grou%ded a%d $)th1i% is give% @ su11ly#

# A11ly the i%1uts a%d verify the truth table for all gates#

FLIFLOS:

1. Give connections as per the circuit diagram.

2. Inputs are given to the circuit making high 1 i.e. +5 V or + Vcc

supply and for lo ! i.e. G"#$ clock input is given from the I%

trainer kit.

&. 'he (inary input !!$ !1$ 1!$ 11 are given and the outputs are

o(served.

). *epeat the same procedure for ,$ #$ and ' -lip-lops and verify the

truth ta(le.

CA6E IN"TIT7TE O! TEC8NO9O:; 6age


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NOT GATE

LOGIC DIAGRAM:

AAA Y0A


CIRCUIT DIAGRAM:

TRUT TABLE:

S".No INUT OUTUT

A Y0A

$# * $

CA6E IN"TIT7TE O! TEC8NO9O:; 6age .


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'# $ *


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'# * $ $

# $ * $

)# $ $ *



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NOR GATE

LOGIC DIAGRAM:


CIRCUIT DIAGRAM:

TRUT TABLE:

CA6E IN"TIT7TE O! TEC8NO9O:; 6age $*


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S".No INUT OUTUT

A B Y06AB7

$# * * $

'# * $ *

# $ * *

)# $ $ *

CA6E IN"TIT7TE O! TEC8NO9O:; 6age $$


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E4OR GATE

LOGIC DIAGRAM:

IN DIAGRAM OF IC 8= :

C

IRCUIT DIAGRAM:

TRUT TABLE:

S".No INUT OUTUT

CA6E IN"TIT7TE O! TEC8NO9O:; 6age $'


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A B Y0A B

$# * * *

'# * $ $

# $ * $)# $ $ *



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RS FLI FLO

LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CARACTERISTIC TABLE:

CLOC

ULSE

INUT RESENT

STATE 6!7

NE4T

STATE6!17

STATUS

S R

1 3 3 3 3 No *%a,e2 3 3 1 1 No *%a,e

; 3 1 3 3 Re)et

3 1 1 3 Re)et

5 1 3 3 1 Set

= 1 3 1 1 Set

1 1 3 4 U,>ete'#+,e>

8 1 1 1 4

CA6E IN"TIT7TE O! TEC8NO9O:; 6age $)


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TRUTH TABLE:

R S ! !

3 3 3 1

3 1 1 3

1 3 3 1

1 1 1 1



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D FLI FLO

LOGIC SYMBOL:

CIRCUIT DIAGRAM:


CLOC

ULSE

INUT

D

RESENT

STATE 6!7

NE4T

STATE6!17

1 3 3 3

2 3 1 3

CA6E IN"TIT7TE O! TEC8NO9O:; 6age $.


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9 FLI FLO

LOGIC SYMBOL:

CIRCUIT DIAGRAM:


CLOC

ULSE

INUT RESENT

STATE 6!7

NE4T

STATE6!179 1 3 3 3 3

2 3 3 1 1

; 3 1 3 3

3 1 1 3

5 1 3 3 1

= 1 3 1 1

1 1 3 1

CA6E IN"TIT7TE O! TEC8NO9O:; 6age $+


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8 1 1 1 3

TRUTH TABLE:

9 ! !

3 3 1 3

3 1 1 31 3 3 1

1 1 1 1



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T FLI FLO

LOGIC SYMBOL:

CIRCUIT DIAGRAM:


CLOC

ULSE

INUT

T

RESENT

STATE 6!7

NE4T

STATE6!17

1 3 3 3

2 3 1 3

; 1 3 1

1 1 3

TRUTH TABLE:

T ! !

CA6E IN"TIT7TE O! TEC8NO9O:; 6age '*


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3 1 1

1 3 1

CA6E IN"TIT7TE O! TEC8NO9O:; 6age '$


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RESULT:

Thus the truth table of all the basic digital ICs a%d the fli1 flo1s are verified#

ALF ADDER

TRUT TABLE:

S.NoINUT OUTUT

A B S C

1. 3 3 3 3

2. 3 1 1 3

;. 1 3 1 3

. 1 1 3 1

DESIGN:

!ro3 the truth table the e


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The first three o1eratio%s 1roduce a su3 of /hose le%gth is o%e digit, but /he% the lasto1eratio% is 1erfor3ed the su3 is t/o digits# The higher sig%ifica%t bit of this result is called acarry a%d lo/er sig%ifica%t bit is called the su3#

ALF ADDER:

A co3bi%atio%al circuit /hich 1erfor3s the additio% of t/o bits is called half adder# The i%1utvariables desig%ate the auge%d a%d the adde%d bit, /hereas the out1ut variables 1roduce the su3a%d carry bits#

FULL ADDER

TRUT TABLE:

S.NoINUT OUTUT

A B C SUM CARRY

1. 3 3 3 3 3

2. 3 3 1 1 3

;. 3 1 3 1 3

. 3 1 1 3 1

5. 1 3 3 1 3

=. 1 3 1 3 1

. 1 1 3 3 1

8. 1 1 1 1 1

DESIGN:



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A co3bi%atio%al circuit /hich 1erfor3s the subtractio% of three i%1ut bits is called full

subtractor# The three i%1ut bits i%clude t/o sig%ifica%t bits a%d a 1revious borro/ bit# A full

subtractor circuit ca% be i31le3e%ted /ith t/o half subtractors a%d o%e OR gate#

CARRY

CARRY 0 AB AC BC

CIRCUIT DIAGRAM:

ALF SUBTRACTOR

TRUT TABLE:

S.NoINUT OUTUT

A B DIFF BORR

1. 3 3 3 3

2. 3 1 1 1

CA6E IN"TIT7TE O! TEC8NO9O:; 6age '.


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;. 1 3 1 3

. 1 1 3 3

DESIGN:



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CIRCUIT DIAGRAM:

-a1 for DI!!ERENCE -a1 for =ORRO>

DIFFERENCE 0 AB AB BORRO 0 AB

FULL SUBTRACTOR

TRUT TABLE:

S.NoINUT OUTUT

A B C DIFF BORR

1. 3 3 3 3 3

CA6E IN"TIT7TE O! TEC8NO9O:; 6age '+


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CIRCUIT DIAGRAM:



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RESULT:

Thus the desig% of the half adder, half subtractor, full adder F full subtractor circuits /as do%e

a%d their truth tables /ere verified#

BINARY TO GRAY:

LOGIC DIAGRAM:

TRUT TABLE:

INUTS6BINARY CODE7 OUTUTS6GRAY CODE7B; B2 B1 B3 G; G2 G1 G3

3 3 3 3 3 3 3 3

3 3 3 1 3 3 3 1

3 3 1 3 3 3 1 1

3 3 1 1 3 3 1 3

3 1 3 3 3 1 1 3

3 1 3 1 3 1 1 1



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3 1 1 3 3 1 3 1

3 1 1 1 3 1 3 3

1 3 3 3 1 1 3 3

1 3 3 1 1 1 3 1

1 3 1 3 1 1 1 1

1 3 1 1 1 1 1 3

1 1 3 3 1 3 1 3

1 1 3 1 1 3 1 1

1 1 1 3 1 3 3 1

1 1 1 1 1 3 3 3

Ex. No.:; DESIGN AND IMLEMENTATION OF CODE CON


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the bi%ary code# The gray code is ofte% used i% digital syste3s because it has the adva%tage thato%ly o%e bit i% the %u3erical re1rese%tatio% cha%ges bet/ee% successive %u3bers#

GRAY TO BINARY:

The "= of the :ray code re3ai%s u%cha%ged i% the bi%ary code the re3ai%i%g bits are

obtai%ed by EX H OR i%g the corres1o%di%g gray code bit a%d the 1revious out1ut bi%ary bit#

BCD TO E4CESS ;:

Code co%verter is a co3bi%atio%al circuit that tra%slates the i%1ut code /ord i%to a%e/corres1o%di%g /ord# The e


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GRAY TO BINARY

LOGIC DIAGRAM:

TRUT TABLE:

INUTS6GRAY CODE7 OUTUTS6BINARY CODE7

G; G2 G1 G3 B; B2 B1 B3

3 3 3 3 3 3 3 3

3 3 3 1 3 3 3 1

3 3 1 1 3 3 1 3

3 3 1 3 3 3 1 1

3 1 1 3 3 1 3 3

3 1 1 1 3 1 3 1

3 1 3 1 3 1 1 3



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3 1 3 3 3 1 1 1

1 1 3 3 1 3 3 3

1 1 3 1 1 3 3 1

1 1 1 1 1 3 1 3

1 1 1 3 1 3 1 1

1 3 1 3 1 1 3 3

1 3 1 1 1 1 3 1

1 3 3 1 1 1 1 3

1 3 3 3 1 1 1 1

CA6E IN"TIT7TE O! TEC8NO9O:; 6age (


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E4CESS ; TO BCD CODE CON


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ODD/E


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Ex. No.: ARITY GENERATOR AND CECER

Date:

AIM:

To desig% a%d verify the truth table of a three bit OddLEve% 6arity ge%erator a%d chec&er#

AARATUS RE!UIRED:


$# Digital IC trai%er &it $

'# NOT gate IC ()*) $

# EX-OR gate IC ()+. $

)# Co%%ecti%g /ires As re0uired

TEORY:

A 1arity bit is used for the 1ur1ose of detecti%g errors duri%g tra%s3issio% of bi%aryi%for3atio%# A 1arity bit is a% e


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ARITY CECER:

ODD ARITY CECER:

TRUT TABLE:

S.No

INUT

6 $o(' +t #e))ae

Re*e+e> 7

OUTUT

6a'+t- e''o' *%e*7

A B C 4

1. 3 3 3 3 1

2. 3 3 3 1 3

;. 3 3 1 3 3

. 3 3 1 1 1

5. 3 1 3 3 3

=. 3 1 3 1 1

. 3 1 1 3 1

8. 3 1 1 1 3

. 1 3 3 3 3

13. 1 3 3 1 1

11. 1 3 1 3 1

12. 1 3 1 1 3

1;. 1 1 3 3 1

1. 1 1 3 1 3

15. 1 1 1 3 3

1=. 1 1 1 1 1

CA6E IN"TIT7TE O! TEC8NO9O:; 6age ))


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BCD TO DECIMAL DECODER:

PIN DIAGRAM FOR IC 74147:

LOGIC DIAGRAM FOR ENCODER:

Ex. No.:5 ENCODER AND DECODER

CA6E IN"TIT7TE O! TEC8NO9O:; 6age )+


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Date:

AIM:

To desig% a%d i31le3e%t e%coder a%d decoder usi%g logic gates a%d study of IC ()) a%d IC

()$)(#

AARATUS RE!UIRED:



'# & I0 ""# G'3 I% /)1! '

# 4* G'3 I% /)&2

)# "4' G'3 I% /)!) $

# Co%%ecti%g /ires As re0uired

TEORY:

ENCODER:

A% e%coder is a digital circuit that 1erfor3s i%verse o1eratio% of a decoder# A% e%coder

has '% i%1ut li%es a%d % out1ut li%es# I% e%coder the out1ut li%es ge%erates the bi%ary code

corres1o%di%g to the i%1ut value# I% octal to bi%ary e%coder it has eight i%1uts, o%e for each octal

digit a%d three out1ut that ge%erate the corres1o%di%g bi%ary code# I% e%coder it is assu3ed that

o%ly o%e i%1ut has a value of o%e at a%y give% ti3e other/ise the circuit is 3ea%i%gless# It has

a% a3biguity that /he% all i%1uts are 2ero the out1uts are 2ero# The 2ero out1uts ca% also be

ge%erated /he% D* G $#

DECODER:

A decoder is a 3ulti1le i%1ut 3ulti1le out1ut logic circuits /hich co%verts coded i%1ut

i%to coded out1ut /here i%1ut a%d out1ut codes are differe%t# The i%1ut code ge%erally has

fe/er bits tha% the out1ut code# Each i%1ut code /ord 1roduces a differe%t out1ut code /ord i#ethere is o%e to o%e 3a11i%g ca% be e


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i Co%%ectio%s are give% as 1er circuit diagra3#

ii 9ogical i%1uts are give% as 1er circuit diagra3#

iii Observe the out1ut a%d verify the truth table#


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CIRCUIT DIAGRAM:

A)-,*%'o,o() R+&&"e *o(,te'

TRUT TABLE:

A B C D

* * * ** * * $* * $ ** * $ $* $ * ** $ * $* $ $ ** $ $ $$ * * *$ * * $$ * $ *

$ * $ $$ $ * *$ $ * $$ $ $ *$ $ $ $



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S-,*%'o,o() R+&&"e *o(,te':

TRUT TABLE:

A B C D

* * * ** * * $* * $ ** * $ $* $ * ** $ * $* $ $ ** $ $ $$ * * *$ * * $$ * $ *$ * $ $

$ $ * *$ $ * $$ $ $ *$ $ $ $

CA6E IN"TIT7TE O! TEC8NO9O:; 6age )


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ROCEDURE:

$# Co%%ect the circuit as 1er the circuit diagra3#

'# Note the out1ut a%d verify the cou%ter o1eratio%#


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SISO

CIRCUIT DIAGRAM:

TRUT TABLE:SISO

Data i%1ut G $$**C"o* Se'+a" I,&(t Se'+a" O(t&(t

* * *

) $ $

+ $ $

$' * *

$. * *

IO

CIRCIT DIAGRAM:



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Ex. No.: SIFT REGISTERS

Date:

AIM:

To i31le3e%t the follo/i%g shift register usi%g fli1 flo1

I# "I6O

II# "I"O

III# 6I"O

I# 6I6O

AARATUS RE!UIRED:



'# IC ()() $

# Co%%ecti%g /ires As re0uired

TEORY:

A register is used to 3ove digital data# A shift register is a 3e3ory i% /hich i%for3atio% is

shifted fro3 o%e 1ositio% i% to a%other 1ositio% at a li%e /he% o%e cloc& 1ulse is a11lied# Thedata ca% be shifted either left or right directio% to/ards right or to/ards left# A shift register ca%

be used i% four /ays de1e%di%g u1o% the i%1ut i% /hich the data are e%tered i% to a%d ta&es out

of it# The four co%figuratio% are give% as

"erial i%1ut H "erial out1ut

6arallel i%1ut H "erial out1ut

"erial i%1ut H 6arallel out1ut

6arallel i%1ut H 6arallel out1utR" or J fli1 flo1 are used to co%struct shift register have D fli1 flo1 is used for co%structi%g

shift register#

TRUT TABLE:



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C"o* a'a""e" I,&(t a'a""e" O(t&(t

A B C D !A !B !C !D

3 3 3 3 3 3 3 3 3

1 1 1 3 1 1 1 3 1

SIO

CIRCUIT DIAGRAM:

TRUT TABLE:

Le$t S%+$tNo. o$ *"

&(")eSe'+a" +,&(t D+,

a'a""e" O(t&(t

!; !2 !1 !3

* * * * * *$ $ * * * $' $ * * $ $ * * $ $ *) $ $ $ * $ * $ * $ *. * * $ * *

( * $ * * *+ * * * * *

CA6E IN"TIT7TE O! TEC8NO9O:; 6age +


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R+%t S%+$t:

No. o$ *" Se'+a" +,&(t D+, a'a""e" O(t&(t



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&(")e !; !2 !1 !3

* * * * * *

$ $ $ * * *

' $ * $ * *

* $ * $ *

) $ $ $ * $

* * $ $ *

. * * * $ $

( * * * * $

+ * * * * *

ISO

CIRCUIT DIAGRAM:

ROCEDURE:$# :ive the co%%ectio%s as 1er the circuit

'# "et or Reset at the 1i% ' /hich it5s the "= of serial data#

# A11ly a si%gle cloc& "et or Reset seco%d digital i%1ut at 1i% '#

)# Re1eat ste1 ' u%til all )-bit data are ta&e% a/ay#


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$# >hat is registerB

'# >hat are the 3odes of shift registerB

# 8o/ ri%g cou%ter is i31le3e%ted usi%g shift registersB

)# Co31are 1arallel a%d serial sub registersB

# Defi%e se0ue%ce ge%eratorB

.# >hat are the ty1es of shift registerB

(# Defi%e shift registers#

RESULT:

Thus the "I"O, "I6O, 6I"O, 6I6O shift registers /ere desig%ed a%d i31le3e%ted#

4 1 MULTILE4ER

LOGIC SYMBOL:

CA6E IN"TIT7TE O! TEC8NO9O:; 6age .$


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TRUTH TABLE:

S".NoSELECTION INUT OUTUT

S1 S2 Y

$# * * I*

'# * $ I$

# $ * I'

)# $ $ I

PIN DIAGRAM OF IC 7411:

Ex. No.:8 MULTILE4ER DEMULTILE4ER

CA6E IN"TIT7TE O! TEC8NO9O:; 6age .'


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Date:

AIM:

To desig% a%d verify the truth table of a )X$ ulti1le


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DEMULTILE4ER

LOGIC SYMBOL:

CA6E IN"TIT7TE O! TEC8NO9O:; 6age .)


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TRUT TABLE:

S".NoINUT OUTUT

S1 S2 D+, Y3 Y1 Y2 Y;$# * * * * * * *'# * * $ $ * * *

# * $ * * * * *)# * $ $ * $ * *# $ * * * * * *.# $ * $ * * $ *(# $ $ * * * * *+# $ $ $ * * * $

CIRCUIT DIAGRAM:

CA6E IN"TIT7TE O! TEC8NO9O:; 6age ..


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ROCEDURE:

$# Co%%ectio%s are give% as 1er the circuit diagra3s#

'# !or all the ICs (th 1i% is grou%ded a%d $)th 1i% is give% @ su11ly#

# A11ly the i%1uts a%d verify the truth table for the 3ulti1le


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CIRCUIT DIAGRAM OF ASTABLE MULTI


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Ex. No.: ASTABLE MULTIVIBRATOR

Date:

AIM:

To study the a11licatio% of IC as a% astable 3ultivibrator#

AARATUS RE!UIRED:


$# !u%ctio% :e%erator 82 $'# CRO * 82 $# Dual R6" * H * $)# Ti3er IC IC $# =read =oard.# Resistors(# Ca1acitors+# Co%%ecti%g /ires As re0uired

TEORY:

A% astable 3ultivibrator, ofte% called a free-ru%%i%g 3ultivibrator, is a recta%gular-/ave

ge%erati%g circuit# This circuit do %ot re0uire a% ehe%ever the threshold voltage ehe% this 1i% is co%%ected to a% ehe% ? is lo/ the tra%sistor o1e%s a%d the ca1acitor charges# The co31le3e%tary sig%al out of

the fli1-flo1 goes to 1i% a%d out1ut# >he% e


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"i3ilarly the ti3e duri%g /hich the ca1acitor discharges fro3 'L cc to $L ccis e0ual to the

ti3e the out1ut is lo/ a%d is give% by,

t>0 3.= 6R27 C

Thus the total ti3e 1eriod of the out1ut /avefor3 is,

T 0 t* t> 0 3.= 6R1 2 R27 C

The ter3 duty cycle is ofte% used i% co%u%ctio% /ith the astable 3ultivibrator# The duty cycle

is the ratio of the ti3e tc duri%g /hich the out1ut is high to the total ti3e 1eriod T# It is

ge%erally e(t- *-*"e 0 6R1 R27 / 6R1 2 R27J x 133

ROCEDURE:

$# Co%%ectio%s are give% as 1er the circuit diagra3#

'# @ su11ly is give% to the @ cc ter3i%al of the ti3er IC#

# At 1i% the out1ut /avefor3 is observed /ith the hel1 of a CRO

)# At 1i% . the ca1acitor voltage is obtai%ed i% the CRO a%d the * a%d c voltage

/avefor3s are 1lotted i% a gra1h sheet#

CA6E IN"TIT7TE O! TEC8NO9O:; 6age ($


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MODEL GRA:


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$# >hat is 3ultivibratorB

'# >hat are the various 3odes of o1eratio% of 3ultivibratorB Ehat is o%e-shot 3ultivibratorB

# >hat is 0uasi stable stateB

.# :ive the a11licatio%s of -ti3er Astable 3ultivibrator#

(# >hat is the adva%tage of IC over o1 a31B

+# 9ist the a11licatio%s of 3o%ostable 3ode of ti3er#

# Defi%e Offset voltage#

$*# Defi%e duty cycle#

$$# e%tio% the a11licatio%s of IC#

$'# :ive the 3ethods for obtai%i%g sy33etrical s0uare /ave#$# >hat is the other %a3e for 3o%ostable 3ultivibratorB

$)# Ehy %egative 1ulse is used as triggerB

RESULT:

The desig% of the Astable 3ultivibrator circuit /as do%e a%d the out1ut voltage a%d ca1acitor

voltage /avefor3s /ere obtai%ed#

IN DIAGRAM:



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Date:

AIM:

To desig% the 3o%ostable 3ultivibrator usi%g the IC#

AARATUS RE!UIRED:


$# !u%ctio% :e%erator 82 $

'# CRO * 82 $

# Dual R6" * H * $

)# Ti3er IC IC $

# =read =oard $

.# Resistors

(# Ca1acitors

+# Co%%ecti%g /ires As re0uired

TEORY:

A 3o%ostable 3ultivibrator ofte% called a o%e-shot 3ultivibrator is a 1ulse ge%erati%g circuit i%/hich the duratio% of the 1ulse is deter3i%ed by the RC %et/or& co%%ected e


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S.No

A#&"+t(>e

6 No. o$ >+ x


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$# Co%%ectio%s are give% as 1er the circuit diagra3#

'# @ su11ly is give% to the @ cc ter3i%al of the ti3er IC#

# A %egative trigger 1ulse of , ' 82 is a11lied to 1i% ' of the IC

)# At 1i% the out1ut /avefor3 is observed /ith the hel1 of a CRO

# At 1i% . the ca1acitor voltage is obtai%ed i% the CRO a%d the * a%d c voltage

/avefor3s are 1lotted i% a gra1h sheet#


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CIRCUIT DIAGRAM:

To 3easure i%1ut offset voltage

To 3easure i%1ut bias curre%t

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Ex. No.:11 CARACTERISTICS OF OAM

Date:

AIM:

To 3easure the follo/i%g 1ara3eters of o1-a31

$# I%1ut bias curre%t

'# I%1ut offset curre%t

# I%1ut offset voltage

)# "le/ rate

AARATUS RE!UIRED:

S".No Na#e o$ t%e A&&a'at() S&e*+$+*at+o, !(a,t+t-$# !u%ctio% :e%erator 82 $'# CRO * 82 $# Dual R6" * H * $)# O6-A6 IC ()$ $# =read =oard $.# Resistors )#(, $**, $ $(# Ca1acitors *#*$P! $+# Co%%ecti%g /ires As re0uired

TEORY:

I,&(t +a) *(''e,t The i%verti%g a%d %o%i%verti%g ter3i%als of a% o1-a31 are actually t/o

base ter3i%als of tra%sistors of a differe%tial a31lifier# I% a% ideal o1-a31 it is su11orted that %o

curre%t flo/s through these ter3i%als# 8o/ever, 1ractically a s3all a3ou%t of curre%t flo/s

through these ter3i%als /hich is o% the order of %A ty1ical a%d 3a


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I%1ut offset voltage G $-3

"le/ rate G *# LSs

I,&(t o$$)et o"tae: Eve% if the i%1ut voltage is 2ero, out1ut voltage 3ay %ot be 2ero# This is

because of the circuit i3bala%ces i%side the o1-a31# I% order to co31e%sate this, a s3all voltage

should be a11lied bet/ee% the i%1ut ter3i%als# I%1ut offset voltage is defi%ed as the voltage that

3ust be a11lied bet/ee% the i%1ut ter3i%als of a% o1-a31 to %ullify the out1ut voltage# Ty1ical

a%d 3a7 S"e@ Rate

$# Co%%ect the circuit as sho/% i% !ig#$##'# :ive s0uare /ave i%1ut fro3 the sig%al ge%erator so that the out1ut is a s0uare /ave at

$&82#

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# I%crease the fre0ue%cy slo/ly u%til the out1ut is ust barely a tria%gular /ave#

)# Calculate sle/ rate as "R G L t#

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I%1ut offset curre%t G ######A

"le/ rate G ##LPs#

IN DIAGRAM:

IN


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Ex. No.:12 IN


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The i%1ut sig%al i is a11lied to the %o% - i%verti%g i%1ut ter3i%al of the o1-a31# This circuit

a31lifies the sig%al /ithout i%verti%g the i%1ut sig%al# It is also called %egative feedbac&

syste3 si%ce the out1ut is feedbac& to the i%verti%g i%1ut ter3i%als#

OBSER

6 No. o$ >+ x T+#e &e' >+ 7

I,&(t

O(t&(tTheoretical -

6ractical -

MODEL GRA:

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The differe%tial voltage dat the i%verti%g i%1ut ter3i%al of the o1-a31 is 2ero ideally a%d theout1ut voltage is give% as,

oG AC9 i

8ere the out1ut voltage is i% 1hase /ith the i%1ut sig%al#

RECAUTIONS:

$# Out1ut voltage /ill be saturated if it e


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NONIN

6 No. o$ >+ x T+#e &e' >+ 7

I,&(t

O(t&(t Theoretical -

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6ractical -

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MODEL GRA:

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Ex. No.:1; ALICATIONS OF OAM

Date:

AIM:

To de3o%strate the use of o1-a31 as

$ su33i%g a31lifier

' subtractor

2ero crossi%g detector a%d

) voltage co31arator#

AARATUS RE!UIRED:


$# !u%ctio% :e%erator 82 $'# CRO * 82 $# Dual R6" * H * $)# O6-A6 IC ()$ $# =read =oard $.# Resistors $, $* $

(# Co%%ecti%g /ires As re0uiredTEORY:

S(##+, A#&"+$+e': O1-a31 3ay be used to 1erfor3 su33i%g o1eratio% of several i%1ut

sig%als i% i%verti%g i% i%verti%g a%d %o%-i%verti%g 3ode# The i%1ut sig%als to be su33ed u1 are



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give% to i%verti%g ter3i%al or %o%-i%verti%g ter3i%al through the i%1ut resista%ce to 1erfor3

i%verti%g a%d %o%-i%verti%g su33i%g o1eratio%s res1ectively#

S(t'a*to': The basic differe%ce a31lifier ca% be used as a subtractor# The sig%als to be

subtracted are co%%ected to o11osite 1olarity i%1uts i#e# i% i%verti%g or %o%-i%verti%g ter3i%als

of the o1-a31#


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e'o C'o))+, Dete*to': Wero crossi%g co31arator WCD is a% a11licatio% of voltage

co31arator# It co%verts a%y ti3e varyi%g sig%al to s0uare of sa3e ti3e 1eriod /ith a31litude V

sat# The refere%ce voltage is set as 2ero volts# >he% the 1olarity of the i%1ut sig%al cha%ges,

out1ut s0uare /ave cha%ges 1olarity#

I,te'ato': I%tegrator is used to i%tegrate the iL1 /avefor3# i#e O G Yi% dt# 8ere i% the

i%verti%g a31lifier co%figuratio%, the feedbac& resistor Rf is re1laced by ca1acitor Cf#

I%tegrators are co33o%ly used i% /ave sha1i%g %L/s, sig%al ge%erators etc# !or 1ro1er /ave

i%tegratio%, T ZZ RC# :ai% a%d li%earity of the oL1 are t/o adva%tages of o1-a31 i%tegrators#9i%earity is due to li%ear chargi%g of ca1acitor# Its li3itatio% is for i%G* a%d for lo/

fre0ue%cies, XCf G[ or the ca1acitor Cf acts as a% o1e% circuit# Therefore the o1-a31 i%tegrator

/or&s as a% o1e% loo1 a31lifier a%d the gai% beco3es i%fi%ity or very high#

D+$$e'e,t+ato': 8ere the out1ut /avefor3 is the derivative of the iL1 /avefor3# I% a basic

i%verti%g a31lifier, if R$ is re1laced by C$, /e get the differe%tiator# =ut at high fre0ue%cies,

the gai% of the circuit RfLXC$ i%creases /ith i%crease i% fre0ue%cy at the rate of '*d=Ldecade#

This 3a&es the circuit u%stable# Also XC$ decreases /he% fre0ue%cy i%creases#

ROCEDURE:

a7 I,e't+, )(##+, a#&"+$+e':

$# Co%%ect the circuit as sho/% i% figure

'# Co%%ect batteries for voltage $, '#



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# easure a%d %ote the out1ut voltage a%d co31are it /ith theoretical value o G -Rf L Ri

$@'

7 S(t'a*to':

)# Co%%ect the circuit as sho/% i% figure

# easure a%d %ote the out1ut voltage a%d co31are it /ith theoretical value#

*7


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$$# Co%%ect the i%1ut to a sig%al ge%erator ge%erati%g a si% /ave /ith o%e volt 1ea& to 1ea& at

$&82#

$'# Co%%ect the i%1ut a%d out1ut to dual cha%%el CRO a%d co31are the i%1ut a%d out1ut#

$# 6lot the i%1ut a%d out1ut /avefor3 i% a gra1h#

e7 I,te'ato' D+$$e'e,t+ato':

$)# $# Co%%ectio%s are 3ade as 1er the diagra3#

$# '# A11ly a% iL1 voltage of $-'11 /ith $&82 fre0ue%cy a%d chec& the /avefor3 o% theCRO#

$.# # easure the value of O by varyi%g the fre0ue%cy of the iL1 sig%al#

$(# )# Calculate gai% usi%g the for3ulae '* log O LIN #



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I,te'ato':

TABULATION:

INUT OUTUT


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D+$$e'e,t+ato':

TABULATION:

IN67T O7T67TO9TA:E TIEON O9TA:E TIEO!!

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RESULT:

Thus, the use of o1-a31 as su33i%g a31lifier, subtractor, voltage co31arator, 2ero crossi%g

detector, i%tegrator, a%d differe%tiator /as studied#

BIT BINARY ADDER:

LOGIC DIAGRAM:

IN DIAGRAM OF IC 8;:

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#IC Trai%er &it - $

.#6atch cards - !e/

TEORY:

A bi%ary adder is a digital circuit that 1roduces the arithe3atic su3 of ' bi%ary %u3bers#It ca% be co%structed /ith full adders co%%ected i% cascade /ith the out1ut carry fro3 each fulladder co%%ected to the i%1ut carry of %e


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)-=IT =INAR; ADDERL "7=TRACTOR

The additio% a%d subtractio% o1eratio% ca% be co3bi%ed i%to o%e circuit /ith o%eco33o% bi%ary adder# The 3ode i%1ut 3 co%trols the o1eratio%# >he% 3G*, the circuit is addercircuit# >he% 3G$, it beco3es subtractor#

)-=IT =CD ADDER

Co%sider the arith3etic o1eratio% of t/o deci3al digits i% =CD, together /ith a% i%1ut carryfro3 a 1revious stage# "i%ce each i%1ut digit does %ot e


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$ $ * $ $ $ * $ $ * $ * $

$ $ $ * $ $ $ * $ $ * * $

$ $ $ $ $ $ $ $ $ $ $ * $

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TRUT TABLE BIT BINARY ADDER/SUBTRACTOR:

INUT DATA A INUT DATA B SUBTRACTION

A A; A2 A1 B B; B2 B1 B D D; D2 D1

$ * * * * * $ * $ * $ $ *

$ * * * $ * * * $ * * * *

* * $ * $ * * * * $ * $ *

* * * $ * $ $ $ * $ * $ *

$ * $ * $ * $ $ * $ $ $ $$ * $ * $ $ $ $ * $ $ $ $

$ * $ * $ $ * $ * $ $ * $



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TRUT TABLE FOR BCD ADDER:

BCD S(# Ca''-

S S; S2 S1 C

* * * * *

* * * $ ** * $ * *

* * $ $ *

* $ * * *

* $ * $ *

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RESULT:

Thus the )-=it adder a%d subtractor /ere desig%ed a%d i31le3e%ted usi%g IC ()+#

CIRCUIT SOING ALICATION OF A/D AND D/A CON


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FUNCTIONAL DIAGRAM OF ADC

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Ex. No.:15 STUDY OF ANALOG TO DIGITAL CON


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I%tegrati%g ty1e ADC" 1erfor3 co%versio% i% a% i%direct 3a%%er by first cha%gi%g the a%alogi%1ut sig%al to a li%ear fu%ctio% of ti3e or fre0ue%cy a%d the% to a digital code# The t/o 3ost/idly used i%tegrati%g ty1e co%vertors are

$# Chargi%g bala%ci%g ADC

'# Dual slo1e ADC

The 3ost co33o%ly used ADC" are successive a11ro


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Thus the reali2atio% of circuit for co%versio% /as studied#

BLOC DIAGRAM OF LL:

IN DIAGRAM:

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out1ut# The high fre0ue%cy co31o%e%ts !s@!oQ is re3oved by the lo/ 1ass filter a%ddiffere%ce fre0ue%cy co31o%e%t is a31lified a%d the a11lied as co%trol voltage cto co# Thesig%al c shifts the co fre0ue%cy i% a directio% to reduce the fre0ue%cy differe%ce bet/ee% !a%d fo# O%ce this actio% starts /e say that the sig%al is the ca1ture ra%ge# The circuit is said tobe loc&ed# O%ce the loc&ed, the OL6 fre0ue%cy to of co is ide%tical to ! i%s1ect for a fi%ite1hase differe%ce !#

!ree Ru%%i%g

$# Ca1ture

'# 9oc&ed or trac&i%g

The gra1h sho/s the ca1ture tra%sie%t as ca1ture starts s3all si%e /ave a11ears# This is due tothe differe%ce fre0ue%cy bet/ee% the co a%d the IL6 sig%al# Each successive cycle causes theco fre0ue%cy beco3es s3aller a%d a large dc co31o%e%t is 1assed by the filter shifti%g the

co loc&s o% to the sig%al a%d differe%ce fre0ue%cy is dc# The lo/ 1ass fiter co%trols thediffere%ce ra%ge# If co fre0ue%cy is far a/ay the beat fre0ue%cy /ill be high to 1ass throughthe filter a%d the 699 /ill %ot res1o%d /e say thet the sig%al is %ot of the ca1ture ba%d# Theco ca% tra%s, thus trac&i%g ra%ge#

NE/SE 5=5 BLOC DIAGRAM:

FRE!UENCY MULTILIER USING IC LL:

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The total ti3e ta&e% by the 699 to establish the loc& is called 1ull i% ti3e# This de1e%dso% the i%itial 1hase a%d fre0ue%cy differe%ce bet/ee% the t/o sig%als as /ell as o% the over allloo1 gai% loo1 filter characteristics#

IC LL 5=5:

. is available as a $)-1i% di1 1ac&age as $*-1i% 3etal ca% 1ac&age# The 1i%co%figuratio% a%d the bloc& diagra3 are sho/% i% figure# The out1ut fre0ue%cy of the co isgive% gy the e0uatio% !oG*#'LRtCt 82, /here Rt a%d Ct are the e


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ROCEDURE:

$# a&e the co%%ectio%s as 1er the circuit diagra3#

'# "et the i%1ut sig%al at 11 s0uare /ave at **82#

# ary the co fre0ue%cy by adusti%g the '* oh3s 1ote%tio3eter till the the 699 is

loc&ed# easure the out1ut fre0ue%cy# It should be five ti3es the i%1ut fre0ue%cy#

)# Re1eat ste1 ', for i%1ut fre0ue%cy of $8W a%d $#8W#

CA6E IN"TIT7TE O! TEC8NO9O:; 6age $'.


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RESULT:

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Thus the 699 IC a%d fre0ue%cy 3ulti1licatio% usi%g NEL"E . 699 IC /ere studied#


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Ex. No.:1 STUDY OF


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curre%t Ca11lied at the 3odulati%g i%1ut or by cha%gi%g the ti3i%g resistor Ri, e


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TYICAL CONNECTION DIAGRAM:

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