ee201 midterm Sp2013 · 2013. 11. 7. · Title: ee201_midterm_Sp2013.fm Author: Gpadmin Created...

ee201_midterm_Sp2013.fm

3/29/13 EE201L Midterm - Spring 2013 1 / 8C Copyright 2013 Gandhi Puvvada

Spring 2013 EE201L Instructor: Gandhi Puvvada Midterm Exam (20%) Date: March 29, 2013 Friday in SAL101 Open-Book Open-Notes Exam Time: 4-6:30PM Name: Total points:

Perfect score:

1 ( 32 points) 30 min.

1.1 A state machine has 13 states and there were 13 Flip-flops in an one-hot implementation of it. At the 13 D-inputs of these 13 flip-flops, _________________________ (towards the end of / towards the beginning of / through out) the clock cycle, we expect to see one and only one D-input to have a "1" standing in front of it while the remaining 12 D-inputs to have "0"s standing in front of them.

If we change the above sentence by replacing "D-inputs" to "Q-outputs" and "standing in front of" to "standing on", will there be any change in your answer? ________ Yes / No. Explain briefly: ________________________________________________________________________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________

1.2 In the OFL (Output Function Logic) of a state machine implementation using one-hot method, if it is a MOORE machine, we expect to see (circle all applicable):(a) OR gates (b) NOR gates (c) straight wires or dummy buffers (d) inverters (e) SOP/POS (i.e. AND-OR, OR-AND, or any of the 6 non-degenerative forms of 2-level logic or their derivatives)

If we changed the above sentence replacing the "MOORE" with "MEALY", will there be any change in your answer? ________ Yes / No. Explain briefly: ________________________________________________________________________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________

1.3 ___________ (Since / While) a flip-flop output does not produce glitches, an OFL such as an OR gate

(example ) or a NOR gate (example ) ______________

(will not / can still) produce glitches. Explain briefly: _______________________________________________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________

1.4 Many combinational logics ________ (do / do not) produce glitches. If the glitches die down by the __________________ (beginning of / end of / middle of) the clock when the output produced by the combinational logic needs to be registered, the glitches are harmless!

5pts

5pts

Q1Q2Q3

X_Load Q4Q5Q6

Y_Load

5pts

4pts



1.5 The state diagram on the side has 3 states on the left and 3 states on the right. You see only state transition arrows from the left to right but not the other way around.

Now further consider the two possibilities of having the K.D.I.S (known desired initial state) on RESET as shown below:

Circle one of the choices below and explain.(a) both are possible cases(b) #1 is possible but not #2(c) #2 is possible but not #1(d) both do not make sense (and hence not possible) because of the state transition arrows between the left three states and right three states are all going from left to right.Explain briefly: ________________________________________________________________________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________

1.6 Output coded state assignment and additional tie-breaker (buried) flip-flops to break aliases:An 8-state state machine was initially implemented using encoded state assignment. It produced glitches at the output of its OFL. Mr. Trojan was called in to re-implement the state machine using output coding so as to avoid OFL altogether and thereby solving the glitches problem. Use one or two tie-breaker flip-flops (TB1 and TB2) as needed and complete the output state coding. Notice that the three columns QOP2, QOP1, QOP0 are identical to the three columns OP2, OP1, OP0.


Basic design of state diagrams:

Problem to be solved: Given an 8-bit number A, inspect its bits serially and determine if it is GOOD (meaning, it has at least one 1 and at least one 0) or BA0 (Bad All Zeros) or BA1 (Bad All Ones).

S1

S2 S3

S4

S5 S6

S1

S2 S3

S4

S5 S6

S1

S2 S3

S4

S5 S6

RESET RESET1 2

5pts

8pts

Q2 Q1 Q0 OP2 OP1 OP0 QOP2 QOP1 QOP0 TB1 TB2S0 0 0 0 0 0 0 0 0 0S1 0 0 1 0 1 0 0 1 0S2 0 1 0 0 1 0 0 1 0S3 0 1 1 0 1 0 0 1 0S4 1 0 0 1 0 0 1 0 0S5 1 0 1 1 0 0 1 0 0S6 1 1 0 1 1 0 1 1 0S7 1 1 1 1 0 1 1 0 1

Output neededEncoded State Assignment Output-coded state assignmentState



2.1 Complete the following design which uses a right-shift register (A




Given on the side is the original GCD state diagram.

3.1 Miss Trojan said that the first doubling (if needed) could be done by doing d



4 ( points) min. We have to code a 4-bit up counter with the usual clear, load, and enable controls and additionally with a special behavior as follows. It increments most of the time by 1, but if the incremented next value (I+1) is equal to the lucky number (an external input which can change on any clock) then it increments by 2 (instead of by 1). The behavior is shown in the following two diagrams. Both are good designs. The second design may have slight timing advantage as usually an equality checker is faster than an incrementer but optimization is the tool’s responsibility.

Given below is the common code provided by the TA to four students and the four students’ individual codes. #1 and #2 students used I_nxt but differed in blocking and non-blocking.

II + 1I i0i1 ys

clr

0000i0i1 ys

loadLoad

Value

i0i1 ys

en1

I + 21

EQlucky

i0i1 ys

I

I + 1I

i0i1 ys

clr

0000i0i1 ys

loadLoad

Value

i0i1 ys

en1

I + 22

EQlucky

i0i1 ys

I

clk

clk

12pts

`timescale 1 ns / 100 psmodule up_counter_special (clk, en, load, clr, loadvalue, lucky, I);

input clk, clr, load, en;input [3:0] loadvalue, lucky;output [3:0] I;reg [3:0] I;

always @(posedge clk)begin : local_blockreg [3:0] I_nxt;if (clr)I



5 ( 8 + 14 = 22 points) 15 min.

Counter analysis:

5.1 Arrive at the count sequence of the following special down counter. Explain briefly.

5.2 Given below is a mix of new and old. The top counter is based on the above down counter, The bottom counter is the same as the bottom up counter from Spring 2012 midterm discussed in class.Write down the repetitive pattern of the top down counter starting from reset. Modify or continue the partial sequence as needed to arrive at the total sequence. Top counter: 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Bottom counter: 0 0

Top counter: 7 6 Bottom counter:

8pts A0A1A2

B0B1B2

S0S1S2

Subtractor

I00I01I02

I10I11I12

Y0Y1Y2

S

Mux

100 1

11

Q0

Q1

Q2D Q

CLK

LSB

MSB

RESET

71

00 SET

On RESET, it

D QSET

D QSET

4

14pts

A0A1A2

B0B1B2

S0S1S2

Adder

I00I01I02

I10I11I12

Y0Y1Y2

S

Mux

100 1

11

D Q

QB0

QB1

QB2

D Q

D Q

CLK

CLR

LSB

MSB

RESET

7

I00I01I02

I10I11I12

Y0Y1Y2

S

Mux

1

0

0

2

QB[2:0] (B = Bottom counter)Register

A0A1A2

B0B1B2

S0S1S2

Subtractor

I00I01I02

I10I11I12

Y0Y1Y2

S

Mux

100 1

11

Q0

Q1

Q2D Q

CLK

LSB RESET

7 SETD Q

SET

D QSET

MSB

1

00

4




6.1 Glitches in control signals such as X_load controlling the updating of a data register X ________(are / aren’t) harmful because _____________________________________________________________________________________________________________________________________________________________________________________________________________________We also note that glitches at the output of a TV remote control are __________________ (similarly / however) ________________(harmful / not harmful).

6.2 A verilog "for loop" construct ____ (is / isn’t) unrolled by the synthesis tool. It is used for coding (circle the right choice (s))(a) combinational logic where some portions of logic structured are repeated n times in cascading(b) to perform hardware iteration under state machine control such as voting machine serially inspecting 8 votes.

6.3 ________________________________ (An input, but not an output, / An output, but not an input, / Either an input or an output / Neither an input nor an output) may be left open (unconnected). Explain: ______________________________________________________________________________________________________________________________________________________________________________________________________________________________________

6.4 Full (4-way) hand-shake (take it, got it, I see that you got it, I see that you saw that I got it):There are two pairs, P1 and C1 are producer-consumer pair #1 and P2 and C2 are producer-consumer pair #2. Pair #1 use active high signals and pair #2 use active low signals. Based on the pair #1 waveform determine if the consumer is slower or faster than the producer. Then draw the C2_Got waveform, making C2 different from C1 in speed. If C1 is slower than P1, C2 must be faster than P2.Also show Cause and Effect arrows for the pair #2.

6.5 Set-up time of a flip-flop has ______ (a / b / c) below.(a) only one value and it is always the minimum value(b) only one value and it is always the maximum value(c) has three values like combinational delays: minimum, typical, maximum.

6.6 An inverter has two propagation delays: tpHL and tpLH where the HL and LH refer to the transitions at the __________________ (input / output) of the inverter. Brute force delay addition by adding two or four inverters is the simple way to fix ___________________ (setup / hold) time violations.

6.7 The ______________________ (longest / shortest) path between the source register and the destination register is considered for setup time verification.

5pts

3pts

5pts

10pts

P1_Take

C1_Got

P2_Take

C2_Got

You determined thatC1 is _____________(slower / faster) thanP1 because ___________________________________________________________________________________________________

3pts

4pts

2pts




Microprogrammed control unit and datapath:

Given X, Y, Z, we need to find the smallest of the three and load it into the S (for Small) register. There is only one bus, so one of the two items to be compared shall be brought and left in the T (Temp) register tied to the comparison unit first. The output of the comp. unit is called BLT to stand for "Bus is Less than Temp". There are altogether 5 registers with 5 Update controls and three tristate buffers with three enable controls. 1. Complete the state transitions conditions in terms of BLT and number the states for uPCU.2. Specify bare minimum values for the components of uPCU (microprogram control unit).

Number of locations in the UPROM: _________ Size of the uPC: _____________ Size of the Branch Address field: _________ Number of control signals going to the DPU___

Size of the Control Signal field: ________ Number of distinct conditions governing branches: _____ Size of the Condition Select Mux: _________________ Size of the Condition Select field: ______Size of the microprogram memory: _________________________________________________.

14pts

14pts

i0i1 ys DQ

CK

C

i0i1 ys DQ

CLK C

i0i1 ys DQ

CLK C

i0i1 ys DQ

CLK C

Update_SENX

ENY

ENZ

Update_X

Update_Y

Update_Z

X

Y

Z

S

Bus

i0i1 ys DQ

CLK C

Update_T

T

ABB

ee201 midterm Sp2013 · 2013. 11. 7. · Title: ee201_midterm_Sp2013.fm Author: Gpadmin Created...

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Transcript of ee201 midterm Sp2013 · 2013. 11. 7. · Title: ee201_midterm_Sp2013.fm Author: Gpadmin Created...