_EE 425_Exp_8.pdf

download _EE 425_Exp_8.pdf

of 5

Transcript of _EE 425_Exp_8.pdf

  • 8/14/2019 _EE 425_Exp_8.pdf

    1/5

    Electronic Circuits I Laboratory

    68

    8 JFET Ampl ifying Circuits

    8.1 Objectives Understand the principles of JFET amplifier circuits.

    8.2 Basic Description

    8.2.a Terminology

    The three most important parameters of JFETs are described as follows:

    1) gm(trans conductance)fixedVds

    Vgs

    id

    =

    =

    2) rd(drain resistance)

    fixedVgsid

    Vds

    =

    =

    3) (amplification factor)

    fixedidVgs

    Vds

    =

    =

    8.2.b Basic Principle

    8.2.b.1 Bias Arrangement

    Self b ias arrangement

    Source self-bias arrangement for JFET is shown in Fig 8.1 (a). When the single

    power supply Vdd is applied to drain, the self-bias can be established at gate and

    souce so as to result in adequate operating point. There is no need for a second

    power supply in order to have a negative VGSvoltage value

  • 8/14/2019 _EE 425_Exp_8.pdf

    2/5

    Electronic Circuits I Laboratory

    69

    Since RGis very large,

    0, 0.G R GG

    I V V = =

    We can also write:

    0.G GS RS GS D

    V V V V I Rs= + = + =i

    This equation yields:

    .GS D

    V I Rs= i

    Fig. 8.1 JFET Self biasing

    Plotting the load line:

    a.From the KVL of output circuit:

    dd D D DS D S V I R V I R= + +

    b.When Id = 0, VDS= Vdd = 12V (point A)

    c.When VDS= 0,

    124

    3D

    D S

    Vdd V I mA

    R R K= = =

    + (point B)

    d.The straight line connected between point A and B is the DC load line. The

    operating point lies in the intersection of this load line and the curve for VGS.

  • 8/14/2019 _EE 425_Exp_8.pdf

    3/5

    Electronic Circuits I Laboratory

    70

    Voltage dividing bias arrangement

    Fig 8.3 shows a voltage-dividing circuit for JFET, wherein except no longer

    setting Vg as zero, the solutions to Vsg and Id are same as those of self-bias.

    21 2

    G

    RV Vdd R R

    =

    + ,

    GS G D S V V I R= and

    2(1 )GS Q

    DQ DSS

    VI I

    Vp=

    .

    Fig. 8.2 Voltage dividing bias arrangement

    8.3 Experiment Equipments

    1. KL- 200 Linear Circuit Lab. Device

    2. Experiment Module: KL-23004

    3. Experiment Instruments: Oscilloscope, Multimeter, Function Generator

    4. Connection cables and short-circuit clips

  • 8/14/2019 _EE 425_Exp_8.pdf

    4/5

    Electronic Circuits I Laboratory

    71

    8.4 Procedures

    Procedure : Common Source Amplifier Self Biasing

    1 )Locate the block marked 23004-block c.2 )Insert the short-circuit clips by referring to Fig 8.4.

    Fig. 8.4

    3 )Use voltmeter (DCV) to measure VGSand VD, then make records.4 )Connect signal generator in the input terminal (IN) and connect

    oscilloscope to the output terminal (OUT).

    5 )Adjust the output of signal generator to 1 kHz sine wave and graduallyincrease the amplitude so that the oscilloscope can display maximum non-distorted output waveform, and make records. At the same time use theoscilloscope to measure the waveform in the input terminal (IN), and makerecords on Table 8.1.

    6 )Change R12 to R16 (6.8K), then repeat Step (3), (4) and (5).7 )Resume R12 to 3.3K and disconnect C3, then repeat Step (5).

  • 8/14/2019 _EE 425_Exp_8.pdf

    5/5

    Electronic Circuits I Laboratory

    72

    Table 8.1 CS Self Biasing

    VDS

    VGSVD

    AV

    R12

    Vinmax

    VDS

    VGS

    VD

    AV

    R16

    Vinmax

    VDS

    VGS

    VD

    AV

    C3

    Disc.

    Vinmax