EE 332 Lab 3

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Experiment-3

R. B. Darling/R. Yotter/T. Chen EE-332 Laboratory Handbook Page E3.1

Experiment-3

Multi-Stage Amplifiers

Introduction The objectives of this experiment are to examine the characteristicsof several multi-stage amplifier configurations. Several of these will

be breadboarded and measured for voltage gain, frequency response

and signal swing.

In addition to the performance measurements, you should also pay

attention to how the biasing of each amplifier stage is achieved, how

the signal is coupled from stage to stage, and what design strategy

has been adopted to desensitize the amplifier performance to

variations in the transistor parameters. For each amplifier in this

experiment, try to answer the question: What has been achieved by

connecting the transistors in this configuration? To begin to answer

this question, first identify whether a particular transistor is providing

bias stabilization for other transistors, or is a gain stage in the signal

path. Some transistors may simultaneously function in both roles.

Then try to determine what components set the voltage gain of the

amplifier. Track the path of the signal through the different stages of

the amplifier and try to understand how much voltage gain is

produced across each stage, how big the signal is at each node along

the path, and what limits the signal swing at each node. Draw a

schematic of the amplifier in your lab notebook and mark it up

extensively to show the DC bias voltage at each node, the path thatthe signal takes from input to output, and any thing else that is of

interest to you.

The amplifier circuits described in this experiment are not as simple

as those previously used in this lab. While all of the component

values are fairly close to the values needed to make the circuits work,

normal variations in transistor parameters will require that each

amplifier circuit be tuned-up slightly to center the signal swings or

trim out the gain. This is left for you to do without any explicit

instructions and is intended to force you to understand how the

circuits work and to gain skill in electronic troubleshooting. Similarly,

the procedures will only ask you to measure certain performance

parameters without giving explicit instructions. At this point, you

should be comfortable making all of these measurements. Refer back

to experiments 2 and 3 if you need to refresh your memory on

making gain and frequency response measurements.

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Comment Some of the procedures in this experiment will utilize the CA3046 npn

BJT array. The CA3046 is an RCA part number, and it is the same as

the National Semiconductor part number LM3046. This integrated

circuit comprises five npn BJTs which are fabricated on the same

piece of silicon, and is a first approximation to the behavior of BJTs

that one would find in a bipolar integrated circuit. The first two BJTsare tied together with a common emitter (pin 3), and the last BJT has

its emitter tied to the substrate (pin 13), as shown in Fig. E5.0 below.

All five npn BJTs have their collectors embedded into a common p-

type substrate, which is connected to pin 13. In order to keep the

collector-substrate pn-junctions reverse biased so that the BJTs will

remain electrically isolated, the substrate on pin 13 MUST be tied to

the lowest potential in the circuit, even if the fifth transistor is not

being used. Any circuits using the fifth BJT of the CA3046 array MUST

tie the emitter of this transistor to the lowest potential power supply

rail. Failure to tie pin 13 to the lowest circuit potential will result in

very unpredictable behavior for the circuit. Be warned!!

Figure E3.0

12

7

1

Q1 Q2

Q5

5

SUBSTRATE

9

11

14

3

13

8

Q4

4

6

10

2

Q3

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Procedure 1 Differential amplifier

Comment A differential amplifier is designed to amplify the difference between

two input voltages. It is also designed to reject the average between

the two input voltages. The difference between two signals is termed

the differential-mode signal, while the arithmetic average of two

signals is termed the common-mode signal. When only one signal is

applied to, or taken from, a differential input or output, it is termed

an unbalanced, single-ended or unipolar input or output. A balanced

signal is a pair of signals whose magnitudes are the same but whose

polarities are opposite. When a balanced signal is applied to, or taken

from, a differential input or output, it is termed a balanced, double-

ended, or bipolar input or output. The common-mode rejection ratio

(CMRR) is the differential-mode gain divided by the common-mode

gain.

Set-Up Produce the circuit of Fig. E4.1 using the following components:

RC1, RC2, RE = 5.1 k5% 1/4 W

Q1, Q2 = CA3046 npn BJT array

Figure E4.1

Ground the bases of both Q1 and Q2 by connecting them both to thesystem ground. Set PPS1 to +6.0 V and PPS2 to -6.0 V. Verify that the

two power rails are at 6.0 V. Verify that both Q1 and Q2 are in the

forward active region of operation by measuring the DC voltage on

the emitter, base, and collector terminals of each. Voltages on the

collectors of both Q1 and Q2 should be around +3 V. If this is not the

case, identify and fix the problem before proceding further.

RC25.1k

5

+6V

RE5.1k

PPS1VCC

-6V

4VB13

RC15.1k

1-6V

VC1

PPS2VEE

2 Q1CA304

VC2

+6V

GND 1 Q2CA304

VB23

SUBSTRATE

GND

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Turn the two DC power supplies OFF by setting them to +0.0 V.

Configure the signal generator to produce a 100 mVpp (peak-to-peak)

sinewave at 1.0 kHz. Make sure that any DC offset on the signal

generator is turned off. Connect the ground of the signal generator

to the system ground of the circuit. Disconnect the wire shorting the

base of Q1 to ground. Connect the output of the signal generator tothe base of Q1, node B1. The base of Q2 (node B2) remains

grounded.

Connect a 10probe to the Ch-1 and Ch-2 inputs of the oscilloscope.

Configure the oscilloscope to display both channels versus time with a

1 ms/div sweep rate. Configure Ch-1 for 50 mV/div and DC coupling,

and Ch-2 for 2 V/div with DC coupling. Trigger the oscilloscope off of

the Ch-1 input. Connect both probe ground leads to the system

ground, connect the Ch-1 probe to the input of the signal generator

(node B1 in Fig. E4.1), and connect the Ch-2 probe to the collector ofQ1 (node C1 in Fig. E4.1).

Measurement-1 Energize the circuit by setting PPS1 to +6.0 V and PPS2 to -6.0 V. You

should observe about 10 cycles of the input and output sinewaves.

The output sinewave, taken from the collector of Q1 should be

centered about a DC level of about 3 V, and it should have an

amplitude that is significantly larger than the amplitude of the input

sinewave on Ch-1. Note the polarity of the output sinewave relative

to the signal generator input. Move the Ch-2 probe to the collector of

Q2 (node C2 in Fig. E4.1) and again note the polarity of the output

sinewave relative to the signal generator input. You should observethat the amplitudes of the two signals on C1 and C2 are the same.

Adjust the amplitude of the signal generator so that the output

sinewave is as large as possible, but not yet clipping on either polarity

peak. Calculate the voltage gain of the amplifier by dividing the

amplitude of the output sinewave by the amplitude of the input

sinewave and record the result in your lab notebook. Note that this

voltage gain represents that from a double-ended input to a single-

ended output. This is because the input signal is applied between the

bases of the two transistors, but the output is taken from only one ofthe collectors. (A double-ended output would have been taken from

between the two collectors.) This voltage gain is the differential

voltage gain of the amplifier.

Adjust the amplitude of the signal generator until the output

sinewave is not clipped. Increase the frequency of the signal

generator until the amplitude of the output sinewave has fallen to

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about 70 percent of its initial value at 1 kHz. This will probably occur

around 1 MHz, so the oscilloscope and the input signal will need to

have their time bases adjusted together to retain 5-20 complete

cycles on the oscilloscope display. Record in your lab notebook the

frequency at which the ratio of the output to input amplitude has

fallen to the 70 percent point. This is the3 dB bandwidth for thedifferential gain of this amplifier.

Next, turn off the PPS power supplies. Disconnect the wire shorting

the base of Q2 to ground and connect the bases of Q1 and Q2

together and to the signal generator. This will apply a common-mode

input signal to the differential amplifier from which the common-

mode gain can be determined. Turn on the PPS power supplies.

Configure the signal generator to produce a 1.0 kHz sinewave with a

peak-to-peak amplitude of 3 Vpp. Adjust both Ch-1 and Ch-2 gains on

the oscilloscope to 2 V/div. Move the Ch-2 probe to and from C1 and

C2, noting the polarity of the output waveforms relative to the signal

generator input. Measure the common-mode gain of the differential

amplifier by taking the ratio of the output amplitude at either C1 or

C2 to the input amplitude at either B1 or B2 and record this in your

lab notebook.

Using the procedures described previously, measure the3 dB

bandwidth of the common-mode gain and record this in your lab

notebook.

Question-1 (a) Calculate the common-mode rejection ratio (CMRR), expressing itin both as a pure ratio and in decibells (dB).

(b) Explain why the common-mode gain is approximately 0.5 and

inverting when no DC offset is applied from the signal generator.

(c) Suggest a way to increase the CMRR of this differential amplifier.

Hint: think about how ideal the current source RE is and how it might

be improved.

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Procedure 2 Active loads---a simple opamp

Comment An active load usually refers to the use of a transistors output

characteristics (ICversus VCE) to provide a high output resistance but

at a much larger level of DC current than what a passive resistor alone

could provide. Using an active load for a common-emitter stage

greatly increases the voltage gain since the collector resistance for

the CE amplifier stage is now the output resistance of the active load

transistor. In the circuit of Fig. E3.2, an active load is used on both

collector legs of an npn differential pair. When connected like a

current mirror as shown, the pair of active loads also has the benefit

of routing both sides of the differential signal into the next stage, the

base of Q6. The active loads in this case form a differential to single-

ended converter.

Transistor Q3 provides an improved current source for the differentialpair which greatly increases the common-mode rejection ratio.

Transistor Q6 implements a simple common-emitter stage with a load

resistor of R8. This adds some final gain and current drive to the

output pin. Resistors R5-R6-R7 provide bias stabilization for this

output stage.

R4 is an optional trimpot between the emitters of Q1 and Q2. This

will lower the voltage gain of this stage slightly, but it will allow the

input differential amplifier to be balanced to help bias the circuit so

that the output voltage will be about zero when the differential input

voltage is also zero. This may or may not be necessary. If R4 is used,

its value should not be more than 1.0 k, or the gain of the

differential amplifier will be lowered too much.

Set-Up Construct the circuit shown in Fig. E3.2 on your solderless breadboard

using the following components:

R1 = 10 k5% 1/4 W

R2 = 100 k5% 1/4 W

R3 = 1.0 k5% 1/4 W

R4 = 1.0 k trimpot (if needed to balance the amplifier)R5 = 15 k 5% 1/4 W

R6 = 43 k 5% 1/4 W

R7 = 620 5% 1/4 W

R8 = 3.3 k5% 1/4 W

Q1, Q2, Q3 = 2N3904 npn BJT

Q4, Q5, Q6 = 2N3906 pnp BJT

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Figure E3.2

Configure the PPS1 DC power supply to +10.0 V DC and the PPS2 DC

power supply to -10.0 V DC. This is to implement the VCC = +10.0 V

and VEE = 10.0 V DC power supply rails, as shown in Fig. E4.2.

Connect the PPS1 and PPS2 outputs to the breadboard. The GND

terminals on PPS1/PPS2 are the system ground.

Because of the high gain of this circuit, you may need to adjust the DC

balance of the input differential amplifier. First check the balance by

grounding both inputs to the bases of Q1 and Q2. Make certain that

these grounds go to the system ground labeled GND in Fig. E3.2.

With both inputs grounded, measure the voltage on the output pin,connected to the collector of Q6. This should be within a volt or so of

ground, also. If it is not, then you may need to add in the optional

trimpot R4 between the emitters of Q1 and Q2. Power down the

circuit, install R4, and then fire it back up to re-measure the DC

output voltage. If the output voltage is still not sufficiently close to

zero, adjust the trimpot to center the output voltage to zero. You

may need to readjust this balance as you go through the rest of this

procedure.

Measurement-2 Ground the () input of the amplifier and apply a sinewave to the (+)input, relative to the system ground. Adjust the amplitude of the

input to produce a non-distorted sinewave at the output. Adjust the

frequency so that the maximum voltage gain is obtained. You will

have to use a very small amplitude sinewave on the input, since the

voltage gain of this circuit is rather high, and the frequency that you

use may need to be fairly low to obtain the maximum voltage gain.

Measure and record the amplitude of the input and output

R

100k

Q62N3906

R

3.3k

GNDQ32N3904

PPS1VC

R

620+10V

-10V

R 1k POTVIN-

PPS2VEE

Q22N3904

Q42N3906

GND

R515k

-10

+10V

Q12N3904

R

1.0kR10k

R643kVIN+

VOUT

Q52N3906

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sinewaves, and take their ratio to determine the differential-mode

voltage gain.

Increase the amplitude of the function generator to where the output

waveform is clipped at both the positive and negative peaks.

Measure and record the output voltage levels at which the clippingoccurs.

Decrease the amplitude of the function generator to again produce

an undistorted sinewave at the output and then increase the

frequency to where the voltage gain drops to 70 percent of its

maximum value. Measure and record this frequency as the -3 dB

differential-mode bandwidth.

Release the () input from ground and apply the function generator

output to both the (+) and () inputs simultaneously, adjusting theamplitude to produce an undistorted sinewave at the output.

Measure and record the amplitude of the input and output sinewaves

and take their ratio to determine the common-mode voltage gain.

Question-2 (a) From your measured data, calculate the differential-mode voltage

gain of the amplifier in decibells (dB).

(b) From your measured data, calculate the common-mode voltage

gain of the amplifier in decibells (dB).

(c) Calculate the common-mode rejection ratio (CMRR) for this

amplifier, expressing the result in decibells (dB).

(d) Explain what determines the clipping voltage levels.

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Procedure 3 Complementary class-AB output stage

Comment Emitter followers (or common-collector) stages were shown to be a

nice means for increasing the output current level of an amplifier and

buffering voltage gain stages. However, when a large bias current

runs continuously through such a stage, it dissipates far more power

than it delivers to the load, resulting in poor power efficiency. One

way to correct this is to only operate the transistor when it is

delivering current to the load, termed class-AB operation. Using two

transistors of opposite sex but driven by the same input signal is

termed a complementary output stage and provides a power efficient

configuration for output buffering or current boosting. This circuit

can be used to boost the output current of an opamp. Putting the

output stage inside the feedback loop causes the gain of the opamp

to linearize the characteristics of the output stage.

Set-Up Construct the circuit shown in Fig. E3.3 on a solderless breadboard

using the following components:

R1, R2 = 4.7 k5% 1/4 W

R3, R4 = 5.0 5% 1/4 W

R5 = 100 k5% 1/4 W

RL = 100 5% 1/4 W

C1, C2 = 10 F electrolytic

D1, D2 = 1N914 or 1N4148

Q1 = TIP-29 npn power BJT

Q2 = TIP-30 pnp power BJTQ3 = 2N3904 npn BJT

Q4 = 2N3906 pnp BJT

-

+ C10uF

R

4.7k

R

5.0

QTIP29

D1N4148

Q2N3904

Q2N3906

+10V +10V

+ C10uF

-

PPS2VEE

GND VOUT

QTIP30

R

4.7k

R

100kVI

R

100

R

5.0GND

PPS1VC

D

1N4148

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Figure E3.3

Configure PPS1 and PPS2 to implement the VCC = +10.0 V and VEE =

10.0 V DC power supply rails, as shown in Fig. E3.3. Turn the PPS

power supplies ON. The center ground terminal is the system ground.

Configure the functional generator to produce a 1.0 kHz 5.0 Vpp

amplitude sinewave and apply this sinewave across the input resistor

R5.

Measurement-3 Use an oscilloscope to monitor the input and output voltage

waveforms. Record sketches of the input and output waveforms in

your lab notebook.

Increase the amplitude of the input signal until the output voltage

waveform is clipped on both the positive and negative peaks.Measure and record the output voltage clipping levels.

Restore the input signal to a 1.0 kHz 5.0 Vpp amplitude sinewave and

increase the frequency until the output voltage waveform falls to 70

percent of its previous amplitude. This is the -3 dB bandwidth of the

output stage.

Question-3 (a) Calculate the voltage gain for this output stage.

(b) Comment on any distortion that is seen in the output voltage

waveform.

(c) Calculate the limited value of output current when the short-circuit protection becomes active.

EE 332 Lab 3

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