File: EE201L_syllabus_Spring2014.docx Date of revision: 1/13/2014 Spring 2014 EE 201L Instructor: Gandhi Puvvada Introduction to Digital Circuits Syllabus 1. Abstract: This course covers a substantial (yet simple) digital “system” design

comprising of a datapath and a control unit. Synchronous digital design principles are taught in lecture and industrial-grade tools (Xilinx ISE, and ModelSim) for design entry, simulation, and implementation are used in lab. RTL design is taught using Verilog HDL. Microprogramming concepts and timing analysis are also covered. Memory components (SRAM, FIFO) are also covered. While most designs are implemented in FPGAs, a couple of simple designs are put on breadboards using discrete ICs. In the last three weeks of the course, the students, propose, specify, design, and implement a fairly big project.

This is a very practical and fundamental course covering substantial skills in digital design, implementation, and testing expected out of any electrical engineering or computer engineering student.

Computer Science students need this course to be able to deal with the computer organization topics covered in EE357 (and EE457 elective).

2. Course administration: a) Course prerequisites: EE101 'Introduction to Digital Logic'. Students are expected to know ALL the material covered in EE101, particularly combinational logic and sequential logic design. b) Course web page: BlackBoard (https://blackboard.usc.edu/) c) Classes and labs: Please refer to the course web page for class timings, classrooms, and lab timings. Labs are held in OHE336. Quiz slot: The quiz slot is created to hold common midterm exams. We meet only two times during the whole semester during the quiz slot for writing one Quiz exam and one midterm exam. d) Final Exam:

The final exam is also common to both sections of the EE201L and is held as per the exceptional exam schedule, but time extended to suit EE201L. http://www.usc.edu/academics/classes/term_20141/finals.html

e) Grading policy:

Weights: Homeworks 10% Quiz 5% Friday 02/28/2014 4:00-6:50PM (QUIZ slot extended) Midterm Exam 20% Friday 03/28/2014 4:00-6:50PM (QUIZ slot extended) Final Exam 20% Wednesday 05/14/2014 10:30AM-1:30PM (Exceptional Final, time extended) Laboratory 30% Lab attendance is mandatory. TA’s points 5% TA’s discretionary points

Final Project 10% Project demonstrations shall be in the final week of classes along with a draft of the report showing all design details. Final report is due on the day specified by your TA no later than the first day of final exams (Wed. 5/14/2014).

Attendance policy: Participation in class discussion is important in a design course like EE201L. If you miss more than 3 lecture sessions, you lose (i) 1% of course grade for each of the next two (4th & 5th) missed lectures, (ii) 2% of course grade for each of the next two (6th & 7th) missed lectures, and (iii) 3% of course grade for each of the subsequent (8th onwards) missed lectures.

f) Miscellaneous administrative matters: Major portion (75% or more) of the exams is OPEN-BOOK type. In the open-book portion of the exams, students are allowed to use any printed or hand-written (but not electronic) material such as CLASSNOTES (EE101 and EE201L), TEXTBOOK, Lab manual, HDL Quick reference guide, ICs data book, homework assignments/solutions, etc. In this course, we want to test your ability to design (and not your ability to memorize). However, you are NOT allowed to use a computer or any electronic device to search answers on the internet for the questions! Students should NOT borrow any item from other students during the exam as it helps COPYING. Academic dishonesty cases will be dealt

with severely. Using another student's work (wired circuit board, HDL code, or simulation results, in the lab or copying another student's logic simulation/FPGA implementation work or homework will earn an F grade in the course to both (note both) the students involved. However students are encouraged to discuss among themselves and share their views on homeworks/labs/project. Discussing is different from copying! When you are discussing, each of you act like a TA, who will help a student to arrive at the answer but will not give out the answer itself. Please be aware that we will be using tools for detecting software plagiarism. So, do not even think of copying. Academic dishonesty cases will be dealt with severely. USC VSoE takes academic integrity very seriously and reports cases of cheating to the SJACS. Please visit the Student Judicial Affairs and Community Standards (SJACS) Website. http://www.usc.edu/student-affairs/SJACS/pages/students/academic_integrity.html http://www.usc.edu/student-affairs/SJACS/pages/students/community_standards.html Please watch the tutorial: http://www.usc.edu/libraries/about/reference/tutorials/academic_integrity/index.php No makeup exams, sorry. Incomplete grade can only be assigned, if there is a verifiable cause, which is acceptable to the VSoE and the university.

g) Instructor and graders’ office hours:

Please refer to the course web site or a separate announcement for this information.

h) Academic Accommodations:

Any student requiring academic accommodations based on a disability, is required to register with Disability Services and Programs (DSP) each semester. A letter of verification for approved accommodations can be obtained from DSP. Please be sure the letter is delivered to me as early in the semester as possible. DSP is located in STU 301. Their phone number is (213) 740-0776. Please visit http://sait.usc.edu/academicsupport/centerprograms/dsp/home_index.html

3. Laboratory Schedule:

Please refer to the lab manual for the list of lab assignments and rules pertaining to the lab. Lab work is an important part of the course. Making a reasonable attempt at ALL lab assignments is a requirement of this course. Lab attendance is mandatory. The TAs are asked to record your attendance. You may not miss more than one lab session. You need to make up for any missed lab session/lab experiment. You may at most have one incomplete/missed lab experiment/assignment. Poor performance in the lab may result in a failing grade.

4. Readings:

The required readings are mainly from classnotes. You may like to refer to relevant sections of the textbook (Wakerly). Books: * "Digital Design Principles and Practices" by J.F. Wakerly 4th ed * Verilog Reference Guide (Esperan/Cadence) * Digital IC Data Handbook (Manufacturer Motorola/Signatics/TI) Printed copies are not available. We will use datasheets on ti.com. * Lab Manual: <= Please purchase from the book store. * Class Notes: <= Please purchase from the book store.

5. Labs :

http://www-classes.usc.edu/engr/ee-s/201/ee201l_lab_manual/AdditionalStuff/Plan.pdf

6. Course topics: I have provided a lecture-by-lecture after this sub section Most of EE201L design topics are taught by example and by performing the design and also by talking up case study analysis 6.1 A list of Verilog topics: Modules and their instantiations Net and Register Data Types Operators Initial and Always Blocks Assign Statement Sequential Statements Blocking and Non-Blocking procedural assignments Tasks (Procedures) and Functions System Tasks and Functions Synthesis Issues Tristate and Latch Inference File I/O Test Benches 6.2 Digital Design topics: Course Introduction, EE101 review, Homework #1 Logic families & their characteristics Schmitt trigger input devices, Totem-pole outputs, Open-collector

outputs, and three-state outputs, Three State Buffers

State Machine Design and Implementation One-Hot method of designing state machines Exercises on one-hot method of design, Homework #5 Design of a Micro-programmed control unit Exercises on uProg. CU design, Homework #6 Data path Design and Data Registers

Glitches in combinational logic, common misconceptions in controlling data registers, counters, etc. Homework #7 and # 8

System Design

Based on a word statement, arrive at a data path and a control unit to perform the task. Realize that one can think of a number of different designs to perform the same task, understand the difference between an informal flow chart and a formal state diagram, understand what changes will perhaps decrease the number of clocks taken without increasing the clock width and what changes imply reducing the number of clocks at the cost of widening the clock. Homework #8A

Timing Analysis Propagation delays in combinational logic, longest path and shortest path, maximum and minimum delays Setup time margin and hold time margin Homework #9 Timing analysis and Counters

Memory components SRAM, FIFO Special combinational component design

Cascading comparators, A Tree of comparators, Barrel Shifters, Logarithmic Barrel Shifters Fixed priority resolvers and Rotating priority resolvers, Priority encoders

Bus protocols Epp, I2C 7. Course Schedule: Please refer to the following page for actual topics covered in each lecture: http://www-classes.usc.edu/engr/ee-s/201/ee201_topics/ee201_topics_covered_in_lecture.txt Lecture #1: Course Intro. (DPU, CU, RTL design, HW#1 (EE101 review), Nexys-3) Lecture #2: Data Path Unit example, One-hot state machine design, Nexys-3 board introduction Lecture #3: Detour lab, Clock division using counters, displaying L/R on SSD, Verilog Introduction (Event driven Simulation) Lecture #4: HW#1 ROM for combinational logic HW#1 combinational logic implementation in 2-level logic Assign HW#5 (One-Hot method)

Verilog Lecture continuation 1_Verilog_Introduction_mht.jnt 2_module_DataTypes_in_Verilog.jnt 3_behavioral_vs_structural_Verilog.jnt Lecture #5: Verilog Lecture continuation 4_Sequential_Statements_in_Verilog.jnt 5_blocking_non_blocking.pdf Lecture #6: Mealy and Moore machines, Divider design to serve as an example of mealy design, Mealy to Moore conversion, what happens during the clock and at the end of the clock, Divider improvements, 2-digit BCD to 7-bit binary, Datapath design Lecture #7: Mutually Exclusive and All Inclusive rules, Data Register with Data Enable control, Loop Counter Incrementation and Terminal Value Checking Lecture #8: RTL coding Style, Loop counter related questions, Divider improvements, HW#7 (State Diagram Design) Quick review Lecture #9: Verilog Decade counters, Verilog Exam questions, Q#4 from Spring 2013 Midterm ee201L_sync_counter_mix_of_blocking_and_non_blocking Lecture #10: GCD design, GCD lab, Datapath design by intercept and inject method, Inches-Feet-Yards question from EE201L Sp2010 Quiz, Traffic lights question from EE201L Sp2013 Quiz, Advise them to go through Q#3 from the Spring 2013 midterm, and Q#4 from Midterm Fall 2013 midterm Lecture #11: Slack in schedule to make up any missed parts Quiz review Lecture #12: Microprogrammed CU design, Change dispenser example design Lecture #13: Microprogrammed CU design -- review of questions from previous exams -- review of HW#6 questions Lecture #14: Lab 6a Debouncing push buttons, single stepping, output-coded state machine to produce glitch-free outputs, difference between clock-enable (data-enable) and clock itself, Lecture #15: HW#8A State Diagram Design and RTL coding, Introduction to Q#1 and Q#2 of HW#8A Advise them to go through the following previous exam questions Q#2 from Spring 2013 Final exam Introduction to Q#3A and Q#3B of HW#8A Advise them to go through the following previous exam questions Q#5.1 and Q#5.2 from Fall 2013 Final Exam Lecture #16: Tristate buffers from Chapter #2, Tristate buffers as routing elements in Data path to bring the right information to a destination register Example questions on the above topic:

Q#2 from Spring 2012 Midtem Exam Q#5.3 from Fall 2013 Final Exam Lecture #17: merge sort lab, Q#3 Spring 2013 final, Q#1 of Fall 2013 Midterm, Lecture #18: General discussion of processor bus-cycle to transact with memory, Asynchronous handshake, Epp protocol, Q#6.4 Sp2013 Midterm, Q#4 Sp2013 Final, Lecture #19: Timing Design, metastable state, setup time and hold time margins, need for RESET synchronization, STA (Static Time Analysis) performed in all synthesis tools Shannon's expansion theorem and its application Q#1 from the Spring 2012 Fianl exam Timing design lab by altering the divider design Lecture #20: Metastable state avoidance, MTBF, Asynchronous inputs and single and double synchronization, Synchronization of control signals and not data (unless it is a count value represented in Gray code), clock skew and clock tree design, HW#9 discussion Lecture #21: Counters, Truncated counters, Cascading counters (Chapter #10), Example: Q# 1.4 Fall 2013 Final, Q#3 Fall 2013 Midterm Special Counters (examples: Q#5 Spring 2013 Midterm and Q#5 Midterm #2 Spring 2011) Lecture #22: Midterm review. Make up missed items Lecture #23: Memories, address pins, data pins, control pins, building larger memories from smaller memories, width and depth expansion, Lecture #24: memory map, address ranges in hex and in binary Q#1 Sp2013 Final Q#3 Fall 2013 Final Lecture #25: FIFOs, Single-clock FIFOs, two-clock FIFOs, Q#3 Spring 2009 Midterm#2 (skip Q#3.6, Q#3.7, Q#3.8) Q#5 Spring 2013 Final Q#6 Fall 2013 Final Lecture #26: Low-active signals and readable logic, Chapter-4_mux, Barrel shifters, fixed priority resolver, rotating priority resolver Q#7 Spring 2012 Final Q#4 Fall 2013 Final Lecture #27: open-collector wire-ANDing, I2C protocol, Q#4 Final Spring 2012 Lecture #28: Cascading comparison units, design from TI data sheet for 74LS85 Q#2 from Spring 2010 Midterm #2 Lecture #29: Priority Encoders, and cascading these to form bigger encoders Q#3 from Spring 2010 Midterm #2

Lecture #30: Review for the Final Exam