EDSAC in Verilog - ChipHackchiphack.org/talks/edsac-in-verilog.pdf · Real teleprinter still...

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EDSAC in Verilog Bill Purvis, September 2017 EDSAC Replica Project

Transcript of EDSAC in Verilog - ChipHackchiphack.org/talks/edsac-in-verilog.pdf · Real teleprinter still...

  • EDSAC in Verilog

    Bill Purvis, September 2017EDSAC Replica Project

  • Initial Task: Reconstruct and Validate Logic

    Starting point: Edsac Report - 1948

    Mostly text, few diagrams

  • Redraw using a home-grown Logic Editor - ELSIE

  • Next step: Simulation

    ELSIE simulates EDSAC devices

    Time step fixed at 80nSec,25 time steps = 1 EDSAC clock pulse

  • Gate-level simulation, very slow!

    Sufficient to establish confidence that the logic should work

    Run very short test programs

    Used as a basis for detailed circuit design

  • Suggestion that a Verilog implementationmight be useful

    Offer of Altera DE2 development board (Simon Moore, Cambridge University)

    Modify ELSIE to export suitable Verilog code

    Hand code Verilog to simulate EDSAC elements and ancilliary modules for I/O and display.

    Build board into case with switches etc.

  • RS232 link to PC/Raspberry Pi for virtual I/O devices:

    Virtual Paper Tape Reader

    Virtual Teleprinter

    SVGA port for memory/register displays

    Real tape reader added

    Real teleprinter still pending

  • Reimplenting with Altera DE2-115 board

    Bigger FPGA, Touch Screen

    Work in progress, display, button, but no VIO yet

  • Mini-EDSAC

    Initial version for IceStick

    Reduce to 16-bit architecture (from 35-bit)

    Simplify some orders

    Switch to ASCII tape coding

    Migrate to BlackIce board

    Needed external UART for RS232

    Register-level coding, not gate-levelParallel not serial!

  • Project proposal 1:

    Extend order set to implement B-register extension

    Three additional orders

    Project proposal 2:

    Extend to full EDSAC simulation:

    Two orders (17-bit) per word (35-bit)

    Original order set

    One additional register

    Serial arithmetic??

  • Links:

    http://www.billp.org/EDSAC

    http://www.billp.org/FPGA

    Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19


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