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Hindawi Publishing Corporation Journal of Electrical and Computer Engineering Volume 2012, Article ID 941653, 2 pages doi:10.1155/2012/941653 Editorial Clock/Frequency Generation Circuits and Systems Woogeun Rhee, 1 Antonio Liscidini, 2 Jae-Yoon Sim, 3 Kenichi Okada, 4 and Sudhakar Pamarti 5 1 Institute of Microelectronics, Tsinghua University, Beijing 100084, China 2 Department of Electronics, University of Pavia, 27100 Pavia, Italy 3 Department of Electrical Engineering, Pohang University of Science and Technology, Kyungbuk 790-784, Republic of Korea 4 Department of Physical Engineering, Tokyo Institute of Technology, Tokyo 152-8552, Japan 5 Electrical Engineering Department, University of California, Los Angeles, CA 90095, USA Correspondence should be addressed to Woogeun Rhee, [email protected] Received 20 November 2011; Accepted 20 November 2011 Copyright © 2012 Woogeun Rhee et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Clock generation and frequency synthesis systems have played a critical role in modern communication system design. As data rate increases, low-noise and low-power clock/frequency generation is getting more important than ever for high-performance digital communication systems. Timing uncertainty directly affects the overall performance of microprocessors and I/O links. The quality of wireless transceiver systems is often determined by the phase noise performance of frequency synthesizers. Active researches in the areas of clocking, data synchronization, and frequency generation have been performed for broad applications. This special issue focuses on the new and existing clock/frequency generation circuits and systems for wireline and wireless system IC designs with a special emphasis given to advanced technical results. This special issue consists of nine papers. Four papers focus on wireline applications: a paper on characterizing the jitter tracking performance of the receiver for high- speed source synchronous links, a paper on generating fault- tolerant clock for VLSI circuits, a paper on a wide lock range clock-and-data recovery (CDR) circuit, and a paper on a delay-locked-loop- (DLL-) based clock generation for USB 2.0 applications. Three papers focus on wireless applications: a paper on open-loop phase modulation techniques for wide-bandwidth transmitter design, a paper on high-speed, high-resolution autocalibration techniques for fractional-N phase-locked loops (PLLs), and a paper on a wideband LC- based voltage-controlled oscillator (VCO) design for recon- figurable radio transceivers. Other two subsequent papers present nontraditional ways of generating clock frequency: the one with an all-digital flying-adder-based method and the other with a semidigital PLL-based method. One of the major factors limiting the maximum achiev- able I/O data rates occurs from the degradation of system timing margins by clock jitter. The paper by A. Ragab et al. presents a comparative analysis of several jitter tracking architectures employed in source synchronous high-speed links. Tracking the transmit clock jitter in the presence of clock skew and channel loss enables high data rate operation in these links. The paper by G. Fuchs and A. Steininger describes a generation scheme of fault-tolerant clock based on a tick synchronization algorithm. An ASIC chip, imple- mented in a 0.18-μm CMOS, demonstrates feasibility of this scheme creating a globally synchronized clock, which is tolerant to a configurable number of arbitrary faults. For high-speed chip-to-chip communication, serial link protocol has been widely adopted in various computer- to-peripheral interfaces. The use of serial links for multi- purpose, however, still presents some challenges which must be overcome by circuit design. The paper by S.-K. Lee et al. presents a 650-Mb/s to 8-Gb/s referenceless CDR with automatic frequency acquisition. By utilizing a novel DLL-based frequency acquisition, the dual-loop CDR shows outstanding performance in terms of lock range, power consumption, and area. The USB 2.0 is one of the most popular wireline standards, but requiring a very small area and low power consumption for portable applications. For low-cost low-power clock generation, a clock generator based on an edge-combiner DLL is presented in the paper by T. Kawamoto et al. The clock generator generates 480-MHz
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Hindawi Publishing CorporationJournal of Electrical and Computer EngineeringVolume 2012, Article ID 941653, 2 pagesdoi:10.1155/2012/941653
Editorial
Clock/Frequency Generation Circuits and Systems
Woogeun Rhee,1 Antonio Liscidini,2 Jae-Yoon Sim,3 Kenichi Okada,4 and Sudhakar Pamarti5
1 Institute of Microelectronics, Tsinghua University, Beijing 100084, China2 Department of Electronics, University of Pavia, 27100 Pavia, Italy3 Department of Electrical Engineering, Pohang University of Science and Technology, Kyungbuk 790-784, Republic of Korea4 Department of Physical Engineering, Tokyo Institute of Technology, Tokyo 152-8552, Japan5 Electrical Engineering Department, University of California, Los Angeles, CA 90095, USA
Correspondence should be addressed to Woogeun Rhee, [email protected]
Received 20 November 2011; Accepted 20 November 2011
Copyright © 2012 Woogeun Rhee et al. This is an open access article distributed under the Creative Commons AttributionLicense, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properlycited.
Clock generation and frequency synthesis systems haveplayed a critical role in modern communication systemdesign. As data rate increases, low-noise and low-powerclock/frequency generation is getting more important thanever for high-performance digital communication systems.Timing uncertainty directly affects the overall performanceof microprocessors and I/O links. The quality of wirelesstransceiver systems is often determined by the phase noiseperformance of frequency synthesizers. Active researches inthe areas of clocking, data synchronization, and frequencygeneration have been performed for broad applications. Thisspecial issue focuses on the new and existing clock/frequencygeneration circuits and systems for wireline and wirelesssystem IC designs with a special emphasis given to advancedtechnical results.
This special issue consists of nine papers. Four papersfocus on wireline applications: a paper on characterizingthe jitter tracking performance of the receiver for high-speed source synchronous links, a paper on generating fault-tolerant clock for VLSI circuits, a paper on a wide lock rangeclock-and-data recovery (CDR) circuit, and a paper on adelay-locked-loop- (DLL-) based clock generation for USB2.0 applications. Three papers focus on wireless applications:a paper on open-loop phase modulation techniques forwide-bandwidth transmitter design, a paper on high-speed,high-resolution autocalibration techniques for fractional-Nphase-locked loops (PLLs), and a paper on a wideband LC-based voltage-controlled oscillator (VCO) design for recon-figurable radio transceivers. Other two subsequent paperspresent nontraditional ways of generating clock frequency:
the one with an all-digital flying-adder-based method andthe other with a semidigital PLL-based method.
One of the major factors limiting the maximum achiev-able I/O data rates occurs from the degradation of systemtiming margins by clock jitter. The paper by A. Ragab etal. presents a comparative analysis of several jitter trackingarchitectures employed in source synchronous high-speedlinks. Tracking the transmit clock jitter in the presence ofclock skew and channel loss enables high data rate operationin these links. The paper by G. Fuchs and A. Steiningerdescribes a generation scheme of fault-tolerant clock basedon a tick synchronization algorithm. An ASIC chip, imple-mented in a 0.18-µm CMOS, demonstrates feasibility ofthis scheme creating a globally synchronized clock, which istolerant to a configurable number of arbitrary faults.
For high-speed chip-to-chip communication, serial linkprotocol has been widely adopted in various computer-to-peripheral interfaces. The use of serial links for multi-purpose, however, still presents some challenges which mustbe overcome by circuit design. The paper by S.-K. Leeet al. presents a 650-Mb/s to 8-Gb/s referenceless CDRwith automatic frequency acquisition. By utilizing a novelDLL-based frequency acquisition, the dual-loop CDR showsoutstanding performance in terms of lock range, powerconsumption, and area. The USB 2.0 is one of the mostpopular wireline standards, but requiring a very small areaand low power consumption for portable applications. Forlow-cost low-power clock generation, a clock generator basedon an edge-combiner DLL is presented in the paper by T.Kawamoto et al. The clock generator generates 480-MHz
2 Journal of Electrical and Computer Engineering
10-tap output signals from a 12-MHz reference signal andconsists of three DLLs to shrink the design area so that it issmaller than the PLL-based one.
The rapid growth of new communication standardslike LTE and WiMAX has led to high data rate, widesignal bandwidth and high peak-to-average power ratio.A wide-bandwidth phase modulator is one of the keybuilding blocks for the design of next generation transceivers.The paper by N. Nidhi et al. presents open-loop phasemodulation techniques for upcoming 60 GHz wireless com-munication and software-defined radio. The open-loopmodulation technique achieves maximum flexibility withwide-bandwidth operation. In modern wireless transceiversystems, the ΔΣ fractional-N frequency synthesizer is anessential building block. Especially for a wide tuning-rangefractional-N frequency synthesizer, high-speed and high-precision automatic calibration is important for shorteningthe lock time and improving the phase noise. In thepaper by J. Shin and H. Shin, an automatic calibrationtechnique for the VCO frequency and the loop gain in thefractional-N PLL design is presented. A simple and efficientautocalibration method based on a high-speed frequency-to-digital converter significantly reduces the calibration time.
Recently, dozens of wireless communication standardshave been used for small mobile terminals, for example,GSM, UMTS, LTE, WiMAX, WLAN, Bluetooth, UWB, GPS,DTV, and RFID, and the standards use several frequencybands spreading in a quite wide range such as 800 MHzto 6 GHz. All of these RF front-ends require a wideband-tunable VCO, which is an indispensable component forthe multiband radio in common. The paper by Y. Itoet al. presents a wide-band frequency synthesizer with afrequency range from 1 GHz to 6.6 GHz by employing awide-tuning LC VCO and a tuning-range extension circuit.Such tuning allows to satisfy the requirements of all cellularand WiFi standards, becoming a very interesting solution formultistandard transceiver where the presence of several localoscillator would results in a too expensive design.
The use of advanced CMOS technologies makes thetraditional phase-locked loop (PLL) design challenging ason-chip variability and modeling inaccuracy become severein deep submicron CMOS. Large loop parameter variationmakes it difficult to find the optimum bandwidth for phasenoise, spur, and settling time. In addition, analog passivedevices become a bottleneck for scalability and integratingthe loop filter (LPF) has been a challenging task in theconventional PLL design. Therefore, clock generation basedon digital or semidigital method has received great attentionrecently. The paper by P.-L. Chen and C.-C. Tsai describesa flying-adder-based digital frequency synthesizer with aninterpolated multiplexer to improve cycle-to-cycle and rmsjitter performance. This synthesizer, fabricated in a 0.18-µm CMOS, shows a frequency lock range of from 33 MHzto 286 MHz. The paper by N. Xu et al. introduces recentsemidigital PLL architectures which relax technology depen-dency and provide low-cost low-power clock generation.With the absence of the time-to-digital converter (TDC),the semidigital PLL enables low-power linear phase detection
and does not necessarily require advanced CMOS technologywhile maintaining a technology scalability feature.
Lastly, the Guest Editors of this special issue would like tothank all the reviewers for their dedicated efforts in ensuringa high standard for the selected papers. We hope that readerswill find this issue interesting.
Woogeun RheeAntonio Liscidini
Jae-Yoon SimKenichi Okada
Sudhakar Pamarti
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