SWARNADHRA COLLEGE OF ENGINEERING & TECHNOLOGYSEETHARAMPURAM, NARASAPUR.

1I year B.Tech.MechDept. of Electronics and communication EngineeringBASIC ELECTRONICS -LAB

LIST OF EXPERIMENTS:

1. Transistor CE Characteristics (input and output).

2. Full Wave Rectifier with and without filter.

3. SCR Characteristics.

4. Single Stage RC Coupled Amplifier.

5. Feed Back Amplifier (voltage series / current series).

6. RC Phase Shift Oscillator.

7. Study of 8085 Kit (Simple Programs).

ADDITIONAL EXPERIMENTS:

These Experiments will be conducted in simulation lab. (Using Multisim software 2001).

1. RC Phase Shift oscillator.

2. Common Emitter and Common Source Amplifier.

3. Series Voltage Regulator.

1

SCET-D/ECE/BE/01

EXP: NO: 01 COMMON-EMITTER CONFIGURATION

AIM: To draw the input and output characteristics of a transistor in Common –

Emitter configuration.

EQUIPMENT &COMPONENTS REQUIRED:

S.NO. EQUIPMENT/COMPONENTSREQU IRED

SPECIFICATION QUANTITY

1 Transistor BC 107 12 Ammeter (0-200m A) 23 Voltmeter (0-1)V 14 Volt meter (0-20V) 15 Bread board WB-102 16 T.P.S. (0-30V)/1A 17 Connecting wires 108 Ammeter (0-2mA) 1

CIRCUIT DIAGRAM:

2

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THEORY:

In the circuit arrangement the input is applied between base and emitter and output is taken from collector and emitter. Here emitter is common to both the input and output terminals. Two sets of characteristics are necessary to describe the behavior of the CE configuration one for the input or base-emitter circuit and the other for the output or collector -emitter circuit.

INPUT CHARACTERISTICS:The input characteristics are a plot between the input current IB versus the

input voltage VBE for varies values of output voltage VCE.

1. The base current( IB) (μA) increases with the increase in base to emitter Voltage (VBE ) for Constant VCE . It implies that input resistance (Ri) of common emitter configuration is very high as compared to CB configuration.2. As the collector – emitter voltage (VCE ) is increased above 1v; the curves shift downwards. I t occurs because of the fact, that as VCE is increased, the depletion width in the base –region increases .the reduces the effective base width, which in turn reduces the basecurrent.3. Input resistance or dynamic (ac) input resistance of the transistor is the ratio of change inBase-Emitter voltage (VBE) to change in base current (IB) at constant Collector-EmitterVoltage (VCE).

3

VCCVBB

IB

IC

VBE

VCE

i.e., Ri =∆ VBE /∆ IB at constant VCE.Typical value of Ri is few Hundred Ohms to 4Kohms.

OUTPUT CHARACTERISTICS:These characteristics may be obtained by using the circuit shown in fig.

1. The output characteristics may be divided in to three important regions namely saturation region, active region & cut-off region. 2. As the collector – emitter voltage (VCE ) above zero, the collector current (IC )

Increases rapidly to a saturation value, depending upon the value of base current (IB). It may be noted that collector current (IC) reaches to a saturation value when VCE is about 1v.

3. When VCE is increased further, the IC slightly increases. This increase in IC is due to the fact that increased value of collector – emitter voltage (VCE) reduces the base current and hence the collector current increases this phenomenon is called an early effect. 4.When IB is zero, a small IC current exists. This is called leakage current. However all practical purposes, the collector current (IC) is zero, when IB is zero. Under this condition the transistor is said to be cut-off.

5. Output resistance (or) dynamic (ac) output resistance is the ratio of change in 6. Collector voltage (∆VCE) to the change in collector current (∆ Ic) at constant IB i.e.Ro = ∆VCE/∆ Ic at constant IB. The common – emitter output resistance of a transistor range from 10KΩ to50K.

The collector current expression is, Ic = (α/1- α) IB + ICEO ( ICEO-leakage current)

SCET-D/ECE/BE/01

IC = β IB + ICEO.

7. The characteristic may be used to determine the small signal Common-emitter current gain. (or) a.c.beta (β0) of a transistor.

(β0)= ∆ Ic /∆ IB.

PROCEDURE:

4

Cutt- offRegion

Active region

Col

lect

or c

urre

nt I C

(mA

)

Collector – emitter voltage (VCE)

IB = 0

IB = 3 (μA)

IB = 1(μA)

IB = 4 (μA)

IB = 2 (μA)

INPUT CHARACTERISTICS:

1. Connect the circuit as shown in the figure.2. The emitter to Base voltage (VBE) is varied, note down the corresponding base

Current (IB) by keeping Emitter to collector voltage (VCE) constant.3. Now change the value of VCE (for different values) repeat the above process. Tabulate the values of VBE (v)& IB (μA) for different values of VCE and Draw the graph IB (μA) verses VBE (v) for different values of VCE to obtain input characteristics.

4. Find the h- parameters: hre = Reverse voltage gain. hie = Input Resistance. (Ohm’s)

5. hie = (∆VBE/∆IB) VCE = Constant = (VBE2-VBE1)/(IB2-IB1) hre = (∆VBE /∆VCE)IB = Constant = (VBE2-VBE1)/ (VCE2-VCE1).

SCET-D/ECE/BE/01

OUTPUT CHARACTERISTICS:

Fig (2)

6. Connect the circuit as shown in fig (2)7. Keep the VCC = 15V corresponding to the given transistor.

5

C

E

B

mA

mA

VB

E

C

+_

+

+

+

+_

_ _

_

(0-2mA) ( 0 - 2 0 m A )

VCE

IB IC

DRB1 DRB2

15V

8. By adjusting the DRB1, keep the base current IB (μA) constant.9. Varying DRB2, note the corresponding the collector to emitter voltage (VCE) and collector current. IC (μA).10. For different values of IB, repeat the step (9) and tabulate the values of VCE (V) & Ic (mA) 11. Draw the graph between VCE (V) versus Ic (mA) for different values of IB to obtain output Characteristics 12. Find the h- parameters:a. hfe = forward current gain.b. hoe = output Conductance. (mho’s)

13. hfe = (∆IC /∆IB) VCE = Constant = (IC2-IC1)/ IB2-IB1) hoe = (∆IC/∆VCE) IB = Constant = (IC2-IC1)/ (VCE2-VCE1)

SCET-D/ECE/BE/01

TABULAR FORMS:INPUT CHRACTERISTICS:

S.NOVCE1 (V) VCE2 (V) VCE3 (V)

VBE(V) IB(μA) VBE(V) IB(μA) VBE(V) IB(μA)

MODEL GRAPH:

OUTPUT CHARACTERISTICS:

6

VBE (volts)Base- Emitter voltage

VBE2 VBE1

VCE1VCE2

IB2

IB1

IB (µA)

Bas

e cu

rren

t

VCE3

VCE constant

S.NOIB1 (μA) IB2 (μA) IB3 (μA)

VCE(V) IC(mA) VCE(V) IC(mA)) VCE(V) IC(mA)

SCET-D/ECE/BE /01

MODEL GRAPH:

RESULT:

The input and out put characteristics of a transistor in CE – configuration is obtained. & hie= ; hfe= ; hre= ; hoe= ;

POINTS TO BE LEARNED:

7

IC(mA)

Col

lect

or c

urre

nt

IC1

IC2

Emitter – Collector VCE (volts)VCE = constant

IB4

(µA)

IB3

(µA)IB2

(µA)

IB1

(µA)ICO

1) What is meant by transistor? (BJT)2) What are the terminals in transistor?3) What is current amplification factor?4) What does gain factor (or) transport factor means?5) What are the applications of transistor?6) What is relation between amplification factor and gain factor?7) What about early effect?8) Define drift current?9) Write down the current equation for transistor?10) Mention CE applications?

SCET-D/ECE/BE /02

EXP: NO: (2) FULL WAVE RECTIFIER

AIM: a) To observe the function and the wave forms of full wave rectifier with and with out filter. b) To calculate the Ripple factor, % of Regulation and Efficiency (η).

EQUIPMENT &COMPONENTS REQUIRED:

S.NO. Equipment/componentsRequired

Specification Quantity

1 Transformer (9-0-9) V 12 Diode 1N4007 23 Decade resistance box (DRB) (0-1) M 14 Digital millimeters (0-20v) 25 Bread board WB-102 16 Capacitor 1000μf / 25V 17 Connecting wires 10

CIRCUIT DIAGRAMS :

WITH OUT FILTER:

8

A D 1 K

Ph

N

VS = V2/2

VS = V2/2

V2V1

A D2 K RL

VS = V2/2

VS = V2/2

AC230V/50Hz

CRO(Vo)

WITH FILTER:

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THEORY: A full-wave rectifier is a circuit, which allows a unidirectional current to

flow through the load during the entire input cycle as shown in the fig1.The result of full wave rectification is a d.c output voltage that pulsates

every half-cycle of the input. There are two types of full-wave rectifiers namely center-tapped and bridge rectifier.

9

D2

V1

VS

VS

+

++

+_

_

_

_

D1

V0

+ i +

V1

VS

+

++

+_ _

D1

V0

+

i +_

+

Fig (2)

A D 1 K

Ph

N

VS = V2/2

VS = V2/2

V2V1

A D2 K RL

VS = V2/2

VS = V2/2

AC230V/50Hz

CRO(Vo)

C

Swarnandhra

WORKING:

Fig1 shows the circuit of a center-tapped full wave rectifier. The circuit uses two diodes, which are connected to the center-tapped secondary winding of the transformer. The input is applied to the primary winding of the transformer. The center-tap on the secondary winding of a transformer is, usually , taken as the ground or zero voltage reference point. It may be noted that the voltage between the center-tap and either end of the secondary winding is half of the secondary voltage,i.e.,VS=V2\2

The operation of a center-tapped full-wave rectifier:

During the positive input half-cycle, the polarities of the secondary voltage are shown in the fig2. This forward biases the diode D1 and reverse-biases the diode D2. As a result of this, the diode D1 conducts some current where as the diode D2 is off. The current through load RL is as indicated in the figure. It may be noted that current through the load flows in the same direction,

SCET-D/ECE/BE /02

during both the positive portion of the input cycle. Therefore the output voltage developed across the load RL. In full-wave rectified D.C voltage as shown in fig3.

Average values of output voltage and load current in a full-wave rectifier :Consider a center-tapped full-wave rectifier with a sinusoidal a.c. input voltage.Let Vm= Maximum value of the voltage across each half of the secondary winding.

We know that r.m.s value of secondary voltage

V2=V1*(N2/N1) & half of the secondary voltages Vs=V2/2 Therefore Max. Value of half of the secondary voltage.

Vm=√2*Vs (or) V2=√2 * VmVs = the r.m.s.value of the voltage across each half of the secondary winding.Im = Maximum value of the load current.Vdc=Average or dc value of the output voltage across the load resistor.Idc = Average or dc value of the current through the load resistor.

Vs = Vm Sin ωtWhere Vs= instantaneous value of the voltage across each half of the secondary winding Vdc=2Vm/π =0.636 Vm The Average (or) D.C value of the load current is given by relation: Idc=Vdc/RL =2Vm/(π* RL)=2Im/π = 0.636 Im (since Im= Vm/RL)

=2Im/π = 0.636Im

Peak inverse voltage:We know that each diode in a full wave rectifier is alternately forward

biased and reverse biased. The maximum value of a reverse voltage, which diode must with stand, is input to the maximum secondary voltage (i.e, 2Vm)

10

VS__ D2

Fig (3)

Consider the circuit of a center tapped full wave rectifier. It may be noted that when the secondary voltage (Vs) has the polarity as shown in the fig, the anode of the diode D1 is +Vm (where Vm is maximum half secondary voltage) and the anode of D2 is –Vm.Since D1 is forward biased/ its cathode is at some voltage as its anode (neglecting barrier potential) i.e.,+Vm.This is also the voltage on the cathode of the diode D2. Therefore the total reverse voltage across the diode D2 is

D2=Vm-(-Vm) =2VmPIV of each diode in a center tapped full wave rectifier is

PIV=2Vm PROCEDURE:

WITH OUT FILTER: 1) Connect the circuit as per diagram. 2) Keep the load resistance (DRB) fixed at Minimum 100. 3) Connect CRO across the load (RL) Keep the CRO switch in ground mode and observe the horizontal Line and adjust it to the X-axis. 4) Switch the CRO in dc mode and observe the waveform. Note down its amplitude (Vm) from the CRO screen along with multiplication factor (volts/div.). 5) Calculate Vdc using the relation Vdc= 2Vm/ π = 0.636Vm 6) Calculate Im= 2Vm/RL 7) Calculate Idc using the relation = Vdc/RL =2Im/π =0.636 Im

SCET-D/ECE/BE /02

8) Repeat the above steps by varying the load resistances (RL). 9) Calculate ripple factor () = √ (Irms /I dc)2 –1 (or) √ [(Im /√2)/(2Im/π)]2 –1 (since Im=2Vm/RL) 10) Calculate efficiency (η) of a full wave rectifier: η=[I2dc * RL] / [I2

r m s (Rf+RL)] (OR) =(0.812)/[1+(Rf /RL)]

We also know that for a full wave rectifier Idc=2Im/π ; Irms = Im/√2. Here Rf is the diode forward resistance Now efficiency will maximum, if RL>>Rf thus ηmax = 0.812 or 81.2%

WITH FILTER: 1) Connect the circuit as per diagram. 2) Keep the load resistance (DRB) fixed at Minimum 100. 3) Choose the C = 1000μF/25V and repeat the above procedure. 4) Tabulate the readings. 5) Calculate ripple factor (), efficiency (η). 6) Remove the load and measure the output voltage (dc mode) and calculate the percentage of voltage Regulation using formula

% Of regulation =(Vnoload-Vfull load)/Vfull load x 100.

TABULAR FORMS :

WITH OUT FILTER: RL(Ω) Vm (V) Im(A) Vdc(V) Idc(A) = η= %Regulation

11

WITH OUT FILTER:

RL(Ω) Vm (V) Im(A) Vdc(V) Idc(A) = η= %Regulation

SCET-D/ECE/BE /02

WAVE SHAPES:

RESULT:

Thus we observed the waveform with filter and without filter. And got the values for the parameters of Ripple factor, and % Regulation.

12

Inpu

t vol

tage

(vin

)

0

VmVm

Out

put v

olta

ge (v

out)

Timeπ 2πTime2ππ0

Fig (1)

POINTS TO BE LEARNED:1) What does rectifier mean?2) What are the types of rectifier?3) What is the theoretical efficiency for full wave rectifier?4) What is meant by ripple & ripple factor?5) Explain the operation of full wave rectifier?6) What are the applications of rectifier?7) Which is higher efficiency- half wave or full wave?

SCET-D/ECE/BE /03

EXP: NO: 03 SCR CHARACTERISTICS

AIM :

To obtain V-I (static characteristics) and firing characteristics for

the given SCR.

EQUIPMENT &COMPONENTS REQUIRED:

S.NO. EQUIPMENT/COMPONENTSREQU IRED

SPECIFICATION QUANTITY

1 Transistor power supply unit (T.P.S.unit)

0-30V 1

2 SCR 13 Resistor 300K 14 Ammeters (dc) 0-100 mA,

0-100 A11

5 Bread board WB-102 16 Volt meters (dc) 0-30V 1

CIRCIUT DIAGRAM:

13

_

THEORY:

SCR is a four layer three terminal device in which the end P-layer acts as anode, the end N-layer acts as cathode and P-layer nearer to cathode acts as gate. As leakage current in silicon is very small compared to germanium, SCRs are made of silicon and not germanium.

SCR acts as switch when it is forward biased. When the gate is kept open i.e. gate current IG=0.When IG<0, the amount of reverse bias applied at reverse biased junction is increased. So the Break over voltage VBO is increased. When IG>0, the amount of reverse bias applied at reverse biased junction is decreased thereby decreasing the break over voltage. With very large positive gate

SCET-D/ECE/BE /03

Current break over occur at a very low voltage. Characteristics of SCR are similar to PN diode. As the voltage at which SCR is switched ON can be controlled by varying the gate current IG, it is commonly called as controlled switch. Once SCR is turned ON, the gate loses control i.e. the gate cannot be used to switch the device OFF .One way to turn the device OFF is by lowering the anode current below the holding current IH by reducing the supply voltage below holding voltage VH, keeping the gate open.

CALCULATIONS:1). Maximum gate current required is 100μA and the available supply voltage

VGG is 30V Rg ≤ VBB/IG = 30/100* 10-6 = 300K

2) Maximum allowable anode voltage VBB= 100V and anode current is limited to 100Ma RL= VBB/IB = 100/100* 10-3 = 1K

PRL= Power dissipation of RL = Ib2. RL = (100*10-3) 2 * 103 = 10 Watts

PROCEDURE : 1. Make connections as shown in circuit diagram. (Fig 1) 2. By increasing VGG set the gate current to Ig1 say (40A), go on increasing the plate Supply voltage VBB and read this voltage by V1 across anode and cathode. When this voltage is Equal to the firing voltage ( Vf ) of SCR, the voltmeter V1 suddenly deflects back to a low value Say < 1V) and the SCR fires and anode current suddenly jumps and is read by millimeter I2. Note down the reading of the voltmeter V1 when it deflects back and at this point the anode Current is approximately equal to zero.

14

(0-100A)

Rg

VGGVBB

_

Fig (1)

3. After deflection of voltmeter to approximately 1V note down this voltage and corresponding anode Current .Now further increase the anode supply voltage VBB

and note down the corresponding .Anode current IB and anode to cathode voltage VAK (V1). Repeat this process until VBB= 100V and

Tabulate the result in Table1. 4. Repeat the above procedure for different gate currents Ig2, Ig3 (42A,44A) etc and tabulate.

TABULAR FORM:Ig1 =A Ig2 = A I g =AVB volts IB mA VB volts IB mA VB volts IB mA

Vf1

--

0--

Vf2

--

0--

Vf3

--

0--

100 100 100

SCET-D/ECE/BE /03

5. The resultant characteristics are as shown below in fig (2).

These are called V-I characteristics. The voltage across anode and cathode VAK

after firing is called Maintenance potential.

V-I Characteristics of SCR fig (2).

6.The second part of the experiment is to obtain the firing characteristics of the SCR for different Values of gate current Ig1, Ig2 , Ig3---------- etc; repeat the steps 1 and 2 and tabulate as shown in table.

TABULAR FORM:

Ig in A Vf

15

1V 10 20 30 VB 100V

10 2

0 30

40

VAK

=V0

Ig3 Ig1 Ig2

Ano

de c

urre

nt

Anode to cathode voltage

Ib

100w

40 A

The resultant characteristics are as shown in below fig. (3)

SCET-D/ECE/BE /03

OBSERVATIONS:1.It is observed that SCR acts as a closed switch after firing and the drop across

switch after firing is<1volt. Therefore the entire applied voltage VBB impressed across RL after

SCR fires.2. Before firing SCR almost acts as open circuit, therefore the voltage across RL

is zero and VAK = VBB.3.For higher gate currents the SCR fires at lesser firing potentials.

4.When once SCR fires gate looses its control over the device.5.Gate gains control over SCR if VBB is less than maintenance potential (VAK V0)

NOTATIONS: VGG=Gate supply voltageVBB=Plate supply (Anode supply voltage)

RESULT:Thus the V-I Characteristics of SCR are observed.POINTS TO BE LEARNED :

1. Explain how SCR acts as control switch.2. What is the application of SCR?3. Obtain indirectly the gate current required for the given A.C. anode supply

voltage of the given circuit to fire SCR at Vm sin 450 fig (4)

16

Vf i

n vo

lts

Ig in A

+

++

Fig (3)

4. Draw the two transistor model of SCR device and explain its operation and how gate looses its Control over the device after firing?

5.For the fig shown in Q (3) if SCR fires at 600 draw the voltage waveform across RL and across Device relationship for Idc Idc =(2 Vm/πRL)*(1+COS) Where = firing angle 6.In question (5) if =0 what is the circuit called as? 7. Sketch VRL for the given circuit shown in fig5

SCET-D/ECE/BE /03

17

Rs

RL

Vm sinωt

Fig (4)

+VGG

_

RgSCR1 SCR2

RL

A.CI/P

Fig (5)

SCET-D/ECE/BE /04

EXP.NO 04 SINGLE STAGE RC COUPLED AMPLIFIER.

AIM: To design a single stage R.C Coupled amplifier and hence determine

its gain and gain bandwidth product from it’s frequency response.

EQUIPMENT &COMPONENTS REQUIRED:

S.NO.EQUIPMENT/COMPONENTSREQU IRED

SPECIFICATION

QUANTITY

1 Transistor SL 100 12 Bread board WB 102 13 T.P.S. (0-30V)/1A 14 Connecting wires 105 Resistors To be disigned6 Capacitors 0.47F, 47F 27 C.R.O. 20MHz 1

18

CIRCUIT DIAGRAM:

T HEORY :

This is most popular type of coupling because it provides excellent audio fidelity over a wide range of frequency. It is generally used for voltage amplification. Coupling capacitor Cc is used to connect the output of the first stage to the base of second

SCET-D/ECE/BE/4

Stage and it allows ac and blocks dc. The resistor R1, R2 and Re form the biasing and stabilization network. By pass capacitor Ce offers low reactance path to the signal.When ac signal Vin is applied to the base of transistor, its amplified output appears across the collector resistor Rc.It is given to the second stage for further amplification and signal appears across the collector resistor Rc.It is given to the second stage for further amplification and signal appears with more strength. At this point, Vout can be measured by either VTVM or CRO.

Self-Bias circuit:

DESIGN:

Let Vcc = 12 V

19

Ic = 4.5 mA = For SL 100 Choose VRE = Vcc/10 =? IE * RE RE = VRE /IE

= VRE /IC RE =?

Choose VCE = Vcc/2 From the circuit

Vcc- Ic * Rc - VCE - VRE = 0 Rc =? K. VB = VRE + VBE =?

IB = Ic/ =? Assume 10 IB is flowing through R1 &

9 IB is flowing through R2

R1 = Vcc-VB/ 10IB Use R1 =? R2 = VB/9IB

R2 =?

SCET-D/ECE/BE /04

Let XCE = RE/10 at f=100Hz 1/(2fCE) = RE/10 CE =(2fRE )/10

Use CE = 50F Electrolytic UseCC1 = CC2 = 0.47F ceramic.

PROCEDURE:

(i) Connections are made as shown in fig (1)(ii) Measure the D.C. voltage Vb, Vc, VE

Vce=Vc-VE

I c = (Vcc-Vc)/RC Q-point=(VCE, IC)

(iii) Feed a sine wave of 100mV(p-p) from signal generator.(iv) Vary the input frequency from 100Hz to 1MHz in suitable steps and

Measure the output voltage V0.

(v) Tabulate the readings and find the gain in db.(vi) Plot its frequency response.

TABULAR FORM:

S.NO Frequency (Hz) V0(volts) Av=V0/Vi G=20log AV in db

20

OBSERVATIONS:

V CC = VC = V E = VB = IBE = ICE = I C =

Q-Point:

SCET-D/ECE/BE /04

MODEL GRAPH:

-3db

Gain in db

f1 f2

Frequency (hz)

Calculation:

f1 =

f2 =

Bandwidth = ( f2-f1 ) =Gain at half power point =Gain bandwidth Product =

21

RESULT:

Thus a R-C coupled amplifier was constructed and its frequency response was Plotted.

Gain bandwidth product =

Bandwidth =

POINTS TO BE LEARNED:

1. Why R.C coupled amplifier is used in audio applications?2. What do you know about bandwidth in R.C coupled amplifier?3. What are the applications?4. What is the expression for gain?5. Advantages & Disadvantages?6. What is the need for the capacitor CE.

7. What is the function of coupling capacitor?

SCET-D/ECE/BE /05(A)

EXP NO.05 (A) CURRENT SERIES FEEDBACK AMPLIFIER

AIM: To observe the effect of feedback in common emitter. Amplifier and plot the frequency response of an amplifier with variation in feedback.

EQUIPMENT&COMPONENTS REQUIRED:

S.No

EQUIPMENT/COMPONE         NT REQUIRED

SPECIFICATION QUANTITY

1. Transistor CL100 1 2. Capacitors 10F, 47 F 1,1 3. T.P.S. UNIT (0 – 30V) 1 4. D.R.B. (0 – 1M) 1 5. C.R.O 20MHz 1 6. Function Generator 1MHz 1 7. Bread board 1 8. Connecting wires 10 9. Resistors 1,R2, Rs, Re, Rc,

RL

CIRCUIT DIAGRAM:

22

CL1001KRs1kohm 10kohm47uFC210uF C310uF

12VVCC=

V1

SCET-D/ECE/BE /05(A)

THEORY: It is called a series- derived series-fed feedback connection. A block diagram

of a current – series feedback connection is shown in figure. In this connection a fractionof the output current is converted into a proportional voltage by the feedback network andthen applied in series with the input. It can be shown easily that the current – series feedback connection increases both the input resistance and the output resistance of a feedback amplifier by a factor equal to (1+β AV). Thus R’I (1+ β AV) Ri and R’o = (1+ β AV)Ro

FEEDBACK RATIO ():

From the figure, it is possible to calculate the approximate value of feedback ratio

Vo’=IcRL, and Ve=IeRe=(Ic+Ib)Re IcRe

23

RC

R2

R1

DRB RL

RE CE 20mV100Hz

Amplifier AVVin

β

RL

Β .VO

IO

Therefore, =Ve/Vo’=IcRe/IcRL = Re/RL

INPUT RESISTANCE (Rif): The equation for input resistance Rif and voltage gain Af for the

common emitter amplifier in figure, with an unbiased emitter resistor Re can be calculated using the circuit drawn for ac quantities.

Input resistance, Rif =Vi/Ii=(Vi’+Ve)/Ii=(Vi’/Ii) + (Ve /Ii)But the input impedance without feedback, Ri=Vi’/IiAlso, Ve=IeRe and Ii=Ie-IcTherefore, Rif= Ri+ieRe/(ie-ic) = Ri+Re/(1-ic/ie)But we know that Ic/Ie=hfb=hfe/1+hfeWhere hfb and hfe are common base and common emitter short-circuited current gain, respectively.Therefore, Rif=hie+(1+hfe)ReThus, we find that there is large increase in the value of input resistance due to negative feedback.Input resistance without feedback, Ri= hie

Thus, Rif=hie+(1+hfe)ReIf the bias resistance, R=R1||R2=R1R2/R1+R2 is considered, the effective input resistance with feedback is Rif’=Rif//R.

SCET-D/ECE/BE /05(A)VOLTAGE GAIN (Af)

We know that Af=AiRL/Rif and Ai= -hfeTherefore, Af=(-hfeRl)/(hie+(1+hfe)Re)

Voltage gain without feedback, A=(-hfeRL/hie)Therefore we find that there is a large decrease in voltage gain due to negative feedback.OUTPUT RESISTANCE (Rof )

The expression for the output resistance Rof looking back into the collector involves Rs, Re, and all the h-parameters. For values of Re in the order of RSand hfe ,an appropriate expression for Rof is Rof=(1+hfe)/hoe=1/hob

This has usually a large value in the range of M, so the overall output resistance Rof’ taking the load resistance RL into consideration is approximately RL . DESIGN:

Vcc=12vIc=Ie=4.5mA;Vre=Vcc/10;Re= Vre/ Ie;Vce=Vcc/2;VB=Vbe+Vre;=1+hfe;Ib=Ic/;R1=(Vcc-VB)/10Ib;R2=Vb/9Ib;

PROCEDURE:1. Connect the ckt. As per circuit. Diagram.2. Set the DRB resistance to min. value.

24

3. Apply 20mv (p-p)/ 100Hz signal at the input and observe theOutput voltage.4. Repeat the above step by varying the frequency of signalGenerator from 50Hz to 1 MHz.5. Set the DRB to 50, 100&150…

6. Repeat the above steps.7. Plot the frequency response.

MODEL GRAPH:

DRB=1 DRB= 50

DRB=100

SCET-D/ECE/BE /05(A)

TABULAR FORMS: DRB=1

DRB=50

Frequency (Hz)

Output voltage(Vo) In volts

Gain = Vo/Vi

Gain in dB=20 log(Vo/Vi)

25

Frequency (Hz)

Gai

n in

(dB

)

Frequency (Hz)

Output voltage (Vo) In volts

Gain = Vo/Vi

Gain in dB=20 log(Vo/Vi)

DRB=100

Frequency (Hz)

Output voltage (Vo) In volts

Gain = Vo/Vi

Gain in dB=20 log(Vo/Vi)

SCET-D/ECE/BE /05(A)

RESULT: The effect of feedback in Common Emitter amplifier is observed.

And the frequency response of different loads has been observed.

POINTS TO BE LEARNED:

1. Why it is called as current series feed back connection?2. What are the features of current series feedback?3. How the gain bandwidth product is maintained varied by employing a

feedback?4. Limitations of a feedback amplifier?

26

SCET-D/ECE/EDC/05 (B)

EXP: NO: 05 (B) VOLTAGE SERIES

FEED BACK AMPLIFIER

AIM: To design and test the voltage series feedback amplifier and to

calculate the following parameters with and with feedback.1. Mid band gain.2. Bandwidth and cut-off frequency.3. Input and output impedance.

EQUIPMENT AND COMPONENTS REQUIRED: -

EQUIPMENT/COMPONENTSREQUIRED

SPECIFICATION QUANTITY

1 Transistor BC 107 12 Capacitors 1µF, 33 µF 1,13 Bread board WB-102 14 T.P.S. (Transistorised Power Supply) (0-30V)/1A 15 Resistors Designed values 1 Each

27

6. C.R.O. (0-20) MHz 17

8.

Function Generator

Connecting wires

(0-1) MHz 1

10

CIRCUIT DIAGARAM: -WITHFEED BACK:

Circuit (1)

SCET-D/ECE/EDC/05(B)

WITHOUT FEEDBACK:

THEORY: -

It is also called a shunt-derived series-fed feedback connection. A block diagram of a voltage-series feedback connection is as shown in figure. In this connection, a fraction of the output voltage is applied in series with the input

28

Ci

Cc++

VCC

VO

Vi

Rf1

RE1R2

RC1

R4

R2R1

Rf

RC2

RE2

Cf

CE2

Co

CE2

+

+

+ +_

__

_

_

_

Ci

Cc++

VCC

VO

Vi

Rf1

RE1R2

RC1

R4

R2R1

RC2

RE2CE2

Co

CE2

+

+ +_

__

_

_

voltage through the feedback network. However. The input to the feedback network is in parallel with output of the amplifier.

It can be shown easily that the voltage-series feedback connection increases the input resistance and decreases the output resistance of the feedback amplifier.

SCET-D/ECE/BE/05(B)

DESIGN: -DC Analysis:

For DC analysis (f = 0), all the capacitors are open-circuited, hence circuit (1) reduces to circuit (2).

Circuit (2):-

Apply Kirchhoff ‘s voltage law to the output loop,VCC = IC1RC1 + VCE1 +IE1RE1

VE1 =IE1(RE1 + Rf1)29

Amplifier AVVin

β

VO

Β .VO

RC1R1

R2 RE1

Rf1

Q1

+VCC

RC1R1

R2 RE1

Q1

+VCC

Feed back Network

VE1 =(IC1 +IB1) (RE1 +Rf1)VE1 ≈ IC1 (RE1 +Rf1)

Where, base current IB1 is very small compare with collector current IC1, hence neglected.

Feedback factor, β = Rf1 / (Rf1 + Rf2) Where, Rf2 >> Rf1.

The voltage at the base is the sum of voltage across base – emitter junction VBE1

And voltage across the emitter resistance VE1 i.e.,VB1= VBE1 + VE1 --------(1)

The base voltage can also be calculated by voltage divider concept i.e., VB1 = VCC.R2 / (R1+R2) ---------(2) On comparing equations (1) and (2) we get

VBE1 + VE1 = VCC R2/ (R1+R2) From the equation for stability factor is obtained as,

S = 1+RB1/RE1

Where, RB1 = R1 || R2 = (R1R2) / (R1+R2)

SCET-D/ECE/BE/05(B)

To operate the given circuit in an active region, assume the voltage dropbetween collector and emitter is half of the supply bias voltage. Then the

operation point set at the center of the DC load lime and offers maximum swing to the input signal i.e.,

VCE =( VCC) / 2 Similarly, the voltage drop across the emitter resistance will assumed to be (VCC)/10 to ensure better stability to the circuit from the above discussion, one can find the values of all biasing resistances.DC Analyses of second stage is same as that of first stage. Therefore, the same DC design holds good for second stage too.Summary of design:

VCC= IC1 RC2 +VCE2 +IE2+RE2

VE2 = IE1 RE2VB2 =VBE2+VE2

VB2 = VCC R4 /(R3+R4)VBE2 + VE2 = VCC R4/ (R3+R4)S=1+ RB2/RE2

Where RB2 = R3|| R4 = R3R4 /(R3+R4)VCE2 = (VCC)/2

VE2 = (VCC)/10From the above discussion, one can find the values of all biasing resistance of

second stage.AC parameters analysis of second stage: - without feedback network output resistance R02.The output resistance is the resistance of the circuit when look back from theinput terminal of the circuit.

R02 = [RC2 || (Rf1 +Rf2)] (current source is open-circuited) R02 = RC2 (RC2 (Rf1+Rf2) / (Rf1+Rf2+Rf2 Input resistance,Ri2:

30

The input resistance is the resistance of the circuit when look back from the input terminal of the circuit.

Ri2 = (RB2 ||hie2) Ri = RB2 hie2 /(RB1+hie2)

Where RB2 =R3||R4

Voltage gain of second stage, AV2

The voltage gain is the ration of output voltage to the input voltage. AV2 = VO2/Vi2 = -hfe2 Ro2/hie2

Where, hie = hfe x ( 26x10-3) / IE

AC parameter analyses of first stage: -The output resistance is the resistance of the circuit when look back from the output terminal of the circuit.

R01 = (RC1 || Ri2) (current source is open-circuited)Input resistance, Ri1

SCET-D/ECE/BE/05(B)

The input resistance is the resistance of the circuit when look from the input terminal of the circuit.

Ri1 = RB1 || [hie1 + (1+ hfe1) (Rf1 ||Rf2)]Voltage gain of first stage, AV1

AV1 = Vo1/Vi = -hfe1 Ro1 / [hie1 + (1+hfe1) (Rf1 ||Rf2)] Where hie = hfe x (26 x 10-3) /IE

Over all voltage gain of the system, AV

AV = V02/Vi =AV1 x AV2

AV = (-hfe1.R01 / [hie1 + (1+hfe1) (Rf1 ||Rf2)]) x hfe2. R02/hi

Feedback factor, βThe expression for feedback factor β can be obtained from the AC model.

The voltage drop across the feedback resistance Rf1 is given by, Vf1 = V0 Rf1/(Rf1+Rf2) Vf1/V0 = Rf1 / (Rf1 + Rf2) = β

De-sensitivity factor, D The de-sensitivity factor is given by

D = (1 + βAv), D= (1+Rf1/ (Rf1 + Rf2)) x AAC parameter analyses: with feedback network

Input resistance, Rif

Rif = Ri x D Output resistance, Rof

Rof = R0/DVoltage, gain Avf : Avf = AV/D Data given VCC = 10V; IE1= 3mA;n IE2 2.5 mA hfe1 = hfe2 =200 (obtained from the millimeter); fL =1KHz; S= 5; β= -0.03.

DC Analysis of second stage VCC = IC2 RC2 + VCE2 +VE2

The drop across the transistor (active condition) is given by,31

VCE2 = VCC/2 = 5VThe voltage across the emitter resistance is given by,

VE2 = VCC/10=1The value of collector resistance is given by,

RC2 = (VCC – VCE2 –VE2)/IC2 = 1.6 OhmsThe feed back factor is given by,

β = Rf1/ (Rf1+Rf2) =0.03 Rf2>>Rf1

Assume, Rf2 = 5K Ohms, then Rf1 = 156.5OhmsThe value of emitter resistance is given by,

RE2 = VE2//IE2 = 400OhmsThe voltage at the base is the sum of voltage across base-emitter junction VBE2

and voltage across the emitter resistance VE2 i.e., VB2 = VBE2 + VE2 = 1.7V ----------(1)

The base voltage can also be calculated by voltage divider concept i.e., VB2 = (VCC R4) / (R3+R4) ------(2)

On comparing equation (1) and (2), we get VBE2+VE2 = (VCC R4) / (R3+R4) =1.7V ----------(3)

The equation for stability factor is obtained as, S= 1+(RB2/RE2) RB2 = (S-1) RE2 = 1.6kOhms ---------(4)

SCET-D/ECE/BE/05(B)

Where, RB2 = R3||R4 =( R3R4) / (R3+R4)On solving the equation (3) and (4) we get

R3 = 9.4Kohms; R4 = 1.93KohmsTo operate the given circuit in an active region, assume the voltage drop

between collector and emitter is half of the supply bias voltage. Then the operating point set at the center of the

DC load line and offers maximum swing to the input signal i.e.,VCE =VCC/2

Similarly, the voltage drop across the emitter resistance will assumed to be VCC/10 to ensure better stability to circuit.DC Analysis of first stage:

VCC = IC1 RC1 + VCE1 +IE1 RE1

The drop across the transistor (active condition is given by, VCE1 = VCC/2 = 5VThe voltage across the emitter resistance is given by,

VE1 = VCC/10 = 1VThe value of the collector resistance is given by

RC1 = (VCC – VCE1 – VE1)/IC1 =1.33KohmsThe drop across the emitter terminal and the ground is given by,

VE1 = (RE1+Rf1)IE1

The value of the emitter resistance is given by RE1 =333.3ohms

The voltage at the base is the sum of voltages across base-emitter junction VBE1 and voltage across the emitter resistance VE1 i.e.,

VBE1 = VBE1 + VE1 = 1.7V ------------(1)The base voltage can also be calculated by voltage divider concept i.e.,

VB1 = VCCR2/(R1+R2) ----------(2)On comparing equation (1) and (2) we get

VBE1 + VE1 = VCC R2 / (R1+R2) = 1.7V ---------(3)The equation for stability factor is obtained as,

S = 1+(RB1/RE2) RB1 = (S-1) RE1 = 1.33 K ohms

32

Where RB1 = R1 || R2 = R1+R2 /(R1+R2) ------(4)On solving equation (3) and (4), we get

R1 =7.8K ohms; R2 = 1.6Kohms.

AC parameters analyses of second stage: Output resistance, R02

The output resistance is the resistance of the circuit when look back from the Output terminal of the circuit.

R02 = [RC2 || (Rf1+Rf2)] =1K ohms Input resistance, R12

The input resistance is the resistance of the circuit when look back from the Input terminal of the circuit.

Ri2 = (RB2 || hie2) = 888.9 ohmsWhere, RB2 = R3 ||R4

Voltage gain of second stage, AV2

The voltage gain is the ratio of output voltage to the input voltage. AV2 = -hfe2 R02 /hie2 =100 (40dB)

Where, hie = hfe x (26x10-3)/IE = 2K ohmsAC parameters analyses of the first stage: With feedback network Output resistance, R01

R01 = (RC1 ||Ri2) = 527.9 ohms Input resistance, Ri1

SCET-D/ECE/BE/05(B)

Ri1 = RB1 || [hie1 + (1+hfe1) (Rf1 || Rf2)] = 1.28K ohms Voltage gain of first stage, AV1

AV1 = (-hfe1R01) / [hie + (1+ hfe1) (Rf1||Rf2)] = 61(35.7dB)Where hie = hfe x (26x10-3)/IE = 1.73K ohmsOver all voltage gain of the system, AV

AV = AV1 x AV2 = 6100 (75.7 dB)Output resistance, Rof

Voltage gain, AVF AVF = AV/D = 33.152 (30.41dB)

Output capacitor, Co XCO << ROF

XCO = ROF/10 1/(2π FL CO)= 5.43/10 CO = 293μF

Input capacitor,C1

XCi<Rif XCi=Rif/10 1/2π FL Ci = 235.5 x 103/10 Ci = 0.67 μFCoupling capacitor,CC

XCC << RO1

XCC = RO1/10 1/ 2π FL CO = 527.9/10 CC = 3 μF

Emitter capacitor of the first stage, CE1

XCE <<R1E

Where R1E= RE1 [hie +RB1/hfe1]

XCE1 =R1E/10

1/2π FL CE1 = 14/10 CE1 = (11.3) 68 μF

33

XCE <<R11E

Where, R11E = RE2 || [hie2 +RB2/hfe2]

XCE1 = R11E/10

1/2π FL CE1 = 17.2/10 CE1 = 92.5 μF

PROCEDURE: -1. Connect the circuit x per the circuit diagram.2. Set Vi (say), using the signal generator.3. Keeping the input voltage constant, vary the frequency fro 0Hz to 1MHz in regular steps and note down the corresponding output voltage.4. Plot the graph gain (dB) Vs frequency.5. Find the input and output impedance. Input impedance,Zi = (ViRS) / (VS+Vi)

Output impedance,ZO = ((Vload – Vnoload) / ( Vload )) x 100%6. Calculate the bandwidth from the graph.

7 Note down the phase angle, bandwidth, input and output impedance. 8. Remove the R12 and C12 from the figure (2) and follow the

same procedures (1to7).

SCET-D/ECE/BE/05(B)

TABULARFORM: -WITH FEEDBACK:Vi = 20mV

FREQUENCY Vo (volts) GAIN = VO/Vi GAIN (dB) = 20log (VO/Vi)

WITH OUT FEEDBACK:Vi = 20mV

FREQUENCY Vo (volts) GAIN = VO/Vi GAIN (dB) = 20log (VO/Vi)

MODEL GRAPH:

34

SCET-D/ECE/BE/05(B)

RESULT:

Theoretical Practical With f/b Without f/b With f/b Without f/b

Input impedance

Output impedance

Gain (Mid band)

Bandwidth

POINTS TO BE LEARNED:-

1. What is feedback?2. What are the advantages of the voltage series feedback amplifier?3. What is the 3dB frequency?4. What is the difference between the voltage series feedback and current series

Feed amplifier?

35

With out feedback

With feedback

fL2 fL1 fh1 fh2

Frequency (Hz)

(AV) d

B

-3dB-3dB

SCET-D/ECE/BE/06

EXP. NO: 06 RC PHASE SHIFT OSCILLATOR

AIM: To design, Construct and test a RC phase shift oscillator circuit and to measure it’s designed frequency (fo).

EQUIPMENT&COMPONENTS REQUIRED:

S.N0 EQUIPMENT/COMPONENTREQUIRED

SPECIFICATION

QUANTITY

1. Transistor CL100 1 2. T.P.S unit 0- 30V 1 3. CRO 20 MHz 1 4. Capacitors (CC, C) 10F, 47µF 1,3 5. Resistors (R1, R2, R) To be designed 1,1,3

CIRCUIT DIAGRAM:

36

C.R.OCL 100

R1

R2 R R

R

RC

1kCC

10uF

C CC

RE47uF

VCC = 12V

CE

SCET-D/ECE/BE/06

THEORY:

RC phase shift oscillator is an audio frequency or low frequency LF oscillator. It is uses a CE amplifier whose output is given to there RC networks. The phase shift produced by the CE amplifier is 1800. Since an oscillator requires a phase shift of 00 or 3600,the addition 1800 phase shift is obtained using three RC networks with an individual shift of 600 each.

CIRCUIT OPERATION:The circuit starts oscillating if there is any inherent noise in the transistor

or any variations in the power source. With this input at the base, the amplifier produces a collector current. The voltage at the collector is amplified and shifted by 1800 in phase. This fed to the RC network shifts the phase by 1800 and feeds the signal in phase with the base current.

This increases the base bias and so collector current Ic increases. This is again fed to the base through RC network in phase and so base current Ib

increases. This process continues to vary Ic between its saturation and cut-off values resulting in oscillations. The oscillations are sustained since the amplifier replaces the lost energy.

ANALYSIS:Now let us determine the conditions to design the above circuit to provide

continues oscillations. We known from Barkhausen’s criterion,

Aβ = 1

Where A = Vo/Vi & β = Vf /Vo

Therefore, Aβ = (Vo * Vf) / (Vi * Vo) = Vf / Vi = 1 or Vf = Vi

To determine Vf from the circuit let us follow the below procedure.

DESIGN:

37

1. The device used in this circuit is a BJT, which is relatively low input resistance device. Therefore this low impedance comes in parallel with output resistor of the feedback network. Hence it is desirable to use voltage shunt feedback as shown in fig.The frequency of oscillation of this circuit is given by fo=1/[2π RC√ (6+4K)]Where K=RC/R and the maintenance condition is given by h fe > 4K+23+(29/K). Which shows that hfe is minimum for K=2.7 and 44.5.Therefore transistor Q with hfe less than 45 cannot be used in this circuit.** Select an n-p-n transistor whose hfe is greater than 50.

2. The Min value of R is determined by hie of the transistor since R=hie+R1

let us consider BC 107transistor whose hfe >100 and hie is 2kΩ and assume R’=200Ω

SCET-D/ECE/BE/06

R=hie + R1 =?3. Calculate RC Value for K=2.7using K=RC/R

Therefore RC =K*R=? Therefore Use Rc≡ 10kΩ pot as shown in circuit diagram.

4. Calculate the value of C by substituting R, K, and fo in the equation.

And assume fo and then calculate the ‘C’ value.

fo=1/[2π RC√ (6+4K)]

Therefore C= 1/[2π R fo√ (6+4K)]

5.VB the bias voltage =IBRB+VBE+IERE

Where RB=R1 parallel R2 & RE ≈ hie and S≈10 =1+(RB/RE)Therefore 10 =1+(RB/RE)Therefore RB=9RE =?Assume Vcc=12v

To select R1, the quiescent collector voltage (VCQ) must be found. Since the voltage at the collector swings from 12v to 12* [RE /(RC+RE )Therefore The collector swing is from 12v to 3v

The mid. voltage (VCQ) is (12+3)/2 =7.5vCalculate the quiescent collector current is given by ICQ = (VCC-VCQ)/RC =?

Therefore IBQ = (ICQ )/β where β = 1+hfe

VCC * [R2 /(R1+R2)]=IBRB+VBE+IERE

VCC * [R2 /(R1+R2)]=(IC/hfe) RB+VBE+IERE

Therefore (R2)/(R1+R2)=?Since RB =(R1R2)/(R1+R2)=? And (R2)/(R1+R2)=?Calculate R1 ≈?Calculate R2 ≈?Choose fmin =100HzCE=1/(2πfmin XCE)=?Therefore Use CE =47µF.

38

PROCEDURE:

1. Make connections as shown in circuit diagram using designed values.2. Connect CRO as shown at the output.3. Obtain waveform on the screen by adjusting RC to get the waveform

Without any distortion.4. Record its amplitude and frequency.5. Compare these values with theoretical values and give your comments.6. Obtain the output waveform at each RC section also.7. Using actual output and output at each RC obtain phase shift on CRO

Using lessojious figures.

SCET-D/ECE/BE/06TABULAR FORM:

THEORITICAL FREQUENCY (KHz)

PRACTICAL FREQUENCY (KHz)

R (Ω)

C(µF)

Model graph:

RESULT:

1. The frequency of oscillations for the given values of R and C are observed on the CRO.2. Practical values are compared with the theoretical values.

POINTS TO BE LEARNED:

1. What is the purpose of RC phase shift network?2. List the applications of RC phase shift network?3. What is the range of frequency generated by RC phase shift network?4. What is the phase shift offered by each RC section of the network?5. Discuss the conditions under which an amplifier behaves as an oscillator?

39

Volts

Time0 Π 2Π

6. What is the phase shift introduced by a single RC section? At what Frequency does it become 60o ?

7. By how much does the CR, feedback network alternate the input signal?8. The low input resistance of BJT loads the CR network. Design a circuit to minimize the loading effect?9. How do you vary the frequency of the phase shift oscillator? Do you Envisage any difficulty?10. Derive the equations:a) fO = 1/[2RC (6+4k)]

Where K = RC /R. b) h fe > 4K+23+(29/K).

11. What type of the feedback are employed in BJT circuit and FET circuit and why?12. What is the phase shift offered by each RC section of the network?

SCET-D/ECE/BE/07

EXP. NO: 07 STUDY OF 8085 KIT (SIMPLE PROGRAMS).

AIM: To study the 8085 Microprocessor. And programming.

EQUIPMENT&COMPONENTS REQUIRED

1. Microprocessor kit 80852. Connectiong wires.

THEORY:

FEATURES:1. It is an 8-bit microprocessor i.e. it can accept, process, or provide 8-bit

data simultaneously.2. It operates on a single +5v power supply connected at Vcc; power supply ground is connected to Vss.3. It operates on clock cycle with 50% duty cycle.4. It has on chip clock generator. This internal clock generator requires tuned circuits like LC, RC or crystal. The internal clock generator divides

oscillator frequency by 2 and generates clock signal, which can be used for synchronizing external devices.

5.It can operate with a 3MHz clock requency.The 8085A-2 version can operate at the maximum frequency of 5MHz.

40

6. It has 16 address lines, hence it can access (2 16) 64Kbytes of memory.7. It provides 8 bit I/O addresses to (2 8 ) 256 I/O ports.8. In 8085, the lower 8-bit address bus (A0 to A7) and data bus (D0 to D7) are multiplexed to reduce number of external pins. But due to this, external hardware (latch) is required to separate address lines and data lines.

9. It supports 74 instructions with the following addressing modes:a) Immediate b) Register c) Direct d) In direct e) Implied.

10. The arithmetic Logic Unit (ALU) of 8085 performs: a) 8-bit binary addition with or without carry b) 16-bit binary addition. c) 2 digit BCD addition. d)8-bit binary subtraction with or without borrow f) 8-bit logical AND, OR<EX-OR, complement (NOT) , and bit

shift operations. 11. It has 8-bit accumulator, flag register, instruction register, six 8-bit

general purpose registers (B, C, D, E, and L) and two 16-bit registers (AP and PC).Getting the operand from ht general purpose registers is more faster than from memory. Hence skilled programmers always prefer

general purpose registers to store program variables than memory. 12. It provides five hardware interrupts: TRAP, RST 7.5, RST 6.5,

and RST 5.5 AND INTR. 13. It has serial I/O control which allows serial communication. 14. It provides control signals (IO-M, RD, WR) to control the bus cycles,

and hence external bus controller is not required.

SCET-D/ECE/BE/07

15. The external hardware (another microprocessor or equivalent master) can detect which machine cycle microprocessor is executing using status signals (IO/M, S0, S1).this feature is very useful when more than one processors are using common system resources (memory and I/O) devices).16. It has a mechanism by which it is possible to increase its

interrupt handling capacity.17. The 8085 has an ability to share system bus with Direct Memory

Access controller. This features allows to transfer large amount of Data I/O device to memory or from memory to I/O device with high speeds.

18. It can be used to implement three chip microcomputer with supporting

I/O devices like IC 8155 and IC 8355.

ARCHITECTURE OF 8085:

It consists of various functional blocks as listed below.

1. Registers2. Arithmetic and Logic Unit.3. Instruction decoder and machine cycle encoder.4. Address buffer.5. Address/Data buffer.6. Incrementer/decree, enter Address Latch.

41

7. Interrupt control8. Serial I/O control.9. Timing and control circuitry.

SIGNALS OF 8085 CAN BE CLASSIFIED INTO SEVEN GROUPS ACCORDING TO THEIR FUNCTIONS ;

1. Power Supply and frequency signals.2. Data bus and Address bus.3. Control bus.4. Interrupt signals.5. Serial I/O signals.6. DMA signals.7. Reset signals.

8085 HAS SEVEN MACHINE CYCLES:

1. Opcode Fetch.2. Memory Read.3. Memory Write.4. I/O Read.5. I/O Writes.6. Interrupt Acknowledge.7. Bus idle.

SCET-D/ECE/BE/07

INSTRUCTION SET OF 8085:

1. MVI R, data (8)2. MVI M, data (8)3. MOV rd,rs4. MOV M,rs5. MOV rd, M6. LXI rp, data (8)7. STA addar8. LDA addar9. SHLD addar10. LHLD addar11. STAX rp12. LDAX rp13. XCHG

ARITHMETIC GROUP:

1. ADD r2. ADD M3. ADI data (8)4. ADC r5. ADC M

42

6. ACI data (8)7. DAD rp8. SUB r 9. SUB M10. SUI data11. SBB r 12. SSB M13. SBI data (8)14. DAA15. INR r16. INR M17. INX rp18. DCR r19. DCR M 20. DCX rp

PROGRAM:

43

44

.

45