ECG With DRL-Sch_Completa+Sim-TexIn_slau516
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JANUARY 5, 2012 | EDN 35 [www.edn.com] E CG (electrocardiography) is the science of con- verting the ionic depolarization of the heart to a measurable electrical signal for analysis. One of the most common challenges in the design of ana- log electronics interfaces to the electrodes or to patients is optimization of the DRL (driven-right- leg) circuit, which is often added to biological-signal amplifiers to reduce common-mode interference and to increase perform- ance and stability. Using Spice to help in this effort can greatly simplify the process. In an ECG front end, the DRL amplifier provides a com- mon electrode bias at the reference voltage, V REF , and feeds back the inverted common-mode noise signal, e NOISECM , to reduce the overall noise seen at the inputs of the instru- mentation amplifier’s gain stage. The positive and negative ECG sources, ECG P and ECG N , are split to show how the DRL amplifier provides the common reference point for a portion of the ECG signal that is seen at the positive and the negative inputs of the instrumentation amplifier (Figure 1). The parallel RC (resistance/capacitance) combination for the left arm, the right arm, and the right leg repre- sents the lumped passive-electrode connection impedances, which are 52 kΩ and 47 nF. Assuming that e NOISE couples parasitically into the inputs, the feedback of e NOISECM will reduce the overall noise signal at each input, leaving the task of either externally filtering the residual noise or having the CMRR reject the instrumentation amplifier’s common- mode noise. Figures 2, 3, and 4 show the variation in CMRR of the common-mode test circuit with the varying gain of the DRL amplifier. These plots show that you can achieve the best low- frequency CMRR with no feedback resistor, yielding infinite gain. In reality, however, eliminating the dc path, setting RF to a high value, or using both of these methods may be impractical for applications that require the linear operation Use Spice to analyze DRL in an ECG front end BY MATTHEW HANN • TEXAS INSTRUMENTS UNDERSTAND THIS CRITICAL ANALOG FRONT END FOR THIS UBIQUITOUS, VITAL ECG MEDICAL INSTRUMENT. Figure 1 The positive and the negative ECG sources, ECG P and ECG N , split to show how the DRL amplifier provides the common reference point for a portion of the ECG signal that the positive and negative inputs of the instrumentation amplifier sees. − + R R INSTRUMEN- TATION AMP OR PGA − + − + R I V REF R F C P2 C P1 BUFFER AMP DRL AMP RIGHT LEG RIGHT ARM LEFT ARM E NOISE E NOISECM ECG P ECG N
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ECG With DRL-Sch_Completa+Sim-TexIn_slau516
Transcript of ECG With DRL-Sch_Completa+Sim-TexIn_slau516
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january 5, 2012 | EDN 35[ www.edn.com ]
ECG (electrocardiography) is the science of con-verting the ionic depolarization of the heart to a measurable electrical signal for analysis. One of the most common challenges in the design of ana-log electronics interfaces to the electrodes or to patients is optimization of the DRL (driven-right-
leg) circuit, which is often added to biological-signal amplifiers to reduce common-mode interference and to increase perform- ance and stability. Using Spice to help in this effort can greatly simplify the process.
In an ECG front end, the DRL amplifier provides a com-mon electrode bias at the reference voltage, VREF, and feeds back the inverted common-mode noise signal, eNOISECM, to reduce the overall noise seen at the inputs of the instru-mentation amplifiers gain stage. The positive and negative ECG sources, ECGP and ECGN, are split to show how the DRL amplifier provides the common reference point for a portion of the ECG signal that is seen at the positive
and the negative inputs of the instrumentation amplifier (Figure 1).
The parallel RC (resistance/capacitance) combination for the left arm, the right arm, and the right leg repre-sents the lumped passive-electrode connection impedances, which are 52 k and 47 nF. Assuming that eNOISE couples parasitically into the inputs, the feedback of eNOISECM will reduce the overall noise signal at each input, leaving the task of either externally filtering the residual noise or having the CMRR reject the instrumentation amplifiers common-mode noise.
Figures 2, 3, and 4 show the variation in CMRR of the common-mode test circuit with the varying gain of the DRL amplifier. These plots show that you can achieve the best low-frequency CMRR with no feedback resistor, yielding infinite gain. In reality, however, eliminating the dc path, setting RF to a high value, or using both of these methods may be impractical for applications that require the linear operation
Use Spice to analyze DRL in an ECG front end
By Matthew hann texas instruMents
UnDERStanD thiS CRitiCaL anaLoG fRont EnD foR thiS UbiqUitoUS, vitaL ECG mEDiCaL inStRUmEnt.
figure 1 the positive and the negative ECG sources, ECGP and ECGn, split to show how the DRL amplifier provides the common reference point for a portion of the ECG signal that the positive and negative inputs of the instrumentation amplifier sees.
EDN MS4430 Fig 1.eps DIANE
+
R
RINSTRUMEN-TATION AMP
OR PGA
+
+
RI
VREF
RF
CP2
CP1
BUFFER AMP
DRL AMP
RIGHT LEG
RIGHT ARM
LEFT ARM
ENOISE
ENOISECM
ECGP
ECGN
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36 EDN | january 5, 2012 [ www.edn.com ]
of the DRL amplifier when one of the input amplifiers leads is removed.
Once you determine the gain of the DRL amplifier, the next step is to inject a small signal step in the loop and moni-tor the output response (Figure 5). In this case, the response shows a strong output oscillation, indicating instability in the
loop (Figure 6). The dominant feedback path causing this instability is the feedback path for the body, the electrode, and the instrumentation-amp feedback path around the DRL amplifier. A test circuit allows you to separate and analyze the feedback and the open-loop-gain curve of the DRL amplifier on a bode plot (Figure 7).
figure 2 You can achieve the best low-frequency CmRR with no feedback resistor, yielding infinite gain.
EDN MS4430 Fig 2.eps DIANE
++
++
+
+
++
+ +RG
RG
REF
VCC
VCC
VOUT
VREFIC1
OPA333
IC3OPA2314
IC2OPA2314
IC4INA826
R12500k
RG16.1k
C533 pF
C61 nF
R452k
C247 nF
RPROT1100k
RPROT2100k
RPROT3100k
C733 pF RG2
6.1k
C101 F
R752k
RI10k
R610k
RF100k
C447 nF
CRLD47 nF
C111 nF
RRLD52k
R11M
R91M
VREF
VCC
V1
VCC
VCM
VCC
VREF
5V
figure 4 Gain is higher in circuits with no DRL drive.
CMRR(dB)
80
RF=100 k100
120
140
160
1801 10 100 1k 10k
FREQUENCY (Hz)
RF=10 k
RF=1 M
RF=10 M
RF=100 M
figure 3 Eliminating the dc path, setting Rf to a high value, or using both of these methods may be impractical for applica-tions that require linear operation of the DRL amplifier when you remove one of the input amplifier leads.
CMRR(dB)
20
40
60
80
160
180
100
120
140
1 10 100 1k 10k 100k
FREQUENCY (Hz)
NO DRL DRIVE
-
EDN MS4430 Fig 5.eps DIANE
++
++
+
+
++
+ +RG
RG
REF
VCC
VCC
VOUT
VREFIC1
OPA333
IC3OPA2314
IC2OPA2314
IC4INA826
R12500k
RG16.1k
C533 pFC6
1 nF
R452k
C247 nF
RPROT1100k
RPROT2100k
RPROT3100k
C733 pF
RG26.1k
C101 F
R752k
RI10k
RF10M
C447 nF
CRLD47 nF
RRLD52k
R11M
R91M
VREF
VCCECGN
VCC
VTEST
VCC
VREF
ECGP
V15V
figure 5 once you determine the gain of the DRL amplifier, the next step is to inject a small signal step in the loop and monitor the output response.
ECGN
ECGP
VOUT
VTEST
2.3
1.3
2.4
2.7
1.3
2.3
100m
100m0 25 50 75 100
TIME (SEC)
figure 6 the response shows a strong output oscillation, indi-cating instability in the loop.
Without an external compensation network, the beta-distribution curve approaches the open-loop-gain curve at a rate of closure greater than 20 dB per decade, indicating instability. To address this issue (Figure 8), add series resis-tor RC and capacitor CC (Figure 9) in the local feedback of the DRL amplifier. ZC then becomes the dominant feedback path between 20 and 30 kHz. The result for the simulation in Figure 7 is represented by the beta (feedback) curve in Figure 10. Figure 11 shows the full circuit of the DRL with compensation. Figure 12 shows the compensated beta-curve plots, employing variations in RC and CC. The overall beta curve intersects the open-loop-gain curve with a rate of clo-sure that is 20 dB per decade or less and a loop gain with a phase margin greater than 45 (Figure 13).
Spice can be a useful tool to quickly help analyze and opti-mize the performance and stability of the DRLs front-end cir-cuitry. Keep in mind that the simulation is only as good as the models, so it is important to correctly model key specifications, such as noise, open-loop gain, open-loop output impedance, and CMRR versus frequency, before analysis and design.EDN
AcknowledgmentThis article originally appeared on EDNs sister site, Planet An-alog, http://bit.ly/uDHbXT.
january 5, 2012 | EDN 37[ www.edn.com ]
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38 EDN | january 5, 2012 [ www.edn.com ]
EDN MS4430 Fig 7.eps DIANE
++
++
+
++
+ +RG
RG
REF
VCC
VCC
VREFIC1
OPA333
IC3OPA2314
IC2OPA2314
IC4INA826
R12500k
RG16.1k
C533 pF
C61 nF
R452k
C247 nF
RPROT1100k
RPROT2100k
RPROT3100k
VORLD
VREF
C733 pF
RG26.1k
C101 F
R752k
R310k
C1ONE TURN
L1ONE TURN
C447 nF
CRLD47 nF
RRLD52k
R11M
R91M
VREF
VCC
VCC+
VTEST
VCCVREF
V15V
figure 7 a test circuit allows you to separate and analyze the feedback and the open-loop-gain curve of the DRL amplifier on a bode plot.
figure 8 Without an external compensation network, the beta-distribution curve approaches the open-loop-gain curve at a rate of closure greater than 20 db per decade, indicating instability.
EDN MS4430 Fig 8.eps DIANE
++OPA2314
VORLD
C3ONE TURN
L2ONE TURN
RF10M
RI10kRC
CC
VREF
VREF
+
VG1
VCCVREF
figure 9 add series resistor RC and capacitor CC in the local feedback of the DRL amplifier.
EDNMS4430 Fig 9.eps DIANE
CCRC
VCC
VREF
++
OPA2314
RF10M
figure 10 the result for the simulation in figure 7 is represented by the beta curve.
GAIN(dB)
120
100
80
60
40
20
01 10 100 1k 10k 10M1M100k
FREQUENCY (Hz)
BETA CURVE, INSTRUMENTATION-AMP/ELECTRODE FEEDBACK ZC=RC, CC
ZC=10 k, 200 pFOPEN-LOOP GAINZC=10 k, 800 pFZC=10 k, 2 nFZC=10 k, 4 nF
-
figure 11 the full circuit of the DRL includes compensation.
EDNMS4430 Fig 10.eps DIANE
+ +RG
RG IC4INA826
IC1OPA333
RG16.1kC5
33 pFC6
1 nF
C247 nF
C447 nF
CRLD47 nF
RRLD52k
C733 pF
C34 nF
RG26.1k
RPROT1100k
R452k
R752k
RI10k
R210M
RF10k
RPROT2100k
RPROT3100k
VCC
VCC
VCC
REF
C101 F R12
500k
+ VREF
IC3OPA2314
VCC
VREF
VREF
+
+
IC2OPA2314
+
+
VORLD
R11M
V15V
R91M
VREF
VCC
+
+
figure 12 the compensated beta-curve plots employ varia-tions in RC and CC.
figure 13 the overall beta curve intersects the open-loop-gain curve with a rate of closure that is 20 db per decade or less and a loop gain (a) with a phase margin greater than 45 (b).
GAIN(dB)
60
40
20
01 10 100 1k 10k 10M1M100k
FREQUENCY (Hz)
OPEN-LOOP GAINZC=RC, CCZC=10 k, 200 pFZC=10 k, 800 pFZC=10 k, 2 nFZC=10 k, 4 nF
GAIN(dB)
(b)
(a)
PHASE()
1201008060
180
135
90
45
4020
0
0
1 10 100 1k 10k 10M1M100k
FREQUENCY (Hz)
Authors biogrAphy
Matthew William Hann is a precision-analog-applications man-ager at Texas Instruments. He has more than a decade of prod-uct expertise, which includes temperature sensors, difference am-plifiers, instrumentation amplifiers, programmable-gain amplifi-ers, power amplifiers, and TIs line of ECG analog-front-end devices. Through his role as an applications engineer, Hann has
developed a focused expertise on the design of analog front ends for medical applications, such as ECGs, electroencephalograms, electromyograms, blood-glucose monitoring, and pulse oximetry. Hann received a bachelors degree in electrical engineering from the University of ArizonaTucson. You can reach him at [email protected].
january 5, 2012 | EDN 39[ www.edn.com ]
