ECEN689: Special Topics in Optical Interconnects Circuits ...€¦ · Sam Palermo Analog &...
Transcript of ECEN689: Special Topics in Optical Interconnects Circuits ...€¦ · Sam Palermo Analog &...
Sam PalermoAnalog & Mixed-Signal Center
Texas A&M University
Lecture 8: VCSEL TXs
ECEN689: Special Topics in Optical Interconnects Circuits and Systems
Spring 2020
Announcements• Reading
• Sackinger Chapter 8
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• Light Amplification by Stimulated Emission of Radiation
• Light Oscillation by Stimulated Emission of Radiation• Lasers are optical oscillators that emit coherent light through the
process of stimulated emission• 3 Elements in all lasers
• Amplifying Medium• Pumping Process• Optical Feedback (Cavity)
What is a Laser?
3
[Fejer]
Semiconductor Diode Lasers
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• Can be made with simple p-n junction• Based on transitions between bands
• Direct bandgap materials necessary• Si isn’t GaAs, InP
• Pumped electrically with current source• Efficient device requires confinement of both carriers
and photons• Leads to the use of heterostructures
[Verdeyen]
Edge Emitters & VCSELs
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• Edge Emitters• Advantage
• Historically easier to manufacture• Disadvantages
• Emit light in an elliptical mode• Higher testing and packaging costs
• VCSELs – Vertical Cavity Surface Emitting Lasers• Advantages
• Can make 2-D arrays• Emit light in a circular output mode• Smaller device Lower operating
currents• Lower testing and packaging costs
• Disadvantage• Hard to manufacture due to growth of
high reflective mirrors
[Verdeyen]
VCSEL Light-Current-Voltage (LIV) Curve
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ITH = 700A = 0.37mW/mA
AW Efficiency Slope
IPIIP THo
VCSEL Model
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Ca Ra
RmCpp‐DBR
n‐DBR
Anode
Cathode
OxideQW 1
cP
LossOutput mirror
Back mirror
aGain
cN
2 g
Output power
aI
1opt cP P
Cp(Ts) Ca(Ts, Ib)
Rm(Ts, Ib)
Ra(Ts, Ib)V
I Ia
+
-
Va
+
-+-
Electrical Input Stage
aI
Optical Output Stage
Vdc(Ts, Ib)
copt PP 1
i a thc cg
T I I TdN PTdt q h
c cg c sp
c
dP PT P Tdt
• Capture thermally-dependent electrical and optical dynamics• Provide dc, small signal, and large-signal simulation capabilities
10Gbps VCSEL Electrical Model
Models finite Q pad capacitance, mirror series resistance, and junction RC
Frequency response dominated by current dependent RJCJ f3dB about 6.5GHz with I≥3mA
RJ Current
Laser Rate Equations
Two coupled differential equations describe the electron density (N) and the photon density (Np) interaction
psp
GNNNqVI
dtdN
:Equation RateDensity Electron
Rate of electrondensity change
Injected electronsgeneration
Non-radiative & spontaneousemission recombination
Stimulatedemission
recombination
p
p
spspp
p NNGNNdt
dN
:Equation RateDensity Photon
Rate of photondensity change Stimulated
emission Spontaneous emission
Photons loss dueto optical
absorption andscattering
lifetimephoton
tcoefficienemission sspontaneou tcoefficienemission stimulated
umecavity vol current injected
p
sp
GVI
VCSEL Rate EquationFrequency Response
p
pdc
sppdc
pdcmgac
GNGNj
GNq
hvvIP
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)I tonal(Proportio avgp
pdcR
GN
p
pdc
sppdc
GN
GN
2
1
tcoefficien lossmirror
velocitygroup g
m
10Gb/s VCSEL Frequency Response
THavg IIBW
D. Bossert et al, "Production of high-speed oxide confined VCSEL arrays for datacom applications," Proceedings of SPIE, 2002.
VCSEL Reliability
Mean Time to Failure (MTTF) is inversely proportional to current density squared
Failure time modeled with lognormal distribution
Higher mechanical stress reduces flip-chip bond reliability
Trade-off between reliability and bandwidth
37311
2j
ATk
E
ejAMTTF
4
1BW
MTTF
M. Teitelbaum and K. Goossen, "Reliability of Direct Mesa Flip-Chip Bonded VCSEL’s," LEOS, 2004.C. Helms et al, “Reliability of Oxide VCSELs at Emcore,” Proceedings of SPIE, 2004.
Laser Rate Equations – Transient Response
• Laser step response displays relaxation oscillations due to low damping
• Turn-on delay (td) occurs if the laser is biased below threshold– Causes data-dependent jitter
TH
spd IIIIt
1
01ln
Turn-on Delay
[Honeywell]
• VCSELs also have additional unwanted frequency modulation called chirp
• The linewidth in this case can be approximated as
Chirp
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.or theis where
122
t factorenhancemenlinewidth meterchirp para
Bc
• The parameter relates the change in optical frequency to the change in optical power
tPdtdtf outln
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• Directly modulated lasers have positive values, implying that for a rising edge the laser will blue-shift (higher frequency/shorter ) and red-shift for a falling edge
• VCSELs have occasional spontaneous emissions which add amplitude and phase noise to it’s coherent light output
• The resulting intensity fluctuations are known as relative intensity noise (RIN)
• At the receiver, this will get converted to an equivalent electrical noise component by the photodetector which is approximately proportional to the received signal power
Relative Intensity Noise (RIN)
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power!laser theincreasingby SNR improvet Can'
1
is SNR resulting The dB/Hz.in measured noise RINlaser thezingcharacteriparameter a is Here
,2
2
2,
2
nRINn
PIN
nPINRINn
BWRINiISNR
RIN
BWIRINi
RIN Power Penalty
16
dB
GHziISNR
HzdBRIN
HzdBRINn
PIN 351016.3
1010
1
is SNR thebandwidth, noisereceiver 10GHz a and /135 laser with a Assuming
3
10/135
,2
2
• This SNR is fine for digital NRZ signaling, but may be an issue for analog optical links for applications such as cable TV
• RIN noise does introduce an additional power penalty
dBPP
BWRINQPP
n
069.0016.1
1016.31035.71
1ispenalty power 10BER theexample, above For the
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32
12-
2
Temperature-Dependent Performance
• Optical power-current-voltage (L-I-V) response is temperature-dependent
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23oC
80oC
25Gb/s
• Bandwidth is bias and temperature dependent
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Ib=6mA
Ib=5mA
Ib=4mA
Ts=23oC
Ib=6mA
Ib=5mA
Ib=4mA
Ts=80oC
Measured and Simulated 25Gb/s Eye Diagrams
VCSEL Performance Issues• Threshold Current
– Reduced with smaller devices, better electron/photon confinement (quantum wells)
• Bias Dependent Frequency Response– Proportional to Sqrt(Ibias)– Low damping factor causes relaxation oscillations in step response
• Turn-On Delay– Leads to data-dependent jitter if biased below threshold
• Chirp– Direct amplitude modulation also modulates the frequency of the
optical carrier– Leads to dispersion in optical fiber– Reason why most long-haul systems use external modulation
Laser Drivers
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• Current-mode drivers are often used due to the laser’s linear L-I relationship
• In addition to the high-speed modulation current IM, laser drivers must also supply a bias current IB to ensure a minimum frequency response and/or eliminate turn-on delay
Current-Mode VCSEL Driver
Laser Drivers
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• The total laser current depends on whether the high-speed modulation current is DC- or AC-coupled
• DC-coupled case
Current-Mode VCSEL Driver
MBLBL IIIII 1,0, current level-0 theiscurrent bias The
• AC-coupled case
2
2
current average theiscurrent bias The
1,0,M
BLM
BLIIIIII
Termination Strategies
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• The laser interface with the driver determines whether double or “back” termination is necessary
• Reflections from bondwires and any laser/transmission-line mismatch can degrade high-speed performace
• Driver on-die termination improves this at a power cost
Active Back Termination
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• While not a major issue for relatively low-power VCSELs, the lost current with on-die driver termination is a concern for high-power (long-haul) lasers
• This motivates the use of active back termination circuitry where the termination resistor is connected to an AC voltage generated by a replica stage
• Ideally, without reflections, no voltage drop is across RT
25Gb/s VCSEL Link
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• Current-mode output driver• Bandwidth extension achieved with on-die shunt-peaking
termination in the output stage and with Cherry-Hooper preamplifier stage
[Proesel ISSCC 2012]
Multiplexing FIR Output Driver
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• 4-tap FIR filter implemented in driver to compensate for VCSEL frequency response
S. Palermo and M. Horowitz, “High-Speed Transmitters in 90nm CMOS for High-Density Optical Interconnects," ESSCIRC, 2006.
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Tap Mux & Output Stage
5:1 multiplexing predriver uses 5 pairs of complementary clock phases spaced by a bit time
Tunable delay predriver compensates for static phase offsets and duty cycle error
VCSEL TX Optical Testing
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Wirebonded 10Gb/s VCSEL
VCSEL 16Gb/s Optical Eye Diagrams
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Iavg=6.2mA, ER=3dB
w/ Equalization
IDC = 4.37mAIMOD = 3.66mA
IDC = 3.48mAI= -0.70mAI0 = 4.36mAI1 = -0.19mAI2 = 0.19mA
Equalization increases vertical eye opening
45% at 16Gb/s
No Equalization
Equalization Performance
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ER=3dB ER=6dB
14Gb/s35% less Iavg
138% increase in MTTF4Tap Eq
No Eq
• Maximum data rate vs Average current• Min 80% eye opening & <40% overshoot
• Equalization allows lower average current for a given data rate
• Linear equalizer limited by VCSEL nonlinearity
PAM2 VCSEL Driver w/ 2-Tap Nonlinear FFE
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• VCSEL’s bias-dependent frequency response results in nonlinear transient pulse responses
• A 2-tap non-linear equalizer with different equalization taps for high and low pulses provides performance improvement
[Raj CICC 2015]
PAM4 VCSEL Driver w/ 2.5-Tap Nonlinear FFE
• A 2.5-tap nonlinear equalizer, with the first pre-cursor weight only dependent on the MSB, is a good compromise between complexity and performance 31
1,11,00,10,0S-1
1,11,00,10,0S0
1,11,00,10,0S+1
3-tap equalizer
1,11,00,10,0S-1
1,11,00,10,0S0
1,X
0,X
S+1
2.5-tap equalizer with the pre-cursor weight only a function of the MSB
Serializing VCSEL TX & Output Stage
• VCSEL transmitter serializes 16 bits or 8 PAM-4 symbols
• Output stage is a 5-bit non-uniform current-mode DAC• MSB and MSB-1 set the main PAM-4 symbol levels• 3 LSB currents implement the 2.5-tap equalizer with the symbol
pattern selecting the weighting from the 32X3 LUT32
VDD VCSEL
VCSEL
DummyLoad
SYDAC Code
EQDAC Code
000
111000
111000
111000
111
00
SYDAC Code
EQDAC Code
Incr
easi
ng V
CSEL
Cur
rent
IBLEED
EQD
AC
DnDbn
VCAS
VBIAS
DnDbn
VCAS
VBIAS
DnDbn
VCAS
VBIAS
DnDbn
VCAS
VBIAS
SYDA
C
0110
11
0001
1011
Uniform DAC Nonuniform DAC
000
111000
111000
111000
111
I0
Output Driver
32x3 lookup table
8:1 Serializer
SYDAC<2>x20
SYDAC<1>x10
EQDAC<3>x4
EQDAC<2>x2
EQDAC<1>x1
Output
8x3
Serializer Clocks
3 bit32:1 MUX
3 bit32:1 MUX
3 bit32:1 MUX
3 bit32:1 MUX3 bit32:1 MUX
3 bit32:1 MUX
3 bit32:1 MUX
3 bit32:1 MUX
8x5
8:1 Serializer
LUT & EQ
PRBS-15
Sel
16 2 bit delay logic
2 bit delay logic
2 bit delay logic
2 bit delay logic
2 bit delay logic
2 bit delay logic
2 bit delay logic
2 bit delay logic
32x3
8x5
16
8x2
8x2 2
3
Clocking UnitCLKNC
LKIN
Shunt-Peaking CML Input & Buffer Stages
CML-to-CMOS
CLKP
Fixed Pattern
Serializing VCSEL TX 5-b Non-Uniform Current DAC Driver
50Gb/s PAM4 Experimental Results
• Core transmitter area is 0.2mm2
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No Equalization 2-Tap Linear
2.5-Tap Linear 2.5-Tap Nonlinear
• 2.5 tap nonlinear equalizer improves eye height and timing alignment of the 3 PAM4 eyes
[Tyagi PTL 2018]
Next Time• Mach-Zehnder Modulator (MZM) TX
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