Elaborado por: Florangel Villegas Verdú ECEN Carmen Andrés Jiménez ECEN Marlon Rojas Sandí PAA
ECEN 468 Advanced Logic Design - Computer...
Transcript of ECEN 468 Advanced Logic Design - Computer...
ECEN 468 Lecture 26 2
Operators
Operator Number of Operands
Result
Arithmetic 2 Binary word Bitwise 2 Binary word
Reduction 1 Bit Logical 2 Boolean value
Relational 2 Boolean value Shift 1 Binary word
Conditional 3 Expression
ECEN 468 Lecture 26 3
Arithmetic Operators
v 2’s complement representation v MSB is sign bit v For scalar and vector v For nets and registers
Symbol Operator
+ Addition
- Subtraction
* Multiplication
/ Division
% Modulus
ECEN 468 Lecture 26 4
Bitwise Operators
~(101011) = 010100 (010101) & (001100) = 000100 (010101) ^ (001100) = 011001
Symbol Operator
~ Bitwise negation
& Bitwise and
| Bitwise inclusive or
^ Bitwise exclusive or
~^, ^~ Bitwise exclusive nor
Shorter word will extend to the size of longer word by padding bits with “0”
ECEN 468 Lecture 26 5
Reduction Operators
v Unary operators v Return single-bit value
Symbol Operator
& Reduction and
~& Reduction nand
| Reduction or
~| Reduction nor
^ Reduction xor
~^, ^~ Reduction xnor
&(101011) = 0 |(001100) = 1
ECEN 468 Lecture 26 6
Logical Operators
v Case equality operators detect exact bit-by-bit match, including “x” or “z”
v The logical equality operator is less restrictive, “x” is returned for any ambiguity
v Verilog is loosely typed - OK to use A&&B when A and B are vectors o A&&B returns true if both words are
non-zero integers
v === can recognize ‘x’ and ‘z’ while == would return ‘x’ for ambiguity
Symbol Operator
! Logical negation
&& Logical and
|| Logical or
== Logical equality
!= Logical inequality
=== Case equality
!== Case inequality
ECEN 468 Lecture 26 7
Relational and Shift Operators
v Relational operators return ‘x’ for ambiguity
v 0xxx > 1xxx returns 1
if ( ( a < b ) && ( a >= c ) ) result = a << 3;
Relational operators Shift operators
< <<
<= >>
>
>=
ECEN 468 Lecture 26 8
Conditional Operator
Y = ( A == B ) ? C : D; wire [1:0] select; wire [15:0] D1, D2, D3, D4; wire [15:0] bus = (select == 2’b00) ? D1 :
(select == 2’b01) ? D2 : (select == 2’b10) ? D3 : (select == 2’b11) ? D4 : 16’bx
v “z” is not allowed in conditional_expression v If conditional_expression is ambiguous, both
true_expression and false_expression are evaluated bitwisely according to the truth table to get the result
? : 0 1 X
0 0 X X
1 X 1 X
X X X X
ECEN 468 Lecture 26 9
Operands
v A Verilog operand may be compose of o Nets o Registers o Constants o Numbers o Bit-select of a net or a register o Part-select of a net or a register o A function call o Concatenation of any of above
ECEN 468 Lecture 26 10
Operator Precedence
Operator precedence Operator symbol
Highest - ! ~ (unary)
* / %
+ - (binary)
<< >>
< <= > >=
== != === !==
& ~&
^ ^~ ~^
| ~|
&&
||
Lowest ? :
Parentheses for precaution !
ECEN 468 Lecture 26 11
Synthesis of Arithmetic Operators
v If corresponding library cell exists, an operator will be directly mapped to it
v Synthesis tool may select among different options in library cell, for example, when synthesize an adder o Small wordlength -> ripple-carry adder o Long wordlength -> carry-look-ahead adder o Need small area -> bit-serial adder
v Implementation of “*” and “/” o May be inefficient when both operands are variables o If a multiplier or the divisor is a power of two, can be implemented
through shift register
ECEN 468 Lecture 26 12
Synthesis of Shift Operators
v Synthesis tools normally support shifting by a constant number of bits
v Cannot support a variable shift
ECEN 468 Lecture 26 13
Relational Operators
Relational operators ( <, >, >=, <= ) can be implemented through o Combinational logic
o Adder/subtractor • In bit-extended format • Calculate A – B, check extended bit of result
• 0 -> A >= B • 1 -> A < B
module compare ( lt, gt, eq, A, B ); input A, B; output lt, gt, eq;
assign lt = ( A < B ); assign gt = ( A > B ); assign eq = ( A == B );
endmodule
ECEN 468 Lecture 26 14
Synthesis of Identity Operators
v The logical identity operators ( ==, != ) and the case identity operators ( ===, !== ) are normally synthesized to combinational logic
ECEN 468 Lecture 26 15
Reduction, Bitwise and Logical Operators
v They are translated into a set of equivalent Boolean equations and synthesized into combinational logic
ECEN 468 Lecture 26 16
Conditional Operator
v The conditional operator ( ? … : ) synthesizes into library muxes or gates that implement the functionality of a mux
v The expression to the left of ? is formed as control logic for the mux
ECEN 468 Lecture 26 17
Concatenation Operator
v Equivalent to a logical bus v No functionality of its own v Generally supported by synthesis tool