ECE473 Computer Organization and...
Transcript of ECE473 Computer Organization and...
![Page 1: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/1.jpg)
1 ECE473
Processor: Combined Datapath
ECE473 Computer Architecture and Organization
Lecturer: Prof. Yifeng Zhu
Fall, 2014
Portions of these slides are derived from:
Dave Patterson © UCB
![Page 2: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/2.jpg)
2 ECE473
Where are we?
• Want to build a processor for the MIPS instruction subset: – Memory reference (lw, sw),
– Arithmetic-logical (add, sub, and, or, slt), and
– Branch (beq, j)
• Last class we looked at simplified datapath for each subset
• Today we review them in similar fashion and begin to put together a datapath for all three subsets
• Coming next: Corresponding control unit design
• To read along, see Sections 5.3 and 5.4
![Page 3: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/3.jpg)
3 ECE473
PC
Instructionaddress
Instruction
Instruction
memory
Add Sum
a. Instruction memory b. Program counter c. Adder
AddressReaddata
Data
memory
a. Data memory unit
Writedata
MemRead
MemWrite
b. Sign-extension unit
Signextend
16 32
Simple Implementation
• Include the functional units we need for each instruction
Why do we need this stuff?
Readregister 1
Readregister 2
Writeregister
WriteData
Registers ALUData
Data
Zero
ALUresult
RegWrite
a. Registers b. ALU
5
5
5
Registernumbers
Readdata 1
Readdata 2
ALU operation4
![Page 4: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/4.jpg)
4 ECE473
RTL Code for MIPS add
1. Fetch
Instruction = ROM[PC], PC=PC+4
2. Read Operands
ALUOp1 = Registers[rs-value],
ALUOp2 = Registers[rt-value]
3. Add
ALUOut = ALUOp1+ALUOp2
4. Write Result
Registers[rd-value] = ALUOut
![Page 5: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/5.jpg)
5 ECE473
Datapath Connections for MIPS add
add R1, R2, R3
P
C address Inst.
R1
R2
R3
add
ReadRegister#1
ReadRegister#2
WriteRegister
Data
Port#1
Port#2
ALU
CLK
![Page 6: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/6.jpg)
6 ECE473
Datapath Connections for MIPS add
add R1, R2, R3
P
C address Inst.
R1
R2
R3
add
ReadRegister#1
ReadRegister#2
WriteRegister
Data
Port#1
Port#2
ALU
CLK
Interconnections
![Page 7: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/7.jpg)
7 ECE473
Critical Path for MIPS add
add R1, R2, R3
P
C address Inst.
R1
R2
R3
add
ReadRegister#1
ReadRegister#2
WriteRegister
Data
Port#1
Port#2
ALU
CLK
Interconnections
Critical path
![Page 8: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/8.jpg)
8 ECE473
Datapath Components for MIPS lw/sw
lw R1, -100(R2)
sw R1, -100(R2)
P
C address Inst.
R1
R2
-100
lw/sw
ReadRegister#1
ReadRegister#2
WriteRegister
Data
Port#1
Port#2
ALU
REGISTERS
ROM
Instruction
Memory
Data Memory
RAM
DataIn
Address
DataOut
16
SIGN-EXTEND 16 32
![Page 9: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/9.jpg)
9 ECE473
Connections for lw
lw R1, -100(R2)
P
C address Inst.
R1
R2
-100
lw
ReadRegister#1
ReadRegister#2
WriteRegister
Data
Port#1
Port#2
ALU
REGISTERS
ROM
Instruction
Memory
Data Memory
RAM
DataIn
Address
DataOut
16
SIGN-EXTEND 16 32
![Page 10: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/10.jpg)
10 ECE473
Critical Path for lw
lw R1, -100(R2)
P
C address Inst.
R1 (rt)
R2 (rs)
-100
lw
ReadRegister#1
ReadRegister#2
WriteRegister
Data
Port#1
Port#2
ALU
REGISTERS
ROM
Instruction
Memory
Data Memory
RAM
DataIn
Address
DataOut
16 (Imm)
SIGN-EXTEND 16 32
![Page 11: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/11.jpg)
11 ECE473
Connections for sw
sw R1, -100(R2)
P
C address Inst.
R1
R2
-100
sw
ReadRegister#1
ReadRegister#2
WriteRegister
Data
Port#1
Port#2
ALU
REGISTERS
ROM
Instruction
Memory
Data Memory
RAM
DataIn
Address
DataOut
16
SIGN-EXTEND 16 32
![Page 12: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/12.jpg)
12 ECE473
Critical Path for sw
sw R1, -100(R2)
P
C address Inst.
R1
R2
-100
sw
ReadRegister#1
ReadRegister#2
WriteRegister
Data
Port#1
Port#2
ALU
REGISTERS
ROM
Instruction
Memory
Data Memory
RAM
DataIn
Address
DataOut
16
SIGN-EXTEND 16 32
![Page 13: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/13.jpg)
13 ECE473
Datapath Connections for MIPS add and lw
add R1, R2, R3
P
C address Inst.
R1 R2 R3 add
ReadRegister#1
ReadRegister#2
WriteRegister Data
Port#1
Port#2 ALU
CLK
lw R1, -100(R2)
P
C address Inst. R1
R2
-100
lw
ReadRegister#1
ReadRegister#2
WriteRegister
Data Port#1
Port#2
ALU
Instruction
Memory
Data Memory
RAM DataIn
Addres
s DataOut
16
SIGN-EXTEND 16 32
![Page 14: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/14.jpg)
14 ECE473
Datapath Connections for MIPS add and lw
P
C address Inst. R1
R2
-100
lw
ReadRegister#1
ReadRegister#2
WriteRegister
Data Port#1
Port#2
ALU
Instruction
Memory
Data Memory
RAM DataIn
Addres
s DataOut
16
SIGN-EXTEND 16 32
NEED MUX
![Page 15: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/15.jpg)
15 ECE473
Combined Datapath: R-Type and Load/Store Instructions
5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
32
M
U
X
MUXALUSrc
MemtoReg
![Page 16: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/16.jpg)
16 ECE473
Combined Datapath: Executing and R-Type Instruction
add rd,rs,rt 5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
32
M
U
X
MUXALUSrc
MemtoReg
![Page 17: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/17.jpg)
17 ECE473
Combined Datapath: Executing a load instruction
lw rt,offset(rs) 5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
32
M
U
X
MUXALUSrc
MemtoReg
![Page 18: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/18.jpg)
18 ECE473
Combined Datapath: Executing a store instruction
sw rt,offset(rs) 5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
32
M
U
X
MUXALUSrc
MemtoReg
![Page 19: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/19.jpg)
19 ECE473
Datapath Components for MIPS beq
beq $R1, $R2, -100
if $R1==$R2 then PC = PC+4+4*(-100) else PC = PC+4
ReadRegister#1
ReadRegister#2
WriteRegister
Data
Port#1
Port#2
REGISTERS Instruction
Memory
P
C address Inst.
R1
R2
-100
beq
ROM 16
SIGN-EXTEND 16 32
ALU
zero
ADD SHIFT LEFT 2
32 32
![Page 20: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/20.jpg)
20 ECE473
Datapath Connections for MIPS beq
beq $R1, $R2, -100
if $R1==$R2 then PC = PC+4+4*(-100) else PC = PC+4
ReadRegister#1
ReadRegister#2
WriteRegister
Data
Port#1
Port#2
REGISTERS Instruction
Memory
P
C address Inst.
R1
R2
-100
beq
ROM 16
SIGN-EXTEND 16 32
ALU
zero
ADD SHIFT LEFT 2 32 32
PC+4
To branch
Control
![Page 21: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/21.jpg)
21 ECE473
Complete Single-Cycle Datapath
5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
32
M
U
X
ALUSrc
MemtoReg
ADD
<<2
RD
InstructionMemory
ADDR
PC
4
ADD
ADD
M
U
X
M
U
X
PCSrc
![Page 22: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/22.jpg)
22 ECE473
5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
32
M
U
X
ALUSrc
MemtoReg
ADD
<<2
RD
InstructionMemory
ADDR
PC
4
ADD
ADD
M
U
X
M
U
X
PCSrc
Complete Datapath Executing add
add rd, rs, rt
![Page 23: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/23.jpg)
23 ECE473
5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
32
M
U
X
ALUSrc
MemtoReg
ADD
<<2
RD
InstructionMemory
ADDR
PC
4
ADD
ADD
M
U
X
M
U
X
PCSrc
Complete Datapath Executing load
lw rt,offset(rs)
![Page 24: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/24.jpg)
24 ECE473
5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
32
M
U
X
ALUSrc
MemtoReg
ADD
<<2
RD
InstructionMemory
ADDR
PC
4
ADD
ADD
M
U
X
M
U
X
PCSrc
Complete Datapath Executing store
sw rt,offset(rs)
![Page 25: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/25.jpg)
25 ECE473
5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
32
M
U
X
ALUSrc
MemtoReg
ADD
<<2
RD
InstructionMemory
ADDR
PC
4
ADD
ADD
M
U
X
M
U
X
PCSrc
Complete Datapath Executing branch
beq r1,r2,offset
![Page 26: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/26.jpg)
26 ECE473
Refining the Complete Datapath
• Depending on the instruction, register file input WN is fed by different fields of the instruction – R-Type Instructions: rd field (bits 15:11)
– Load Instructin: rt field (bits 21:16)
• Result: need an additional multiplexer on WN input
op rs rt offset
6 bits 5 bits 5 bits 16 bits
op rs rt rd funct shamt
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R-Format
I-Format
![Page 27: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/27.jpg)
27 ECE473
Complete Datapath (Refined)
5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
Mem Read
DataMemory
ADDR
Mem Write
5
Instruction I32
M
U
X
ALUSrc
Mem toReg
ADD
<<2
RD
InstructionMemory
ADDR
PC
4
ADD
ADD
M
U
X
M
U
X
PCSrc
MUX RegDst
5
rd
I[15:11]
rt
I[21:16]
rs
I[25:21]
immediate/
offset
I[15:0]
![Page 28: ECE473 Computer Organization and Architecturearch.eece.maine.edu/ece473/images/b/b9/Lec06_Datapath_Combined.pdfECE473 Computer Architecture and Organization ... •Want to build a](https://reader031.fdocuments.net/reader031/viewer/2022021820/5ae181d17f8b9ad47c8be378/html5/thumbnails/28.jpg)
28 ECE473
Complete Single-Cycle Datapath
Control signals
shown in blue
5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
Mem Read
DataMemory
ADDR
Mem Write
5
Instruction
I32
M
U
X
ALUSrc
Mem toReg
ADD
<<2
RD
InstructionMemory
ADDR
PC
4
ADD
ADD
M
U
X
M
U
X
PCSrc
MUX RegDst
5
rd
I[15:11]
rt
I[20:16]
rs
I[25:21]
immediate/
offset
I[15:0]
0
1
0
1
1
0
10