NAME __Solutions _______________________

FINAL EXAM

(Closed book)

ECE 442 Fall 2009

2 hours

Instructions: Write your name where indicated. This examination consists of 4 problems. You are allowed to use a calculator and 2 formula sheets (81/2 by 11 in). Show all work.

Problem 1

(30 pts)

Problem 2

(20 pts)

Problem 3

(20 pts)

Problem 4

(30 pts)

Total

(100 pts)

- 2 -

Formula Sheet

DIODE

/( 1)D TV VD SI I e= , where 26 mVBT k TV q= = BIPOLAR (NPN forward active IB>0, VCE>VCE,sat)

/ /1BE T BE TV V V VCEC S SA

VI I e I eV

= + where 26 mVBT

k TVq

= =

1 CEC E B BA

VI I I IV

= = + 1 = +

Small Signal Characteristics:

( ); ; 1 ; ; AC Tm m e e oT E C

VI Vg g r r r r rV I I

= = = + = = MOSFET (long channel model equations)

Define VDSP = VGS-VT, where VT is the threshold voltage NMOS PMOS

Triode Region (Linear) & ,GS T DS DSPV V V V> <

2

( )2

= DS

D n ox GS T DSVWI C V V V

L

Active Region (Saturation)

& ,GS T DS DSPV V V V> [ ]2( ) 1

2 = + n oxD GS T DSCWI V V VL

Body Effect ( )2 2T To SB F FV V V = + +

, 0GS T DV V I =

Triode Region (Linear) & ,GS T DS DSPV V V V< >

2

( )2

= DS

D p ox GS T DSVWI C V V V

L

Active Region (Saturation)

& ,GS T DS DSPV V V V< [ ]2( ) 1

2 = p oxD GS T DSCWI V V VL

Body Effect ( )2 2T To SB F FV V V = +

, 0GS T DV V I =

Small Signal Characteristics (NMOS): 12 ; Am n ox D ds

D D

VWg C I rL I I

= = =

- 3 -

1. For the circuit shown, assume that =100, VBE = 0.6 V, fT = 107 Hz and C =10 pF at the bias point used.

Determine the following quantities

(a) The DC base voltage VB

2

1 2

18 8 2.0562 8

CCB

V RV VR R

= = =+ +

VB = ____2.05 V

(b) The DC collector current IC

2.05 0.6 1.45E B BEV V V V= = = 1.45 2.910.5

EE

E

VV mAR

= = =

100 /1011

= =+

2.88 100 /101 2.88C EI I mA= = = IC = ____2.88 mA____

- 4 -

(c) The midband voltage gain

2.88 110.97 /0.026

Cm

T

Ig mA VV

= = =

/ 100 /110.97 0.901mr g k = = = 100 1 66.6

0.901 0.6C

MBg

RAr R

= = =+ +

AMB = ____66.6___

(d) The upper 3-dB frequency 3

117

110.97 10 10 17562 10

m m

T T

g gC C C C pF

+

+ = = = =

(1 ) 1756 10(1 110.97) 2875.7eq m CC C C g R pF = + + = + + = (0.901)(0.6) 0.3600.901 0.6g

R R r k= = = +&

3 3 12

1 1 153.62 2 0.360 10 2875.7 10dB eq

f kHzRC + = = =

f3dB = ___153.6 kHz__

More accurate approach:

( ) ( ){ }i3dB ' 'i m C C i1 R gf 2 R C C 1 g R C R 1 R g += + + + +

{ }3 3

3dB 3 12 12 12 3 3 3

1 (0.6 10 1.1098 10 )f2 0.6 10 1756 10 2875 10 10 10 1 10 1 (0.6 10 1.1098 10 )

+

+ + + + = + + +

( )9

3dB1.6658 10f 95.18 kHz

2 2778.6 6.658+= =+

f3dB = ___95.18 kHz__

- 5 -

2. Using an ideal op amp, design an inverting circuit for which the voltage gain is -5 V/V and the total value of resistance used is 120 k. (Draw circuit schematic and show component values.)

For inverting amplifier, closed-loop gain is: 1

FRGR

=

Thus, we must have:

1

5FRR

= and 1 120FR R+ =

1 1 1 15 120 6 120 20R R R R k+ = = = 15 100F FR R R k= =

R1 = ____20 k___ RF = ____100 k___

- 6 -

3. The current source shown in the figure utilizes a pair of matched pnp transistors having IS=10-15 A, = 50, and |VA| = 50V. It is required to design the circuit to provide an output current Io = 1 mA at Vo = 2 V.

(a) What values of IREF and R are needed?

IREF = Io = 1 mA

VREF =5-0.7=4.3

R = 4.3/1=4.3 k

IREF = __1 mA _________

R = __4.3 k ________

- 7 -

(b) If this current source is to be used as an active load for a common-emitter amplifier, what is the equivalent load impedance presented by the active load.

| | 50 501

AL o

C

VR r kI

= = = =

RL = ___50 k___________

- 8 -

4. In the differential amplifier shown, Q1 and Q2 form the differential pair while the current source transistors Q4 and Q5 form the active loads for Q1 and Q2 respectively. The dc bias circuit that establishes an appropriate dc voltage at the drains of Q1 and Q2 is not shown. The following specifications are desired: differential gain Ad = 100 V/V, IREF = 100 A, the dc voltage at the gates of Q6 and Q3 is +1.5V; the dc voltage at the gates of Q7, Q4 and Q5 is 1.5V.

The technology available is specified as follows: nCox=3pCox = 100A/V2; Vtn=|Vtp| = 0.7 V, VAn=|VAp| = 20V. Specify the required value of R and the W/L ratios for all transistors. Also, specify ID and VGS at which each transistor is operating. For dc bias calculations, you may neglect channel-length modulation. Fill in the entries in the table provided to show your results.

- 9 -

1.5 ( 1.5) 3100 300.1REF

VI A R kR mA

= = = =

R = ____30 k_____

1 2 4 5 61

20 40050 10

= = = = = = Ap

o o o o

Vr r r r k

I

Drain currents are determined by symmetry and inspection

VGS values are also determined by inspection for all transistors except Q1 and Q2. To determine VGS for Q1 and Q2, we do the following: the equivalent load resistance will consist of ro1 in parallel with ro4 for Q1 and ro2 in parallel with ro5 for Q5. Since the ros are equal, this corresponds to ro/2.

We have

2 2 100 0.5 /2 400

= = = =o d

m d mo

r Ag A g mA Vr k

2 2 2 0.05 0.20.5

= = = =D Dm ovov m

I Ig VV g

V

Take polarity into account for PMOS

1,2 0.2 0.9= = GS TV V V

To find W/L ratios, use: 2 22( )

2 ( )D

D ox GS Tox GS T

IW WI C V VL L C V V

= =

taking into account PMOS and NMOS devices separately

CMOS OP-AMP DESIGN TABLE

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Units

Cox 33.33 33.33 33.33 100 100 33.33 100 A/V2 ID 50 50 100 50 50 100 100 A VGS -0.9 -0.9 -1 +1 +1 -1 +1 V

W/L 75 75 66.67 11.11 11.11 66.67 22.22