ECE425: Introduction to VLSI System Design
Transcript of ECE425: Introduction to VLSI System Design
ECE425: Introduction to VLSI System Design
Machine Problems: An overview
Zigang Xiao Aug 29, 2014
MP Overview • Four problems
– Cell based circuit design – From cell to blocks, logic to layout – Simulation, verification – Automatic Place and route
• 50% towards your final grade – MP0 2.5% due Sep 5th 2014 – MP1 10% due Sep 29th 2014 – MP2 25%
• CP1 due Oct 27th 2014 • CP2 due Nov 17th 2014
– MP3 12.5% due Dec 8th 2014
Late Policy • Each individual MP is allowed to be late for
up to 3 days with penalties • 1 day: 90% • 2 days: 70% • 3 days: 50% • > 3 days: 0%
• Note: no late submission for Homework!
Submission • Printouts as specified in MP document • Submit to ECEB drop box (available next
week)
• Late submission: – should be submitted directly to our office in
Rm 408 CSL (not to drop box) – an email should be sent to the TAs as a
record
Where to Get Help • TAs:
– Zigang Xiao (zxiao2) – Haitong Tian (htian3) – Daifeng Guo (guo31)
• Office hours: posted in piazza • Post resources, questions to Piazza • MP tutorials
MP0 • Cadence Virtuoso Walk Through • Composer: schematic design • NC-verilog: logic verification • Layout Editor: layout design & verification • Follow the manual, very verbose
Schematic
Layout
MP1 • 8 Bit Adder • Start to build your cell library
– INV, NAND2, NOR2, XOR2 etc – Schematic usable in next MP
• Half-adder • Full-adder • 8 bit adder
MP1
MP1
MP2 • AMD Am2901 • 4-bit bitslice datapath unit • Two checkpoints
– MP2.1: Logic design – MP2.2: Layout design
• Bonus for top 3 designs with smallest layout area (not violating design rules)
• The document is long but complete, read through
Top Level View
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Control Block
Datapath MP2 part 1: Schematic, simulation
MP2 part 2: Layout, LVS
MP3: Synthesis, place & route (Done automatically with CAD tools)
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Datapath
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2
Register
RAM
ALU
A OP
CODE
B
MP3 • Follow up of MP2 • Automated EDA tools to synthesize
controller • Logic Synthesis: compile your HDL • Automatic Place & Route:
– The synthesized network (control block) – Integrate Control and Datapath
Top Level View
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Control Block
Datapath MP2 part 1: Schematic, simulation
MP2 part 2: Layout, LVS
MP3: Synthesis, place & route. Automatically synthesized (full manual design in MP2)
……
Advices • Search/Ask question in Piazza! • Get familiar with UNIX commands
– Past students overwrote their works by accidental unzip/rm
• Always verify cells – Simulation, DRC, LVS – Potentially save debugging time (from
backtracing)
• Hierarchical design – Easier to manage and debug