ECE-L304 Lecture 3

ECE-L304 LECTURE 3

Review of Step 2

Introduction to Step 3

Tech Notes

Step 2 Review

ADC and display are assembled

Table of dc tests

Observation of performance on logic analyzer

Comparison of predicted and measured timing

Report writing completed

Please put all authors last names in filename for submission

ECE-L304 Lecture 3 2

Step 2 Review

Step 3 can not begin until the Step 2

circuit is complete and operational

Don’t continue if your TA has not checked

your ADC circuit hardware


Step 2 Deliverables

A functioning circuit

Graded on output, neatness

Your circuit must be checked out by your TA

Report

See details in lab instructions


Step by Step

Step 1 Review of ADC and DAC

Step 2 Building the ADC Circuit

Step 3 Build the DAC Circuit

Step 4 Introduce Static RAM

Step 5 Build the On-Board Clock

Step 6 Introduce Control Logic

Step 7 Final Changes


This Week

Step 3 Prelab

Read the DAC0808 datasheet

Review Figure 1 on datasheet

Step 3 Lab

Add a DAC to the data bus

Observe DC input and DC output


Figure 1 DAC 0808


Step 3 Lab - Add the DAC


ADC RAM DAC

Control

8 8

Data Bus

Step 3 LabE

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ecture 3

9

8-pin header

Data Bus Test Port

Resistor

Array

LED

Array

Timing & Filter

Components

Self-ClockedADC

DAC

External Components

A Digital to Analog Convertor DAC0808

An external reference voltage is used in

conjunction with resistor R14 to establish a

reference current.

Full scale current is adjusted by setting all

digital inputs high and adjusting VREF and/or R14

until IOUT = IFS.

The DAC output voltage is generated across RL

at pin 4, where the total current (Io) flows into

pin 4. Hence, the DAC output is Vo = - RL Io

The resistor tied to pin 15 is to temperature

compensate the bias current and may not be

necessary for all applications.

𝐼0 =𝑉𝑅𝐸𝐹𝑅14

𝐴12+𝐴24+𝐴38+𝐴416

+𝐴532

+𝐴664

+𝐴7128

+𝐴8256

DAC Circuit - As Given

ECE-L304 Lecture 311

𝑉0 = 𝑉𝑟𝑒𝑓𝐴12+𝐴24+𝐴38+ − − +

𝐴8256

DAC Circuit - As Modified


Our Modification

R14, R15 and

RLOAD = 5 k

VREF = Vcc = 5.12 V

DAC CircuitE

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ecture 3

13

DAC Circuit

Two external resistors, load resistor

Mounted to board

One external capacitor

Mounted to board

Negative 15 V power supply

Reference voltage

Connect Vref to Vcc


-15 V Vee Supply


+5.12V +15V

Vcc Vee

-15V Vee Supply


CH 1 CH 2CH Set to

1 +5 V

2 +15V

-15V

GND

+5V

DAC Circuit


𝐼0 = 𝐾𝐴12+𝐴24+𝐴38+𝐴416

+𝐴532

+𝐴664

+𝐴7128

+𝐴8256

Where K=𝑉𝑅𝐸𝐹

𝑅14

𝑉𝑜𝑢𝑡 = −𝐼0𝑅𝐿𝑜𝑎𝑑

𝑉𝑜𝑢𝑡 = −𝑅𝐿𝑜𝑎𝑑𝑅14

𝑉𝑅𝐸𝐹𝐴12+𝐴24+−−−+

𝐴7128

+𝐴8256

Step 3 TestingPurpose

Test functionality of DAC design

How?

As was done in the simulation in Step 1, we will compare

the DAC output to the analog input

Input a low frequency 0 - 5 V ramp to the ADC, view the ADC

input and DAC output on the scope

Use scope to measure and record the quantization step

duration of the DAC output. Compare to the INTR_

interrupt period measured in Step 2

Use the scope to test the frequency limits of the circuit

ECE-L304 Lecture 318

Time and Voltage Quantization


time

Vin

(V

)Vout

(V)

Ideal Case

Time and Voltage Quantization


time

Vin

(V

)Vout

(V)

Real Case

Voltage

resolution

Time resolution

Frequency Limit

Theory says that we must capture at least two samples per cycle of

a periodic input waveform

𝑓𝑠≥ 2𝐵 → 𝑇𝑠 ≤

𝑇𝑚

2where 𝑇𝑚 =

1

𝐵

where fs is the sampling frequency and B is bandwidth of the sampled

signal

In self-clocked mode, the ADC capture frequency is set by it’s

internal clock

As the input frequency increases, you will reach a point where

ADC no longer captures 2 samples per cycle. Find this frequency.


Under-sampling and AliasingThe higher the frequency content of the signal, the higher the sampling rate

should be to preserve the full information in the signal. It is necessary to

sample at least at twice the maximum frequency of the signal.

The Sampling Theorem states that a signal can be exactly reproduced if it is

sampled at a frequency Fs, where Fs is greater than twice the maximum

frequency in the signal, which is known as the Nyquist rate..

If the signal is sampled at a frequency that is lower that the Nyquist rate,

when converted back into a continuous time signal, it will exhibit a

phenomenon called aliasing.

Aliasing is the presence of unwanted components in the reconstructed

signal which were not present when the original signal was sampled.

The process of aliasing describes the phenomenon in which components of

the signal at high frequencies are mistaken for components at lower

frequencies.


𝑓

F(w)

𝑓𝑚𝑎𝑥−𝑓𝑚𝑎𝑥f(t)

t

Ts

Ts

Xsampled(f)), 𝑓𝑠 > 2𝑓𝑚𝑎𝑥

𝑓−𝑓𝑠 2𝑓𝑠𝑓𝑠−2𝑓𝑠 0 𝑓𝑚𝑎𝑥−𝑓𝑚𝑎𝑥_

𝑓−𝑓𝑠 2𝑓𝑠𝑓𝑠−2𝑓𝑠 0 𝑓𝑚𝑎𝑥𝑓𝑚𝑎𝑥

Xsampled(f)), 𝑓𝑠 < 2𝑓𝑚𝑎𝑥

Original signal and Sampled signal Spectrum of original signal

Aliasing Example: Single Tone Signal


𝑓

Xsampled(f)), 𝑓𝑠 > 2𝑓𝑚𝑎𝑥

−𝑓𝑠 2𝑓𝑠𝑓𝑠−2𝑓𝑠 0 𝑓𝑚𝑎𝑥−𝑓𝑚𝑎𝑥

𝑓

Xsampled(f)), 𝑓𝑠 < 2𝑓𝑚𝑎𝑥

−𝑓𝑠

2𝑓𝑠

𝑓𝑠

−2𝑓𝑠 0 𝑓𝑚𝑎𝑥−𝑓𝑚𝑎𝑥

Aliasing ExampleSampling frequency is less than

the Nyquist criteria, less than 2

samples per cycles

Sampling frequency is higher

than the Nyquist criteria, more

than 2 samples per cycles

Two different sine waves that fit the same set of samples


2𝑇𝑠

𝑇m

𝑇𝑠 =sampling interval

𝑇𝑚 =message period

To avoid aliasing 𝑓𝑠 ≥ 2𝑓𝑚 → 2𝑇𝑠 ≤ 𝑇

Step 3 Deliverables

Have functionality and construction

quality checked by your TA

Answer questions in the Step 3 lab

instructions

Comment on your observations


Tech Notes

Remember that we replaced the opamp

in figure 1 of the DAC0808 datasheet

with a 5 k resistor. You do not need to

use an opamp in this lab.

You must connect VREF and VEE to be able

to use the DAC.


ECE-L304 Lecture 3

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