1

ECE 667 - Synthesis & Verification - Lecture 0

ECE 697B (667)ECE 697B (667)Spring 2006Spring 2006

Synthesis and Verificationof Digital Circuits

VLSI Design StylesVLSI Design Styles

ECE 667 - Synthesis & Verification - Lecture 0 2

Implementation ChoicesImplementation Choices

Custom

Standard CellsCompiled Cells Macro Cells

Cell-based

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Semicustom

Digital Circuit Implementation Approaches

ECE 667 - Synthesis & Verification - Lecture 0 3

Cell-based Design (or standard cells)Cell-based Design (or standard cells)

Routing channel requirements arereduced by presenceof more interconnectlayers

Functionalmodule(RAM,multiplier,…)

Routingchannel

Logic cellFeedthrough cellR

ow

s o

f ce

lls

ECE 667 - Synthesis & Verification - Lecture 0 4

Standard Cell Layout Methodology – 1980sStandard Cell Layout Methodology – 1980s

signals

Routingchannel

VDD

GND

module example(clk, a, b, c, d, f, g, h)input clk, a, b, c, d, e, f;output g, h; reg g, h;

always @(posedge clk) beging = a | b;if (d) begin

if (c) h = a&~h;else h = b;if (f) g = c; else a^b;

end elseif (c) h = 1; else h ^b;

endendmodule

Specification

d

abe

fc

0h

g

clk

Logic Extraction

Synthesis FlowSynthesis FlowSynthesis FlowSynthesis Flowa multi-stage process

Technology-Independent Optimization

f

g0

h1

a

c

e

g1

h3

h5

H

Gb

d

Technology-Dependent Mapping

f

d

beac

clk

hH

G g

ECE 667 - Synthesis & Verification - Lecture 0 7

Intel Pentium (IV) microprocessorIntel Pentium (IV) microprocessor

ECE 667 - Synthesis & Verification - Lecture 0 8

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Array based designArray based design

ECE 667 - Synthesis & Verification - Lecture 0 9

Gate Array — Sea-of-gatesGate Array — Sea-of-gates

rows of

cells

routing channel

uncommitted

VDD

GND

polysilicon

metal

possiblecontact

In1 In2 In3 In4

Out

UncommitedCell

CommittedCell(4-input NOR)

ECE 667 - Synthesis & Verification - Lecture 0 10

Sea-of-gate Primitive CellsSea-of-gate Primitive Cells

NMOS

PMOS

Oxide-isolation

PMOS

NMOS

NMOS

Using oxide-isolation Using gate-isolation

ECE 667 - Synthesis & Verification - Lecture 0 11

Sea-of-gatesSea-of-gates

Random Logic

MemorySubsystem

LSI Logic LEA300K(0.6 m CMOS)

Courtesy LSI Logic

ECE 667 - Synthesis & Verification - Lecture 0 12

2-input mux 2-input mux as programmable logic blockas programmable logic block

FA 0

B

S

1

Configuration

A B S F=

0 0 0 00 X 1 X0 Y 1 Y0 Y X XYX 0 YY 0 XY 1 X X 1 Y1 0 X1 0 Y1 1 1 1

XYXY

XY

ECE 667 - Synthesis & Verification - Lecture 0 13

Logic Cell of Actel Fuse-Based FPGALogic Cell of Actel Fuse-Based FPGA

A

B

SA Y

1

C

D

SB

1

S0S1

1

ECE 667 - Synthesis & Verification - Lecture 0 14

Look-up Table Based Logic CellLook-up Table Based Logic Cell

Out

ln1 ln2

Me

mory In Out

00 00

01 1

10 1

11 0

ECE 667 - Synthesis & Verification - Lecture 0 15

LUT-Based Logic CellLUT-Based Logic Cell

Courtesy Xilinx

D4

C1....C4

xxxxxx

D3

D2

D1

F4

F3

F2

F1

Logicfunction

ofxxx

Logicfunction

ofxxx

Logicfunction

ofxxx

xx

xx

4

xxxxxx

xxxxxxxx

xxx

xxxx xxxx xxxx

HP

Bitscontrol

Bitscontrol

Multiplexer Controlledby Configuration Program

x

xx

x

xx

xxx xx

xxxx

x

xxxxxx

xx

x

xx

xxx

xx

Xilinx 4000 Series

Figure must be updated

ECE 667 - Synthesis & Verification - Lecture 0 16

Array-Based Programmable WiringArray-Based Programmable Wiring

Input/output pinProgrammed interconnection

InterconnectPoint

Horizontaltracks

Vertical tracks

Cell

M

ECE 667 - Synthesis & Verification - Lecture 0 17

Mesh-based Interconnect NetworkMesh-based Interconnect Network

Switch Box

Connect Box

InterconnectPoint

Courtesy Dehon and Wawrzyniek

ECE 667 - Synthesis & Verification - Lecture 0 18

Transistor Implementation of MeshTransistor Implementation of Mesh

Courtesy Dehon and Wawrzyniek

ECE 667 - Synthesis & Verification - Lecture 0 19

Altera MAXAltera MAX

From Smith97

ECE 667 - Synthesis & Verification - Lecture 0 20

Altera MAX Interconnect ArchitectureAltera MAX Interconnect Architecture

LAB2

PIA

LAB1

LAB6

tPIA

tPIA

row channelcolumn channel

LAB

Courtesy Altera

Array-based(MAX 3000-7000)

Mesh-based(MAX 9000)