ECE 448: Spring 13Lab 3

Sequential Logic for Synthesis

Simulation using ModelSim

Part 1: Introduction to Lab 3

• Top-level circuit

• LFSR

• MISR

• Debouncer

• Edge Detector

Part 2: Hands-on Session:

Simulation Using ModelSim

Part 3: Demos of Lab 2

Agenda for today

ECE 448 – FPGA and ASIC Design with VHDL

Part 1

Introduction to Lab 3

Top-Level Circuit

rstclk

enCNTRUP

rstclk

enMISR

ld

rst clk

enLFSR

X”00” 8

8

8

IVBloadB

rst

OR

loadB

nexti

10cnz

ld

rst clk

enLFSR

X”00” 8

8

8

IVAloadA

rst

OR

loadA

10cnz

clkclk

LAB2

A B

X Y

sel

En ‘0’

8

clkrst

8

YSGN

nexti

nextrst

clk

enMISR

8

clkrst

8

XSGN

next

10k

k9..8

2

k7..0

8

≠ 0

cnz

= X”3FF”10

done

rstclk

next

OR

AND not donenext

step run

AND

cnz

Used to enterIVA, IVB

Used to generateloadA, loadB,

step, run

Used to displayXSGN, YSGN

Source of Inputs & Display of Outputs (to be experimentally tested in Lab 4)

Connection of Buttons to the Pins of FPGA

RED = Rising Edge Detector

RESET

BTNL

BTNR

BTNU

BTNS

Debouncer RED loadA

Debouncer RED loadB

Debouncer RED step

rst

Debouncer RED

runD Q‘1’

en

rst

clk

rst

clkrst

clk

rst

clkrst

clk

rst

clk

rst

clk

rst

clk

rst

clk

Generation of Inputs Using Buttons

Pseudo-Random Number Generators

Implemented Using LFSRs

PRNG• Generates a sequence of numbers that

approximates the properties of random numbers.

• The sequence is fully deterministic, i.e., it can be repeated based on an initial state of PRNG.• The period of the sequence may be made very

large (typically, 2n-1, where n is an internal state size)

PRNG

• Random Numbers are often important– Testing of VLSI circuits– Cryptography– Monte Carlo simulations– Noise addition– Bit error detection, and many other applications

Linear Feedback Shift Register (LFSR)

L, C(D)

Connection polynomial, C(D)

C(D) = 1 + c1D + c2D2 + . . . + cLDL

Length

Each stage = D flip-flop

Initial state[sL-1, sL-2, . . . , s1, s0]

LSFR recursion:

sj = c1sj-1 c2sj-2 . . . cL-1sj-(L-1) cLsj-L

for j L

Sj-1 Sj-2 Sj-(L-1) Sj-L

4, 1+D+D4

Connection polynomial, C(D)Length

Example of LFSR

c1=1 c2=0 c3=0 c4=1

C(D) = 1 + 1D + 0D2 + 0D3 + 1D4

LFSR State Sequence

s4 = c1s3 c2s2 c3s1 c4s0 = s3 s0

s4 s3 s2 s1 s0

8, 1+D4+D5+D6+D8

Connection polynomial, C(D)Length

LFSR to be used in Lab 3

Selected to make a period = 28-1 = 255

Initializing Serial Shift Register with Parallel Load

D(3)

D Q

Clock

Enable

SinD(2)

D Q

D(1)

D Q

D(0)

D Q

Q(0)Q(1)Q(2)Q(3)

Load

Hint: Use similar technique for initializing LFSR

Multiple Input Signature Register

MISR

AND

D Q

C7

en

rst

rst

en

D7

AND

D Q

C6

en

rst

rst

en

D6

AND

D Q

C5

en

rst

rst

en

D5

AND

D Q

C4

en

rst

rst

en

D4

AND

D Q

C3

en

rst

rst

en

D3

AND

D Q

C2

en

rst

rst

en

D2

AND

D Q

C1

en

rst

rst

en

D1

AND

D Q

C0

en

rst

rst

en

D0

MISR - Multiple Input Signature Register

Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

C=C7..C0 should be declared as a generic in VHDL code

For the purpose of testing set C=X”B8”

MISR is used to compress multiple inputs D to a single signature Q

Debouncer

Debouncer

Capacitance in the button and contacts “bouncing” causes spurs that cause false positives.

A debouncing circuit removes these spurs.This graphs shows releasing a button.

Debouncer

When the first change is detected, we ignore all subsequent changes for some period of time, preferably until all of the bouncing would have occurred. This is usually in the order of ms.

Debouncer

Debouncer

reset

input

clk

output

Debouncer

Rising Edge Detector

RED

Rising Edge Detector - RED

• Turn a step function into an impulse• Allows a step to run a circuit for only one clock

cycle

Rising Edge Detector

Rising Edge Detector

clk

input

output

input

clk

output

rising edge detector

reset

ECE 448 – FPGA and ASIC Design with VHDL

Part 2

Hands-on Session

Simulation Using ModelSim

Hands-on Session

on ModelSim using

four_bit_counter

based on JK flip-flops

ECE 448 – FPGA and ASIC Design with VHDL

Part 3

Lab 2 Demos