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Transcript of ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from...
![Page 1: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/1.jpg)
ECE 331 – Digital System Design
Counters
(Lecture #19)
The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
![Page 2: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/2.jpg)
Fall 2010 ECE 331 - Digital System Design 2
Material to be covered …
Chapter 12: Sections 3 – 6
![Page 3: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/3.jpg)
Fall 2010 ECE 331 - Digital System Design 3
A circuit that cycles through a fixed sequence of states is called a counter.
Counters
Shift register with inverted feedback
![Page 4: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/4.jpg)
Fall 2010 ECE 331 - Digital System Design 4
Binary Counters
000
001
010
011
100
101
110
111
3-bit Binary Counter
![Page 5: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/5.jpg)
Fall 2010 ECE 331 - Digital System Design 5
1. Create a state graph to count in the desired sequence.
2. Create a state table from the state graph created in (1). We need one flip-flop per bit.
3. Derive Karnaugh maps from the state table created in (2) and solve for the inputs to each flip-flop.
Binary Counters: Design
![Page 6: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/6.jpg)
Fall 2010 ECE 331 - Digital System Design 6
Binary Counter
Example: State Table (using T FF)
![Page 7: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/7.jpg)
Fall 2010 ECE 331 - Digital System Design 7
Binary Counter
Example: K-maps (for T FF)
![Page 8: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/8.jpg)
Fall 2010 ECE 331 - Digital System Design 8
Binary Counter
Example: Circuit Diagram (using T FF)
![Page 9: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/9.jpg)
Fall 2010 ECE 331 - Digital System Design 9
Binary Counter
Example: State Table (using D FF)
![Page 10: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/10.jpg)
Fall 2010 ECE 331 - Digital System Design 10
Binary Counter
Example: K-maps (for D FF)
![Page 11: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/11.jpg)
Fall 2010 ECE 331 - Digital System Design 11
Binary Counter
Example: Circuit Diagram (using D FF)
![Page 12: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/12.jpg)
Fall 2010 ECE 331 - Digital System Design 12
Binary Up-Down Counter
![Page 13: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/13.jpg)
Fall 2010 ECE 331 - Digital System Design 13
Binary Up-Down Counter
![Page 14: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/14.jpg)
Fall 2010 ECE 331 - Digital System Design 14
Loadable Counter with Enable
![Page 15: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/15.jpg)
Fall 2010 ECE 331 - Digital System Design 15
Loadable Counter with Enable
![Page 16: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/16.jpg)
Fall 2010 ECE 331 - Digital System Design 16
Counter Design (T FF)
Example: 000 → 100 → 111 → 010 → 011
![Page 17: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/17.jpg)
Fall 2010 ECE 331 - Digital System Design 17
Counter Design (T FF)
Example: 000 → 100 → 111 → 010 → 011
We could derive TC , TB , and TA directly from the state table, but it is often more convenient to plot next-state maps showing C+, B+, and A+ as functions of C, B, and A, and then derive TC , TB , and TA from these maps.
![Page 18: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/18.jpg)
Fall 2010 ECE 331 - Digital System Design 18
Counter Design (T FF)
Example: 000 → 100 → 111 → 010 → 011
![Page 19: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/19.jpg)
Fall 2010 ECE 331 - Digital System Design 19
Counter Design (T FF)
Example: 000 → 100 → 111 → 010 → 011
![Page 20: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/20.jpg)
Fall 2010 ECE 331 - Digital System Design 20
Counter Design (T FF)
Example: 000 → 100 → 111 → 010 → 011
![Page 21: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/21.jpg)
Fall 2010 ECE 331 - Digital System Design 21
Counter Design (T FF)
Example: 000 → 100 → 111 → 010 → 011
Although the original state table for the counter is not completely specified, the next states of states 001, 101, and 110 have been specified in the process of completing the circuit design
![Page 22: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/22.jpg)
Fall 2010 ECE 331 - Digital System Design 22
Counter Design (T FF)
Example: 000 → 100 → 111 → 010 → 011
Given the present state of a T flip-flop (Q) and the desired next state (Q+), the T input must be a 1 whenever a change in state is required. Thus, T = 1 whenever Q+ ≠ Q.
T = Q+ xor Q
Q+ Q T
0 0 0
0 1 1
1 0 1
1 1 0
Excitation Table
![Page 23: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/23.jpg)
Fall 2010 ECE 331 - Digital System Design 23
Counter Design (D FF)
Example: 000 → 100 → 111 → 010 → 011
![Page 24: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/24.jpg)
Fall 2010 ECE 331 - Digital System Design 24
Counter Design (D FF)
Example: 000 → 100 → 111 → 010 → 011
Characteristic Equation: Q+ = D
![Page 25: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/25.jpg)
Fall 2010 ECE 331 - Digital System Design 25
Counter Design (D FF)
Example: 000 → 100 → 111 → 010 → 011
![Page 26: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/26.jpg)
Fall 2010 ECE 331 - Digital System Design 26
Counter Design (D FF)
Example: 000 → 100 → 111 → 010 → 011
Although the original state table for the counter is not completely specified, the next states of states 001, 101, and 110 have been specified in the process of completing the circuit design
![Page 27: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/27.jpg)
Fall 2010 ECE 331 - Digital System Design 27
Counter Design (SR FF)
The procedures used to design a counter with S-R flip-flops are similar to the procedures for T flip-flops. However, instead of deriving an input equation for each D or T flip-flop, the S and R input equations must be derived for each S-R flip-flop.
Example: 000 → 100 → 111 → 010 → 011
![Page 28: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/28.jpg)
Fall 2010 ECE 331 - Digital System Design 28
Counter Design (SR FF)
Example: 000 → 100 → 111 → 010 → 011
Excitation Table
![Page 29: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/29.jpg)
Fall 2010 ECE 331 - Digital System Design 29
Counter Design (SR FF)
Example: 000 → 100 → 111 → 010 → 011
![Page 30: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/30.jpg)
Fall 2010 ECE 331 - Digital System Design 30
Counter Design (SR FF)
Example: 000 → 100 → 111 → 010 → 011
![Page 31: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/31.jpg)
Fall 2010 ECE 331 - Digital System Design 31
Counter Design (SR FF)
Example: 000 → 100 → 111 → 010 → 011
![Page 32: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/32.jpg)
Fall 2010 ECE 331 - Digital System Design 32
Counter Design (JK FF)
The procedures used to design a counter with JK flip-flops are similar to the procedures for T flip-flops. However, instead of deriving an input equation for each D or T flip-flop, the J and K input equations must be derived for each JK flip-flop.
Example: 000 → 100 → 111 → 010 → 011
![Page 33: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/33.jpg)
Fall 2010 ECE 331 - Digital System Design 33
Counter Design (JK FF)
Example: 000 → 100 → 111 → 010 → 011
Excitation Table
![Page 34: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/34.jpg)
Fall 2010 ECE 331 - Digital System Design 34
Counter Design (JK FF)
Example: 000 → 100 → 111 → 010 → 011
![Page 35: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/35.jpg)
Fall 2010 ECE 331 - Digital System Design 35
Counter Design (JK FF)
Example: 000 → 100 → 111 → 010 → 011
![Page 36: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/36.jpg)
Fall 2010 ECE 331 - Digital System Design 36
Counter Design (JK FF)
Example: 000 → 100 → 111 → 010 → 011
![Page 37: ECE 331 – Digital System Design Counters (Lecture #19) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,](https://reader036.fdocuments.net/reader036/viewer/2022062421/56649d825503460f94a671e2/html5/thumbnails/37.jpg)
Fall 2010 ECE 331 - Digital System Design 37
Questions?