ECE 265 – LECTURE 12 The Hardware Interface 8/22/2015 1 ECE265.

ECE 265 – LECTURE 12

The Hardware Interface

04/21/23

1ECE265

Joanne E. DeGroat, OSU

Lecture Overview

The Hardware Interface The pins Special Characteristics of the ports Software control of I/O Port lines

REF: Chapters 1,6, and 9 plus the 68HC11 reference manual.

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The hardware pins

The hardware pins Power and Ground Timing Interrupt Port A – I/O lines

(restricted in how used) Port B – Output extended

addressing Port C – Bidirectional I/O Port D – 5 bit port for

serial I/O Port E – 8 analog inputs

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Accessing I/O ports

This is a memory mapped architecture I/O done by writing to specific memory address

The ports Port A – At address $1000

Used for either General-purpose I/O but 3 are Inputs/4 outputs/1 bidirectional Output compare Input capture Pulse-accumulator applications

Linked with the internal timers on the 68HC11 (more later)

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Port A

The direction of Port A signal lines Note that 3 pins input 4 pins output 1 bidirectional

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The I/O ports

Port B – at address $1004 An output port – has the dual use of being used for

external addressing when the MPU is configured for extended memory mode.

Port C – at address $1003 All the lines are bidirectional The Port C data direction register DDRC is at $1007

This register configures the direction of the pins of the port.

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Port C configuration example

Note configuration

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The ports

Port D – only a 6 pin port - at $1008 Lines can be configured as general bidirectional I/O lines The lines can be used for both asynchronous and

synchronous serial communication. The port is set up to implement a SPI – Serial Parallel

Interface SPI interface – allows communication with a peripheral or

communication between processors in a multiple master MPU system.

The SPI interface is one where data is simultaneously transmitted and received. It has two data lines MISO and MOSI for this.

This is detailed in chapter 8 of the chip manual. Port D data direction register - $1009

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Port D

Port D can also be used to implement an asynchronous serial interface sometimes referred to as a UART system.

The system implements a full duplex UART-type system.

Multiple control registers are use and can be accessed. SCCR1 ($102C), SCCR2 ($102D), SCCR ($102E),

SCDR ($102F), BAUD ($102B), SPCR ($1028), SPSR ($1029), SPDR ($102A)

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The interrupt lines

Allow the processor to respond to an external device and ‘service’ the device.

This is done by asserting a signal on an input pin to the processor. When asserted the processor finishes the current instruction

and then starts execution of the interrupt service routine. When the service routine is completed, processing

continues from where it was interrupted. At the start of the routine the registers are placed on the

stack. The routine end with the RTI instruction which causes

restoration of the registers and return to the point at which execution was interrupted.

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Who is interrupting me?

Interrupts are generated either from the two external pins, IRQ and XIRQ or internally from various on chip devices.

The table lists the interrupt sources on the chip.

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Handling an interrupt

You need attention – your action? Raise your hand A peripheral or internal device needs attention

Generate an interrupt What needs to happen to service and interrupt

Instruction executed in response to an interrupt are called the interrupt service routine

Interrupt happen asynchronously The current instruction will complete execution All of the registers are saved on the stack

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Saving registers

When an interrupt occurs the current instruction completes and then the registers are stacked ORDER (remember stack is First In Last Out)

PCL – Program Counter Low PCH – Program Counter High IYL IYH IXL IXH ACCA ACCB CCR

After CCR is stacked, the I bit of the CCR is set If there is a pending XIRQ’ interrupt, the X bit is set

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Getting to service routine

After saving the state of the processor, the next step is getting to the code of the correct service routine.

Program counter is loaded with the 2 bytes in a interrupt vector table that is located at $FFxx addresses.

As these addresses are ROM, some systems set these up such that they have value $00xx. At these addresses is an unconditional jump, JMP op code 7E, to the service routine.

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Interrupt table

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Interrupt flow of execution

Interrupt occurs Current instruction in execution completes Registers are pushed onto stack New PC address is obtained from the 2 byte address for that

type interrupt Example – Real Time interrupt - $FF00 and $FF01 Example – Timer IC2F - $FFEC and $FFED IRQ pin – Maskable interrupt – $FFF2 and $FFF3 SWI instruction – Software Intr - $FFF6 and $FFF7

Execution continues from that address MEM(PC) IR PC + 1 PC

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Interrupt action continued

At that address, as shown previously, is a jump instruction for an unconditional jump to the interrupt service routine.

When service routine completes it does so with an RTI – Return from interrupt instruction. As shown in the instruction action for the RTI The registers are restored Then the PC is restored to continue execution of the

interrupted program

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Lecture summary

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Have looked at the ports of the 68HC11 Have looked at some specifics of 68HC11 interrupt

handling and interrupt handling in general.


Assignment

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HW 9 Get to a THR simulator Complete Project Step 1 Due Friday May 20

Work alone or in groups of 2. If working in a group of 2, be sure both names are clearly on the submission, but only 1 submits it to the drop box.

ECE 265 – LECTURE 12 The Hardware Interface 8/22/2015 1 ECE265.

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