Lecture 16:

Spring 2018

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More Single Cycle Microprocessor

ECE 2300Digital Logic & Computer Organization

Lecture 16: 2

Announcements• HW6 due tomorrow

• Prelim 2: Tues April 17, 7:30pm, 101 Phillips Hall – Coverage: Lectures 8~16– Inform instructor ASAP to resolve schedule conflict– An old exam will be released after spring break– Review sessions

• Friday April 13, 4:30-6:00pm, PHL 219• Monday April 16, 7:00-8:30pm, PHL 203

Lecture 16: 3

Control Word Example

R2 <= R0 + R1

R1 <= M[R2]

M[R2] <= R0

R3 <= R1 – 3

DR SA SB MB FS MD LD MWIMM

010 000 001 0 ADD 0 1 0x

001 010 xxx 1 ADD 1 1 00

xxx 010 000 1 ADD x 0 10

011 001 xxx 1 SUB 0 1 03

RF

LDSASBDRD_in

ALU RAM

DataA

DataB

V C Z N

Fm … F0

SE

IMMMB

M_address

Data_in

MW MD

01

01V

CNZ

DRSASB

IMMMBFSMDLD

MWCU

Lecture 16:

Unsigned Multiplication• Form each partial product by multiplying a

single digit of the multiplier by the multiplicand• Add shifted partial products to get result

4

101011x

multiplicand ( = 5)multiplier ( = 3)

partial products

result ( = 15)

101101

00001111

Lecture 16: 5

Revisit Sequential Multiplication• Multiply A2A1A0 by B2B1B0

A2A1A0 B2B1B0

(A2A1A0)ÎB0(A2A1A0) ÎB1

(A2A1A0) ÎB2P4P3 P2 P1 P0

Multiply A=101 by B=011: Determine the values of R1~R4 after each loop iteration

R2 R4R1 R3

R1 <= M[0] // load A from M[0]R2 <= M[1] // load B from M[1]R3 <= 0 // initialize R3 (P) = 0

(*) R4 <= R2 & 1 // R4 = lsb(B)R2 <= SRL(R2) // shift B rightif (R4) R3 <= R3+R1 // if lsb(B)=1, P=P+AR1 <= SLL(R1) // shift A leftif (R2) goto (*) // repeat until B=0

M[2] <= R3 // store P to M[2]

Lecture 16: 6

Instruction SequenceR1 <= M[0] R0 <= R0-R0 S1

R1 <= M[R0] S2R2 <= M[1] R2 <= M[R0 + 1] S3R3 <= 0 R3 <= R3-R3 S4R4 <= R2 & 1 R4 <= R2 & 1 S5R2 <= SRL(R2) R2 <= SRL(R2) S6R3 <= R3 + R1 R3 <= R3 + R1 S7R1 <= SLL(R1) R1 <= SLL(R1) S8M[2] <= R3 M[R0 + 2] <= R3 S9

R2 != 0R4 = 0

Lecture 16: 7

FSM for Sequential Multiplication

S1 R0 <= R0-R0S2 R1 <= M[R0]S3 R2 <= M[R0 + 1] S4 R3 <= R3-R3S5 R4 <= R2 & 1S6 R2 <= SRL(R2)S7 R3 <= R3 + R1S8 R1 <= SLL(R1) S9 M[R0 + 2] <= R3

DR SA SB MB FS MD LD MW000 000 000 0 SUB 0 1 0001 000 xxx 1 ADD 1 1 0010 000 xxx 1 ADD 1 1 0011 011 011 0 SUB 0 1 0100 010 xxx 1 AND 0 1 0

011 011 001 0 ADD 0 1 0001 001 xxx x SLL 0 1 0xxx 000 011 1 ADD x 0 1

010 010 xxx x SRL 0 1 0

IMMx01x1

xx2

x

0 1 2 3 4 5 6 7 8 9

R4=0

R2≠0Start=1

Start=0

R4=1R2=0

Lecture 16: 8

Programmable Control Unit• Datapath (RF, ALU, RAM, muxes) is flexible

• However, FSM-based multiplier control unit is “hardwired”– New operation sequence would require new state

machine

• Programmable Control Unit– Control words stored in RAM– State machine replaced by a Program Counter plus

branch operations– Flexible: Can run different sequences of control

words (programs)

Lecture 16: 9

Program Counter (PC)• Special register that points to the location (address) in

RAM of the next control word

• Updated every clock cycle

• Sequential execution (default behavior)– Control words read from sequential RAM locations– PC is increased by 1 after each control word read

• Branch operations– Special control flow operations– Condition code determines whether to branch or not – If so, next RAM address is PC + branch offset

Lecture 16: 10

R0 <= R0 – R0R1 <= M[R0]R2 <= M[R0+1]R3 <= R3 – R3

PC-Based Control Unit

DR SA SB MB FS MD LD MWIMM000 000 000 0 SUB 0 1 0x001 000 xxx 1 ADD 1 1 00010 000 xxx 1 ADD 1 1 01011 011 011 0 SUB 0 1 0x

1:2:3:4:

Adder1

PC

RF

LDSASBDRD_in

ALU RAM

DataA

DataB

V C Z N

Fm … F0

SE

IMMMB

M_address

Data_in

MW MD

01

01

DRSASB

IMMMBFSMDLD

MWRAM

PC+1

Lecture 16: 11

Instruction Sequence of Sequential MultiplicationR1 <= M[0] R0 <= R0-R0 S1

R1 <= M[R0] S2R2 <= M[1] R2 <= M[R0 + 1] S3R3 <= 0 R3 <= R3-R3 S4R4 <= R2 & 1 R4 <= R2 & 1 S5R2 <= SRL(R2) R2 <= SRL(R2) S6R3 <= R3 + R1 R3 <= R3 + R1 S7R1 <= SLL(R1) R1 <= SLL(R1) S8M[2] <= R3 M[R0 + 2] <= R3 S9

R2 != 0R4 = 0

Lecture 16:

Branch Operations• Used to jump to a different part of the program

• Consists of a condition and an offset

• Condition– Checks to see whether the result of the last

instruction met a specified criteria, such as • Zero (Z = 1), Negative (N = 1)

• Offset– How far ahead, or back, to jump within the program

if the condition is met

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Lecture 16: 13

PC

RF

LDSASBDRD_in

ALU RAM

DataA

DataB

V C Z N

Fm … F0

SE

IMMMB

M_address

Data_in

MW MD

01

01

Branch Operations

DRSASB

IMMMBFSMDLD

MWBS

OFFRAM

SE(OFF) AdderMP

01

+1

Lecture 16: !19

Branch Operations

PC

! RF !LD SA SB DR D_in

ALU RAM

DataA

DataB

V C Z N

Fm … F0

SE

IMMMB

M_address

Data_in

MW MD

0 1

0 1

MP

BS

0 1 Z Z’ N N’ C V

0 1 2 3 4 5 6 7

DR SA SB

IMM MB FS MD LD

MW BS

OFFROM

DR SA SB

IMM MB FS MD LD

MWROM

SE(OFF) AdderMP

0 1

+1+1

MP

BS

01ZZ’NN’CV

01234567

Lecture 16: 14

R2 <= SRL(R2)if (R4=0) goto 8R3 <= R3 + R1R1 <= SLL(R1)

PC

RF

LDSASBDRD_in

ALU RAM

DataA

DataB

V C Z NSE

IMMMB

M_address

Data_in

MW MD

01

01

5:

6:

7:

8:

010 010 xxx x SRL 0 1 0x 000 x

001 001 xxx x SLL 0 1 0x 000 x

011 011 001 0 ADD 0 1 0x 000 x

DR SA SB MB FS MD LD MWIMM BS OFF

Branch Operations

DRSASB

IMMMBFSMDLD

MWBS

OFFRAM

SE(OFF) AdderMP

01

+1 MP

BS

01ZZ’NN’CV

01234567

Fm … F0

Lecture 16: 15

R1 <= SLL(R1)if (R2≠0) goto 4M[R0+2] <= R3

8:9:

10:

DR SA SB MB FS MD LD MWIMM BS OFF

001 001 xxx x SLL 0 1 0x 000 x

010 000 011 1 ADD x 0 12 000 x

Branch Operations

xxx

PC

RF

LDSASBDRD_in

ALU RAM

DataA

DataB

V C Z NSE

IMMMB

M_address

Data_in

MW MD

01

01

DRSASB

IMMMBFSMDLD

MWBS

OFFRAM

SE(OFF) AdderMP

01

+1 MP

BS

01ZZ’NN’CV

01234567

Fm … F0

Lecture 16: 16

Programmable Multiplication0: R0 <= R0-R01: R1 <= M[R0]2: R2 <= M[R0 + 1] 3: R3 <= R3-R34: R4 <= R2 & 15: R2 <= SRL(R2)6: if (R4=0) goto 87: R3 <= R3 + R18: R1 <= SLL(R1)9: if (R2≠0) goto 410:M[R0+2] <= R3

DR SA SB MB FS MD LD MWIMM BS OFF

000 000 000 0 SUB 0 1 0x 000 x

001 000 xxx 1 ADD 1 1 00 000 x

010 000 xxx 1 ADD 1 1 01 000 x

011 011 011 0 SUB 0 1 0x 000 x

100 010 xxx 1 AND 0 1 01 000 x

010 010 xxx x SRL 0 1 0x 000 x

xxx 100 xxx 1 SUB x 0 00 010 2

001 001 xxx x SLL 0 1 0x 000 x

011 011 001 0 ADD 0 1 0x 000 x

xxx 000 011 1 ADD x 0 12 000 xxxx 010 xxx 1 SUB x 00 0 011 -5

Lecture 16:

Providing Even More Flexibility

• Replace control words with instructions– More intuitive and not specific to

particular hardware– Shorter than control words– Instruction decoder (hardwired logic)

creates the control words from the instruction

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PC

DRSASB

IMMMBFSMDLD

MWBS

OFFRAM

PC

Inst. RAM

Decoder

DRSASB

IMMMBFSMDLD

MWBS

Lecture 16: 18

Assembly Language• Human readable version of instructions

ADD rd,rs,rt // R[rd] = R[rs] + R[rt]

Dest RegSrc Reg

Src Reg

Operation15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Function

Lecture 16: 19

Register to Register Format (R-type)

• ALU operations with two source registers• Shift operations (arithmetic and logical)• NOP and HALT

Lecture 17: !9

Register to Register Format

• ALU operations with two source registers • Shift operations

– Logical: Shift in a 0 – Arithmetic: Shift in the sign bit

• NOP and HALT

Lecture 16:

Logical and Arithmetic Right Shift

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• Logical Right Shift– Shifts each bit right by 1 position– 0 shifted into MSB

• Arithmetic Right Shift – Preserves the sign bit

• Example: 11010000 SRA => 11101000 – Equivalent to division by 2 (for two’s complement)

Lecture 16: 21

Immediate Format (I-type)

• ALU instructions with an immediate operand• Load and Store instructions

– LB, SB: Load or store a byte (8 bits)– LW, SW: Load or store a word (16 bits)

• Branch instructions

Lecture 17: !10

Immediate Format

• ALU instructions with an immediate operand • Load and Store instructions

– LB, SB: Load or store a byte (8 bits) – LW, SW: Load or store a word (16 bits)

• Branch instructions

Lecture 16:

Memory Operations

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• The smallest addressable quantity in modern memory is typically a byte (8 bits) – A memory address points to a particular byte location

• LB : Load a byte – “give me the byte at this address”

• LW : Load a word, which in our case is two bytes – “give me the byte at this address and the next one too”

Lecture 16:

Branch Instructions

• Condition– Test two registers for equality (BEQ, BNE)– Test if a register is positive or negative (BGEZ, BLTZ)

• Target address– Where to jump in the program if the condition is true– Formed by adding the offset to the PC

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Lecture 17:

Branch Instructions

• Condition – Test two registers for equality (BEQ, BNE) – Test if a register is positive or negative (BGEZ, BLTZ) !

• Target – Where to jump in the program if the condition is true – Formed by adding the offset to the PC

!12

Target address

Lecture 16:

Forming the Branch Target Address

• A memory address points to a byte location

• If instructions are 2 bytes wide– Instructions are located at

even locations (0, 2, 4, ...)– The PC must be incremented

by 2 (PC+2)– Since the offset refers to the number of instructions (not bytes) to

jump, we must append a 0 to it

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SE(OFF) AdderMP

01

+1

SE({OFF,0}) AdderMP

01

+2

Lecture 17:

Branch Instructions

• Condition – Test two registers for equality (BEQ, BNE) – Test if a register is positive or negative (BGEZ, BLTZ) !

• Target – Where to jump in the program if the condition is true – Formed by adding the offset to the PC

!12

Lecture 16:

Multiplication Revisited

L0: SUB R0,R0,R0L1: LB R1,0(R0)L2: LB R2,1(R0) L3: SUB R3,R3,R3L4: ANDI R4,R2,1L5: SRL R2,R2L6: BEQ R4,R0,L8L7: ADD R3,R3,R1L8: SLL R1,R1L9: BNE R2,R0,L4L10: SW R3,2(R0)

OP RS FUNCTRT RD0001111 000 001000

0010 000 001 0000000010 000 010 0000011111 011 001011 0110110 010 100 0000011111 010 011xxx 0101000 000 100 0000101111 011 000001 0111111 001 100xxx 0011001 000 010 1110110011 000 010 000010

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Lecture 16:

Before Next Class • H&H 7.5.1-7.5.2

Next Time

Pipelined Microprocessor

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