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Chapter 3

FET Amplifiers

Spring 2012

4th Semester Mechatronics

SZABIST, Karachi

CH 322 12

FET

Amplifiers

Course Support

humera.rafique@szabist.edu.pk

Office: 100 Campus (404)

Official: ZABdesk

https://sites.google.com/site/zabistmechatronics/home/spring-2012/ecd

ebooks: https://sites.google.com/site/zabistmechatronics/home/ebooks

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Chapter Contents

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• JFET Small Signal Model

• Fixed Bias Configuration

• Self Bias Configuration

• Voltage Divider Configuration

• Common Gate Configuration

• Source Follower Configuration

• D and E type MOSFET Configurations

• FET Amplifier Network Design

• Cacade Configuration

• Applications

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4

FET

Small Signal Model

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FETs Advantages:

• Excellent voltage gain

• High input impedance

• Low-power consumption

• Good frequency range

FET Small Signal Model 5

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Transconductance:The relationship of a change in ID to the corresponding change inVGS:

FET Small Signal Model 6

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GS

Dm

V

Ig

∆

∆====

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Mathematical Definition of gm:

Where VGS =0V

Where

FET Small Signal Model 7

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Dm

G S

D SS G Sm

P P

D S Sm 0

P

G Sm m 0

P

G Sm m 0

P

Ig

V

2I Vg 1

V V

2Ig

V

Vg g 1

V

Vg g 1

V

∆=

∆

= −

=

= −

= −

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Example 8-1:

Determine the magnitude of gm for a JFET with IDSS = 8 mA and VP = −4 V

at the following dc bias points:

a. VGS = − 0.5 V

b. VGS = − 1.5 V

c. VGS = − 2.5 V

FET Small Signal Model 8

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Example 8-1:

Determine the magnitude of gm for a JFET with IDSS = 8 mA and VP = −4 V

at the following dc bias points:

a. VGS = − 0.5 V

b. VGS = − 1.5 V

c. VGS = − 2.5 V

FET Small Signal Model 9

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Example 8-2:

For the JFET of Ex 8-1, find:

a. gm (max)

b. gm at each point of Ex 8-1

FET Small Signal Model 10

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gm vs VGS:

FET Small Signal Model

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When VGS = 0V,

gm is maximum

When VGS = VP, gm is zero

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Example 8-3:

Using JFET of Ex 8-1, plot gm vs VGS.

FET Small Signal Model 12

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Example 8-3:

Using JFET of Ex 8-1, plot gm vs VGS.

FET Small Signal Model 13

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−=

P

GS

P

DSSm

V

V

V

Ig 1

||

2

||

20

P

DSSm

V

Ig =

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Effect of ID on gm:

Shockley’s equation:

FET Small Signal Model 14

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DSS

D

P

GS

I

I

V

V=−1

GSm m0

P

Dm m0

DSS

Vg g 1

V

Ig g

I

= −

=

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Plot of of ID vs gm:

FET Small Signal Model 15

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Dm m0

DSS

Ig g

I=

||

20

P

DSSm

V

Ig =

gm ID

gmo IDSS

0.707 gmo IDSS/2

0.5 gmo IDSS/4

0 0 mA

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Example 8-4:

Plot gm vs ID of Ex 8-1:

FET Small Signal Model 16

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Example 8-4:

Plot gm vs ID of Ex 8-1:

FET Small Signal Model 17

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Gm ID

gmo IDSS

0.707 gmo IDSS/2

0.5 gmo IDSS/4

0 0 mA

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JFET Zi:

FET input impedance, Zi is sufficiently large. Usually in the range of

109 Ω (1000MΩ)

JFET Zo:

FET output impedance, Zo is similar in magnitude to conventional BJTs.

Output impedance appears as yos with units of µs

where

FET Small Signal Model 18

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( )iZ FET = ∞Ω

constant VD

DSd GSI

Vr ========

∆∆∆∆

∆∆∆∆

osdo

y

1rZ ========

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Defining rd using JFET characteristics:

FET Small Signal Model 19

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Example 8.5:

Determine the output impedance for the given JFET for VGS = 0 V and − 2V

at VDS = 8V.

FET Small Signal Model 20

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JFET AC Equivalent:

FET Small Signal Model 21

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Example 8-6:

Given yfs = 3.8 mS and yos = 20 µS. Sketch the FET ac equivalent model:

FET Small Signal Model 22

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Ω

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JFET Configurations

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JFET Configurations:

1. Fixed bias (Common Source)

2. Self bias

3. Voltage-Divider bias

4. Common Gate

5. Source-Follower (Common Drain)

Important Parameters of AC Analysis:

1. Input impedance

2. Output impedance

3. Voltage Gain

JFET Configurations 24

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Fixed Bias

Configuration

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1. Fixed Bias Configuration (Common Source):

JFET Fixed Bias 26

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Determining Zi:

Substituting the JFET ac equivalent circuit unit into the fixed bias network

JFET Fixed Bias 27

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Determining Zi:

Redrawn network

JFET Fixed Bias 28

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( )i GZ FET R=

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Determining Zo:

JFET Fixed Bias 29

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( )o d DZ FET = r || R

iSet V 0=

( )o D

d D

Z FET = R

if r 10R≥

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Determining AV:

JFET Fixed Bias 30

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( )

( )

( )

( )

≥

v o i

m d D

v o i

m D d D

A = V V

= -g r || R

A = V V

= -g R when r 10R

( )

( )

o m gs d D

gs i

o m i d D

V = -g V r || R

V = V

V = -g V r || R

Phase reversal

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Example 8-7:AC analysis of the fixed-bias configuration of Ex 7-1: If yos = 40 µS, than,

determine:

a. gm

b. rd

c. Zi

d. Zo

e. Av

f. Av (ignoring the effects of rd)

JFET Fixed Bias 31

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IDQ=5.625mA; VGSQ = −−−−2V

yOS=40µµµµS

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Self Bias

Configuration

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JFET Self Bias:Bypassed RS

JFET Self Bias 33

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JFET Self Bias:

Fixed bias network following the substitution of the JFET ac equivalent

JFET Self Bias 34

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JFET Self Bias:

Redrawn network

JFET Self Bias 35

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JFET Self Bias:Unbypassed RS

JFET Self Bias 36

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i GZ R=

oo D

o

VZ R

I= =

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JFET Self Bias:Unbypassed RS

Including the effects of rd in the self bias JFET configuration

JFET Self Bias 37

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JFET Self Bias:Unbypassed RS

JFET Self Bias 38

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1

1

Sm S

d

O D

S Dm S

d d

Rg R

rZ R

R Rg R

r r

+ +

=

+ + +

O DZ R≅

11

O m D m Dv

S Di m Sm S

d

V g R g RA

R RV g Rg R

r

= = − ≅ −+ +

+ +

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Example 8-8:AC Analysis the self-bias configuration of Ex 7-2:

If yos = 20 µS, then, determine:

a. gm

b. rd

c. Zi

d. Zo (with and without the effects of rd ).

Compare the results.

e. Av (with and without the effects of rd ).

Compare the results.

JFET Self Bias 39

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Computer Analysis:

JFET Self Bias 40

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Voltage Divider

Configuration

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Voltage Divider Bias:

JFET Voltage Divider Bias 42

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Voltage Divider Bias:

JFET Voltage Divider Bias 43

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Voltage Divider Bias:

JFET Voltage Divider Bias 44

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ov m D

i

VA g R

V= ≅ −

o DZ R≅

1 2||iZ R R=

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Common-Gate

Configuration

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Common Gate Configuration:

JFET Common-Gate 46

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Common Gate Configuration:

JFET Common-Gate 47

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Common Gate Configuration:

JFET Common-Gate 48

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1||

i S

m

Z Rg

≅

o DZ R≅

'

1

1

D

d

i

m

d

R

rZ

gr

+

≅

+

v D mA R g≅

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Example 8-9:Determine:

a. gm

b. rd

c. Zi

d. Zo (with and without the effects of rd ).

Compare the results.

a. Vo (with and without the effects of rd ).

Compare the results.

JFET Common-Gate 49

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Source-Follower

(Common-Drain)

Configuration

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50

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Source-Follower (CD):

JFET Source-Follower (CD) 51

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Source-Follower (CD):

JFET Source-Follower (CD) 52

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Common-Follower (CD):

JFET Source-Follower (CD) 53

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Common-Follower (CD):

JFET Source-Follower (CD) 54

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Determining Zo

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Common-Follower (CD):

JFET Source-Follower (CD) 55

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1||

1

i G

o Sm

m S

m S

Z R

Z Rg

g RAv

g R

=

≅

≅+

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Example 8-10:AC analysis: VGSQ= 2.86 V and IDQ = 4.56 mA. Determine:

a. gm

b. Rd

c. Zi

d. Zo with and without rd. Compare results.

e. Av with and without rd. Compare results.

JFET Source-Follower (CD) 56

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Depletion-Type

MOSFETs

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MOSFET Configurations:

D-MOSFET:

1. Voltage Divider

E-MOSFET:

1. Drain Feedback

2. Voltage Divider

MOSFET Configurations 58

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D-MOSFET

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D-MOSFET Equivalent Model:

D-MOSFET Configurations 60

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Example 8-11:AC analysis (Ex 7-8): VGSQ = 0.36 V and IDQ = 7.6 mA. Determine:

a. gm and compare to gmo.

b. rd

c. Zi

d. Zo

e. Av

f. Sketch the ac equivalent

D-MOSFET Configurations 61

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Example 8-11:

D-MOSFET Configurations 62

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E-MOSFET

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Equivalent Circuit:

E-MOSFET Configurations 64

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E-MOSFET

Drain-Feedback

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Drain Feedback:

E-MOSFET Configurations 66

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Drain Feedback:

E-MOSFET Configurations 67

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Drain Feedback:

E-MOSFET Configurations 68

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Determining Zo

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Drain Feedback:

E-MOSFET Configurations 69

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Av=− gm(RF||rd||RD) Av=− gmRD

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Example 8-12:The E-MOSFET of Fig. 8-41 was analyzed in Example 7.11, with the result that

k = 0.24 x 10−3 A/V2, VGSQ = 6.4 V, and IDQ = 2.75 mA.

Determine gm.

a) Find rd.

b) Calculate Zi with and without rd. Compare results.

c) Find Zo with and without rd. Compare results.

d) Find Av with and without rd. Compare results.

E-MOSFET Configurations 70

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E-MOSFET

Voltage Divider

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Voltage Divider:

E-MOSFET Configurations 72

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Voltage Divider:

E-MOSFET Configurations 73

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Voltage Divider:

E-MOSFET Configurations 74

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Designing

FET

Amplifier Network

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Example 8-13:Design the fixed-bias network of Fig. 8-44 to have an ac gain of 10.

That is determine the value of RD.

Amplifier Network Designing 76

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Example 8-14:With a relatively high level of gm, select the values of RD and RS for the given

network, that will result in a gain of 8. For the device VGSQ = ¼ VP.

Amplifier Network Designing 77

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Example 8-15:With a relatively high level of gm, select the values of RD and RS for the given

network, that will result in a gain of 8. For the device VGSQ = ¼ VP. Now bypass

capacitor has been removed.

Amplifier Network Designing 78

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Summary Table 79

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Summary Table 80

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Summary Table 81

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Summary Table 82

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Effect of

RL and Rsig

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Effect of RL and Rsig:.

RL and Rsig84

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Effect of RL and Rsig:

RL and Rsig85

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Effect of RL and Rsig:.

RL and Rsig86

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Cascade

Configuration

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Cascade Configuration:

Cascade Configuration 88

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Av1 Av2Vi1

VO2VO1=Vi2

1 2.....v v v

A A A=

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Cascade Configuration:

Cascade Configuration 89

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Example 8-16:Calculate the dc bias, voltage gain, input impedance, output impedance and resulting

output voltage for the cascade amplifier shown in Fig. 8.49. Calculate the load

voltage if a 10-k load is connected across the output.

Cascade Configuration 90

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Example 8-17:For the cascade amplifier of Fig. 8-50, use the dc bias calculated in Example 8-15

and 8-16 to calculate the input impedance, output impedance, voltage gain, and

resulting output voltage.

Cascade Configuration 91

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Practical

Applications

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1. Three channel audio mixer

Practical Applications 93

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2. Phase Shift network

Practical Applications 94

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Reading:

1. Summary

2. Equations

3. Computer analysis

Problems:

1. Sec 8.2: (odd)

2. Sec 8.3: 17,18

3. Sec 8.4: 19,21

4. Sec 8.5:23,25

5. Sec 8.6: 27,29

6. Sec 8.7: 31

7. Sec 8.8: 33,35,37

8. Sec 8.10: 39,41

9. Sec 8.11: 43

10. Sec 8.12: 45

11. Sec 8.14: 47

12. Sec 8.15: 49

Home Task 95

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Refernces 96FET

1. Bolestad

2. Paynter

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