EC303_CHAPTER5

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MEMORY ELEMENT

CHAPTER 5

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Storage Hierarchies :Computer data storage often called storage or memory, refers to computer

components and recording media that retain digital data. Data storage is one of

the core functions and fundamental components of computers.

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PRIMARY STORAGE

• Primary storage (or main memory or internal memory), often referred to simply asmemory, is the only one directly accessible to the CPU. The CPU continuously readsinstructions stored there and executes them as required. Any data actively operated on isalso stored there in uniform manner.

RAM:• Processor registers are located inside the processor. Each register typically holds a word

of data (often 32 or 64 bits). CPU instructions instruct the arithmetic and logic unit to performvarious calculations or other operations on this data (or with the help of it). Registers are thefastest of all forms of computer data storage.

• Processor cache is an intermediate stage between ultra-fast registers and much slowermain memory. It's introduced solely to increase performance of the computer. Most activelyused information in the main memory is just duplicated in the cache memory, which is faster,

but of much lesser capacity.

• Main memory is directly or indirectly connected to the central processing unit via a memory bus . It is actually two buses ): an address bus and a data bus. The CPU firstly sends anumber through an address bus, a number called memory address, that indicates thedesired location of data. Then it reads or writes the data itself using the data bus.

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SECONDARY STORAGE

• Secondary storage (also known as external memory or auxiliary storage), differs fromprimary storage in that it is not directly accessible by the CPU. The computer usually usesits input/output channels to access secondary storage and transfers the desired data using

intermediate area in primary storage. Secondary storage does not lose the data when thedevice is powered down—it is non-volatile.

• Example: Flash drive, CD and DVD drives, floppy disks, punch cards.

TERTIARY STORAGE•

Tertiary storage or tertiary memory, provides a third level of storage. Typically it involvesa robotic mechanism which will mount (insert) and dismount removable mass storage mediainto a storage device according to the system's demands; this data is often copied tosecondary storage before use.

• Example: useful for extraordinarily large data stores, accessed without humanoperators(robotic arms). Typical examples include tape libraries and optical jukeboxes.

Off-line storage• Off-line storage is a computer data storage on a medium or a device that is not under the

control of a processing unit. The medium is recorded, usually in a secondary or tertiarystorage device, and then physically removed or disconnected. It must be inserted orconnected by a human operator before a computer can access it again. Unlike tertiarystorage, it cannot be accessed without human interaction.

• Example : Optical discs and flash memory devices

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Memory Devices Hierarchy

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There are four major storage levels:

1.Internal –

Processor registers and cache2.Main – the system RAM and controller

cards.

3.On-line mass storage –

Secondarystorage.

4.Off-line bulk storage – Tertiary and Off-

line storage.

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Virtual Memory Organization

– Solves problem of limited memory space

–

Creates the illusion that more memory exists than is available in system

Virtual memory combines active RAM and

inactive memory in disk form into a large range

of contiguous addresses.

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2 Approaches of virtual memory organization:

Linear Virtual Memory• Virtual memory usually has linear ordered addresses in the range [0, M] where some

regions may be inaccessible

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Paging • In a paged system, there are fixed-size blocks of memory called pages that

are allocated to a process. A memory reference consists of a page numberand an offset within the page. The memory management unit (MMU) uses thevirtual page number to look up the physical page number. Because the virtualaddress space can be quite large, the look-up usually involves hashing, andpossibly additional search. However, only one piece of an address is needed asthe look-up key.

• With a paged system, there is one address space and every reference must bechecked to ensure that it refers to a page that has been allocated to the currentprocess. The operating system allocates pages from this one address space asneeded. The operating system can swap out a subset of the pages that areallocated to a process and bring them into memory when they are needed again.The down side is that a process can get into a pattern of access where it isfrequently page-faulting and starts to operate at disk access speeds.

• Because the pages are fixed in size, they may be only partially used. Thisinternal fragmentation was a significant problem when machine memories weretiny, but is now negligible. However, it lead to the notion of segmentation as analternative that avoids internal fragmentation.

2 Techniques of virtual memory organization:

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• Segmentation

• In a segmented system, the blocks of memory are variable in size. Eachprocess may have one or more segments. The segments may be visible to theprocess, that is, it may be aware that there are code, data, stack, and heap

segments (whereas pages are usually transparent). A segment table is usedthat specifies the base of the physical addresses associated with a segment andthe valid range. The combination of this base and the offset specified by theaddress means that two words must be used by the MMU to identify the physicaladdress.

• One advantage to the operating system is that once a segment has been

allocated, there won't be any access faults from the process except those thatactually try to access beyond the segment boundaries. Thus, once a processhas started, it can run at memory rates until it returns control to the OS. Ofcourse, this leads to the problem that if a segment is large, the time for a contextswitch can be excessive.

• An access outside of the segment is detected as exceeding the valid range, andis trapped. Segmented virtual addressing is otherwise similar to paging. Oneproblem with pure segmentation is external fragmentation (holes in the addressmap following a series of allocations and deallocations) that can lead to lowmemory utilization. External fragmentation is also called checkerboarding, andits correction requires a phase of memory compaction that reduces processingefficiency.

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Cache Memory

• Cache memory is random access memory (RAM) that a computer

microprocessor can access more quickly than it can access regular RAM. As the

microprocessor processes data, it looks first in the cache memory and if it finds

the data there (from a previous reading of data), it does not have to do the more

time-consuming reading of data from larger memory.

• Direct Mapped : Each block from main memory has only one place it can

appear in the cache

• Example: We have a Cache memory of 512KB (i.e. 219), divided into blocks of

each 32 bytes (25). Thus there are 16K (i.e. 219 /25 = 214) blocks also known as

Cache slots or Cache lines in cache memory. It is clear from above numbers

that there are more Main memory blocks than Cache slots.

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Direct mapping assigned each memory block to a specific line in the cache. If a

line is all ready taken up by a memory block when a new block needs to be loaded,

the old block is trashed. The figure below shows how multiple blocks are mapped to

the same line in the cache. This line is the only line that each of these blocks can be

sent to. In the case of this figure, there are 8 bits in the block identification portion of

the memory address.

Once the block is stored in the line of the cache, the tag is copied to the tag

location of the line.

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Direct Mapping Summary• The address is broken into three parts: (s-r) MSB bits represent the tag to be

stored in a line of the cache corresponding to the block stored in the line; r bits inthe middle identifying which line the block is always stored in; and the w LSBbits identifying each word within the block. This means that:

• The number of addressable units = 2s+w words or bytes

• The block size (cache line width not including tag) = 2w words or bytes

• The number of blocks in main memory = 2s (i.e., all the bits that are not in w)

• The number of lines in cache = m = 2r

• The size of the tag stored in each line of the cache = (s - r) bits

• Direct mapping is simple and inexpensive to implement, but if a programaccesses 2 blocks that map to the same line repeatedly, the cache begins tothrash back and forth reloading the line over and over again meaning misses arevery high.

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Decoder• A decoder is a device which does the reverse of an encoder, undoing the

encoding so that the original information can be retrieved.

Four-output decoder and a parallel decoder

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Determine the digital circuit in a tree-type

decoding network with 16 output lines• The first stage is a 2-to-4-line decoder. A new variable is introduced in each successive

stage; it or its inverse becomes one input to each of the two-input AND gates in this stage.The second input to each AND gate comes from the preceding stage. For example, one ofthe outputs of the second stage will be AB'C. This will result in two outputs from the next stage, AB'CD and AB'CD'. This design does avoid the fan-out problem in the early stagesbut not in the later stages. Nevertheless, the problem exists only for the variables introducedin those stages.

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A balanced multiplicative decoder network

• Requires the minimum number ofdiodes

•

This decoder circuit is the fastest andmost regular.

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Describe the buses line to interface memory• In computer architecture, a bus is a subsystem that transfers data between

components inside a computer, or between computers.

How the RAM chip works?

a) Data bus -Carry information

b) Address bus- Determine where it

should be sent

c) Control bus - Determine its

operation

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Read cycle for a RAM chip

• Read Bus Cycle: Describes the operations carried out by the processor when amemory read is executed.

Step of Read Bus Cycle:

• Processor initiates a read bus cycle by floating the address of the memorylocation on the address lines.

• Once the address lines are stable, the processor asserts the address strobesignal on the bus. The address strobe signals the validity of the address lines.

• Processor then sets the Read/Write* signal to high, i.e. read.

• Now the processor asserts the data strobe signal. This signals to the memorythat the processor is ready to read data.

• The memory subsystem decodes the address and places the data on the datalines.

• The memory subsystem then asserts the data acknowledge signal. This signalsto the processor that valid data can now be latched in.

• Processor latches in the data and negates the data strobe. This signals to thememory that the data has been latched by the processor.

• Processor also negates the address strobe signal.

• Memory subsystem now negates the data acknowledgement signal. This signalsthe end of the read bus cycle.

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Read cycle

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• Write Bus Cycle: Sequence of operations in memory write is described here.

Step of Write Bus Cycle:

• Processor initiates a write bus cycle by floating the address of the memorylocation on the address lines.

• Once the address lines are stable, the processor asserts the address strobesignal on the bus. The address strobe signals the validity of the address lines.

• Processor then sets the Read/Write* signal to low, i.e. write.• The processor then places the data on the data lines.

• Now the processor asserts the data strobe signal. This signals to the memorythat the processor has valid data for the memory write operation.

• The memory subsystem decodes the address and writes the data into theaddressed memory location.

• The memory subsystem then asserts the data acknowledge signal. This signalsto the processor that data has been written to the memory.

• Then the processor negates the data strobe, signaling that the data is no longervalid.

• Processor also negates the address strobe signal.

• Memory subsystem now negates the data acknowledgement signal, signaling an

end to the write bus cycle.

Write cycle for a RAM chip

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Write cycle

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How CPU read from memory and write to

memory

• The computer loads the operating system (OS) from the hard drive into the

system's RAM. Generally, the critical parts of the operating system aremaintained in RAM as long as the computer is on. This allows the CPU to haveimmediate access to the operating system, which enhances the performanceand functionality of the overall system.

• When you open an application, it is loaded into RAM. To conserve RAM usage,many applications load only the essential parts of the program initially and then

load other pieces as needed.• After an application is loaded, any files that are opened for use in that

application are loaded into RAM.

• When you save a file and close the application, the file is written to the specifiedstorage device, and then it and the application are purged from RAM.

• In the list above, every time something is loaded or opened, it is placed into

RAM. This simply means that it has been put in the computer's temporarystorage area so that the CPU can access that information more easily. The CPUrequests the data it needs from RAM, processes it and writes new data back toRAM in a continuous cycle. In most computers, this shuffling of data betweenthe CPU and RAM happens millions of times every second. When an applicationis closed, it and any accompanying files are usually purged (deleted) from RAMto make room for new data. If the changed files are not saved to a permanent

storage device before being purged, they are lost.

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Static random-access memory (SRAM)• Static random access memory (SRAM) is a type of volatile semiconductor

memory to store binary logic '1' and '0' bits. SRAM uses bistable latching

circuitry made of Transistors/MOSFETS to store each bit. Compared to DynamicRAM (DRAM), SRAM does't have a capacitor to store the data, hence SRAMworks without refreshing. In SRAM the data is lost when the memory is notelectrically powered.

• SRAM is faster and more reliable than the more common DRAM . While DRAMsupports access times (access time is the time required to read or write data

to/from memory) of about 60 nanoseconds, SRAM can give access times as lowas 10 nanoseconds. In addition, its cycle time is much shorter than that ofDRAM because it does not need to pause between accesses. Unfortunately, it isalso much more expensive to produce than DRAM. Due to its high cost, SRAMis often used only as a memory cache.

• SRAM is generally used for high-speed registers, caches and relatively smallmemory banks such as a frame buffer on a display adapter. In contrast, the

main memory in a computer is typically dynamic RAM (DRAM, D-RAM).

• An SRAM is designed to fill two needs: to provide a direct interface with the CPUat speeds not attainable by DRAMs and to replace DRAMs in systems thatrequire very low power consumption. In the first role, the SRAM serves as cachememory, interfacing between DRAMs and the CPU.

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Typical microprocessor memory configuration

Basic memory component connections Asynchronous SRAM- Logical & pin diagrams

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• The pin connections common to all type of memory devices (including SRAM)are the address inputs, data I/O, some type of selection input and at least onecontrol input used to select a read or write operation.

• The address inputs are used to connect or select a memory location within thememory device. The memory device that has 10 address lines will be having itsaddress pins labeled from A0 (Least Significant) to A9.

• The number of memory address pins found on a memory device is determinedby the number of memory locations found within it. The data I/O connections arethe points at which the data are entered for storage or extracted for reading.

• Today the memory devices are equipped with bi-directional common data I/Olines.The SRAM has an input that selects or enables the memory device, called chipselect (CS). If this pin is active (a logic 0 applied at this pin) the memory deviceperforms a read or a write operation.

• The other two control inputs associated with SRAM are Write Enable (WE) and

Output (also called read enable) Enable (OE). Sometimes the (WE) is labeled as(W) and the (OE) is labeled as (G). The write enable pin must be made active(applying logic 0) to perform a memory write operation and the (OE) must beactive to perform a read operation from the memory. But they must never bothbe active at the same time.

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Dynamic random-access memory (DRAM)

• A type of random-access memory that stores each bit of data in aseparate capacitor within an integrated circuit. The capacitor can be

either charged or discharged; these two states are taken to representthe two values of a bit, conventionally called 0 and 1.

• Since capacitors leak charge, the information eventually fades unlessthe capacitor charge is refreshed periodically. Because of this refreshrequirement, it is a dynamic memory as opposed to SRAM and other

static memory.• The main memory (the "RAM") in personal computers is Dynamic RAM

(DRAM). It is the RAM in laptop, notebook and workstation computersas well as some of the RAM of home game consoles (PlayStation3,Xbox 360),

• The advantage of DRAM is its structural simplicity: only one transistor

and a capacitor are required per bit, compared to six transistors inSRAM. This allows DRAM to reach very high densities. Unlike flashmemory, DRAM is volatile memory(cf. non-volatile memory), since itloses its data quickly when power is removed. The transistors andcapacitors used are extremely small; billions can fit on a single memorychip.

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DRAM pin diagrams

R d O l M (ROM)

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Read Only Memory (ROM)

• Read-only memory (ROM) is a class of storage medium used in computers andother electronic devices. Data stored in ROM cannot be modified.

• ROM indicates a non-volatile memory which serves functions typically provided

by mask ROM, such as storage of program code and nonvolatile data.

ROM pin diagrams

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