EC Q2 Communication
Transcript of EC Q2 Communication
DESIGNING TOMORROW’S CHIPSYatin Hoskote
Director, Soc Technology and IP
Intel labs
MEMOCODE Oct 2013
MEMOCODE 2013 2
The number of devices is exploding
What are compute devices going to look like in the100 billion device market?
MEMOCODE 2013
Wearable Computing
Mobile
Computing
Invisible Computing
Intelligent Computing Everywhere
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MEMOCODE 2013
IoT Revolution
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Car
Work
Home
My Devices
Retail
Healthcare
Buildings
Transportation
Resources
Cities
Personal Cloud
Energy
Fully Evolved IoT = Fully Interconnected and Interoperable “System of Systems”
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Specialized Algorithms
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Gesture Recognition
Hand Gestures / Body Pose
Speech Recognition
Continuous Speech Recognition
Interest Point Detection
Descriptor Generation
Match (L1/L2 Distance)
GMM (Gaussian Mixture Model)
HMM (Hidden Markov Model)
Neural Networks, WFST, etc
Feature Extraction
HMM (Hidden Markov Model)
Need power-efficient, real-time implementations
Need better accuracy, higher levels of cognition
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High Level of Integration
• Communications, compute, sensors, actuators etc
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AmbientLight
Sensor
Accelerometer
Gyrometer(Gyro)
(Gyroscope)
Magnetometer(Compass)
Inclinometer(Tiltmeter)
DeviceOrientation
GPS WiFi BT LE
NFC Piezoelectricactuator
ImagesensorMicrophone Haptics
Fingerprintsensor
Proximitysensor
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Ultra Low Power
• Long battery life, always on, always connected, low power communications, aggressive power management
• Low cost
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Power/ Battery Life Challenge
>10X gap!
1.5Whr battery has 2hrs life capturingaudio/video
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Rapid Design Environment
• Need smaller focused teams with domain expertise working in a design environment that enables rapid prototyping at multiple levels
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Systems engineering
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Platform based design
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Model-based Top-down Design Flow
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MRD
UX prototyping
Reference modeling
Algorithmic refinement
System modeling
Design space exploration
HW/SW Co-design
Emulation
Silicon and FFRD
Refinem
ent
Feedback
Lib
rary
of buildin
g b
locks
Test
corp
us
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UX Prototyping
• Mock ups
• Focus groups
• Smoke and mirror prototypes
• User experiences and usages
• Suite of workloads and expected results
• Decide on quality metrics
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Cessna TTx cockpit mockup
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Personal Billboard UX
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A design research prototype that explores new ways for people to
express themselves in real-time, in the same physical location.
The Billboard app allows people to display text and images on the cover
screen of a dual-screen Ultrabook, and for others to interact with this content by “liking”, voting on, or “peeling” a copy of the displayed content
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Reference Modeling
• Functional models and executable spec
• Models of sensors, actuators, peripherals
• Reuse and enhance suite of UX workloads
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Face
Iris
Voice
Location
Phone interface
Camera Trace
Mic.Trace
GPS Trace
Bluetooth Trace
Gesture
Authen.
control
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Algorithmic Refinement
Edge-detectionAlgorithm
• Key step, requiring domain expertise
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Design Space Exploration: Steps x Levels
Define appropriate architecture and deploy given applications onto it
Applications
ConstraintsE.g. Power for given workloads
Implementation
Architecturetemplates
DSE SoC IP
Define
Analyze
Optimize
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System Modeling
• Functional and data partitioning
• Models for all sensors, actuators, peripherals
• Reuse and enhance workloads and test corpus
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CPU SRAM Face Iris Gesture
Voice GPS BT LEDMA
Fabric
SW +
Tests
FW
Initial architecture model
camera miclocation
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Single Source System Model
• Consistency among models and with golden model• Models are at multiple different levels of abstraction
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Golden HLM
VPHLSPower
estimationArchitectureexploration
Functionalvalidation
Post-Sidebug
Performanceverification
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Example: System Power Modeling
• Display power profile for real workloads
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Expected results
Time
Power
Sys_off
Always Available (AAV)
Audio Log Video LogTake Pic
States include single or multiple function (e.g. image capturing, storing, button pressing etc.)
State
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Video Subsystem
Example: Functional Validation
• System model constructed from functional model(s), 3rd party IP, and firmware
• Common trace points ( ) identified for system model and RTL model
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Raw
RGB
RGB
YCbCr
JPEG Encoder
PacketizerRaw
CameraData
DMA
Shared
Memory
Bus
Host core
InstructionSet
Simulator
Firmware
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IP Implementation
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Codesign Memory analysis Code refactoring
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HW/SW Codesign
TLM Untimed
TLM LT/AT
Synthesizable
Cycle Accurate
HLS
RTL SystemVerilog
Synthesis
Netlist
C/C++
Compiler
Firmware
Binary
HW/SW partitioning
Cycle Approximate
Cycle Accurate
Untimed
Perf
orm
ance
/Co
st F
eed
bac
k
SystemC
Reference ModelC++/Matlab
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Modelrefinement
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HLS Flow
TLM
Block Level Synthesis
Synthesizable HLS Models
Virtual SystemPrototypes
FPGA
Interface IPGenerator
Memory IP Generator
HL Synthesis
Control Datapath IP
RTL
Optimizer
ASIC
Control and Data Flow Graphs
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IP
Standard Cells
Memory
compiler
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Interface
Inner loop RAM optimization
630
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Long Path Optimization
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Pipelined design20
10
30
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1.3ns clk
50
40
60
2d 3d 4d 5d 6d1day 2weeks 6months
Exploring the Design Space
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7d 8d 9d 10d
Dual Input Read
Compiled C to DSP Core1
Handcrafted RTL
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1
2 Memory Buffer
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Development Time
Dela
y *
are
a
Viterbi Decoder with Soft Outputs
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Next Generation HLS
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Abstr
action
Micro-Architecture
& Control
Scheduled
Transistor
Post-Timed
Gate
Pre-Timed
Timed
Physical
Unscheduled = No clock
Scheduled = Clocks
Design Complexity
Power(cpf/upf)Test (ctl)
Floor Plan(def)
Sine
Macro-Architecture
Unscheduled
RTL(IP)
Scheduled
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Programmable Accelerators
• Domain specific instruction processors
• Architecture Description Language ADL
• Complete tool suite
– Base architecture template
– Design tools to go from source code to RTL
– Programming tools for firmware development
• Fast development loop
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Architecture
Description
Instruction
Gen
App
src
Which way to go further
HW
modification
Simulator
Metrics
Algorithm/
SW
modification
Compiler
RTL
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IP Library ToolKit
Parametric
Algorithmic Pyramid
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RTL
Drivers/FW
Test
Debug
ESL
Parameters
Workloads
IP Stack
Configurable
Vertical IP
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Software Development
• Software development cost is outpacing hardware
• Hybrid virtual platforms
• Single source model
• Validation
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App
proc
VP
ProcessorSimulator+ wrapper
FPGA
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Emulation
• Path to FPGA from high level models using high level synthesis
• Functional validation and SW development
• Highly useful as a demonstration vehicle
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MEMOCODE 2013
Summary
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UX prototyping
Reference modeling
Algorithmic refinement
System modeling
Design space exploration
HW/SW Co-design
Emulation
Silicon and FFRD
Lib
rary
of buildin
g b
locks
Test
corp
us
MEMOCODE 2013
Call to Action
• Need a formal refinement methodology
– Equivalence verification
– Automatic generation of models
– Compositional verification for constraints and behavior
• Design support
– Feedback to designer at each step for quick iterations
– Debug assistance
• Embedded software analysis
– Firmware code generation / driver synthesis
– Firmware validation
• IP library and standardization
– Analog and mixed signal IP
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THANK YOU
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