EC 513 - ascslab.orgascslab.org/courses/ec513/lectures/L04.pdf · Central Processing Unit (CPU) §...

Department of Electrical & Computer Engineering

EC 513Computer Architecture

Prof. Michel A. Kinsy

Pipelining & Hazards


Single Cycle RISC-V CPU

ReadAddress Inst[31-0]

ADD

PC

4

WriteData

ReadAddr1

ReadAddr2

WriteAddr

RegisterFile

ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

ReadData

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

Instr[30,14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

ControlUnit

Instr[31-21]

Branch

DataMemory

InstructionMemory


Central Processing Unit (CPU)

§ Central Processing Unit (CPU) Organization

§ CPU Execution Process 1. Fetch Instruction 2. Decode Instruction 3. Execute Operation 4. Memory Operation 5. Register Writeback Operation

Fetch Instruction

Decode Increment PCRead registers

ALU Operation Or

Branch Address

Data Memory Operation

Write Back




ADD

PC

4

WriteData

ReadAddr1

ReadAddr2

WriteAddr

RegisterFile

ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

ReadData

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

Instr[30,14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

ControlUnit

Instr[31-21]

Branch

DataMemory

InstructionMemory



ADD

PC

4

WriteData

ReadAddr1

ReadAddr2

WriteAddr

RegisterFile

ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

ReadData

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

Instr[30,14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

ControlUnit

Instr[31-21]

Branch

DataMemory

InstructionMemory


IDIF EXE MEM WB



ADD

PC

4

WriteData

ReadAddr1

ReadAddr2

WriteAddr

RegisterFile

ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

ReadData

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

Instr[30,14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

ControlUnit

Instr[31-21]

Branch

DataMemory

InstructionMemory

Multi-Cycle RISC-V CPU

IDIF EXE MEM WB


Multi-Cycle RISC-V Processor § Single cycle processor

§ The cycle time has to be long enough for the slowest instruction to complete

§ CPI = 1

§ Multi-cycle Implementation§ Instructions are broken into smaller steps§ Execute each step (instead of the entire

instruction) in one cycle§ The cycle time has to be long enough for the

slowest step to complete


Multi-Cycle RISC-V Processor § The advantages of the multiple cycle processor

§ Cycle time is much shorter§ Different instructions take different number of

cycles to complete§ Load takes five cycles§ Jump only takes three cycles§ CPI is between 3 and 5

addi x10,x10,513j label


Multi-Cycle RISC-V Processor addi x10,x10,513jlabelIDIF EXE MEM WB

5ps 5ps 5ps 5ps 5ps

25psaddi x10,x10,513 jlabel

50ps

40ps


Multi-Cycle RISC-V Processor § Although CPI increased overall execution time is

shortened, so performance is improved!

§ Performance can be improved even more with pipelining!

Time =Instructions Cycles TimeProgramProgram*Instruction*Cycle


Task Pipelining § How to move from stage to stage?

§ Buffers/ Registers

stage1

stage2

stage3

stage4

stage1

stage2

stage3

stage4


Ideal Pipeline

§ All objects go through the same stages§ No sharing of resources between any two stages§ Propagation delay through all pipeline stages is

equal

stage1

stage2

stage3

stage4


5-Stage RISC-V Pipelining

Instruction Fetch Execute

Instruction Decode WriteBackMemory

InstructionFetch

Instruction Decode

Execute Memory Writeback


Multi-Stage RISC-V CPU


ADD

PC

4

WriteData

ReadAddr1

ReadAddr2

WriteAddrRegisterFile

ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

ReadData

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30,14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]


Pipelined Datapath

Write-backStage

FetchStage

ExecuteStage

Decode Stage

MemoryStage

IDIF EXE MEM WB


ADD

PC

4

WriteData

Read Addr 1

Read Addr 2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

Read Data

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30, 14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]


5-Stage Pipelined

Time t0 t1 t2 t3 t4 t5 t6 t7 . . . .Instruction1 IF1

Write-backStage

FetchStage

ExecuteStage

Decode Stage

MemoryStage


ADD

PC

4

WriteData

Read Addr 1

Read Addr 2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

Read Data

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30, 14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]


Time t0 t1 t2 t3 t4 t5 t6 t7 . . . .Instruction1 IF1 ID1

Instruction2 IF2

5-Stage Pipelined

Write-backStage

FetchStage

ExecuteStage

Decode Stage

MemoryStage


ADD

PC

4

WriteData

Read Addr 1

Read Addr 2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

Read Data

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30, 14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]


Time t0 t1 t2 t3 t4 t5 t6 t7 . . . .Instruction1 IF1 ID1 EX1

Instruction2 IF2 ID2

Instruction3 IF3

5-Stage Pipelined

Write-backStage

FetchStage

ExecuteStage

Decode Stage

MemoryStage


ADD

PC

4

WriteData

Read Addr 1

Read Addr 2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

Read Data

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30, 14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]


Time t0 t1 t2 t3 t4 t5 t6 t7 . . . .Instruction1 IF1 ID1 EX1 MA1

Instruction2 IF2 ID2 EX2

Instruction3 IF3 ID3

Instruction4 IF4

5-Stage Pipelined

Write-backStage

FetchStage

ExecuteStage

Decode Stage

MemoryStage


ADD

PC

4

WriteData

Read Addr 1

Read Addr 2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

Read Data

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30, 14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]


Time t0 t1 t2 t3 t4 t5 t6 t7 . . . .Instruction1 IF1 ID1 EX1 MA1 WB1

Instruction2 IF2 ID2 EX2 MA2

Instruction3 IF3 ID3 EX3

Instruction4 IF4 ID4Instruction5 IF5

5-Stage Pipelined

Write-backStage

FetchStage

ExecuteStage

Decode Stage

MemoryStage


ADD

PC

4

WriteData

Read Addr 1

Read Addr 2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

Read Data

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30, 14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]



Instruction2 IF2 ID2 EX2 MA2 WB2

Instruction3 IF3 ID3 EX3 MA3

Instruction4 IF4 ID4 EX4Instruction5 IF5 ID5

5-Stage Pipelined

Write-backStage

FetchStage

ExecuteStage

Decode Stage

MemoryStage


ADD

PC

4

WriteData

Read Addr 1

Read Addr 2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

Read Data

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30, 14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]





Instruction4 IF4 ID4 EX4 MA4Instruction5 IF5 ID5 EX5

5-Stage Pipelined

Write-backStage

FetchStage

ExecuteStage

Decode Stage

MemoryStage


ADD

PC

4

WriteData

Read Addr 1

Read Addr 2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

Read Data

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30, 14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]





Instruction4 IF4 ID4 EX4 MA4 WB4Instruction5 IF5 ID5 EX5 MA5

5-Stage Pipelined

Write-backStage

FetchStage

ExecuteStage

Decode Stage

MemoryStage


ADD

PC

4

WriteData

Read Addr 1

Read Addr 2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

Read Data

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30, 14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]





Instruction4 IF4 ID4 EX4 MA4 WB4Instruction5 IF5 ID5 EX5 MA5 WB5

5-Stage Pipelined

Write-backStage

FetchStage

ExecuteStage

Decode Stage

MemoryStage


ADD

PC

4

WriteData

Read Addr 1

Read Addr 2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

Read Data

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30, 14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]


Time t0 t1 t2 t3 t4 t5 t6 t7 . . . .instruction1 IF1 ID1 EX1 MA1 WB1

instruction2 IF2 ID2 EX2 MA2 WB2

instruction3 IF3 ID3 EX3 MA3 WB3

instruction4 IF4 ID4 EX4 MA4 WB4instruction5 IF5 ID5 EX5 MA5 WB5

5-Stage Pipelined

Write-backStage

FetchStage

ExecuteStage

Decode Stage

MemoryStage


ADD

PC

4

WriteData

Read Addr 1

Read Addr 2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

Read Data

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30, 14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]


time t0 t1 t2 t3 t4 t5 t6 t7 . . . IF I1 I2 I3 I4 I5ID I1 I2 I3 I4 I5EX I1 I2 I3 I4 I5MA I1 I2 I3 I4 I5WB I1 I2 I3 I4 I5

Reso

urce

s

5-Stage Pipelined

Write-backStage

FetchStage

ExecuteStage

Decode Stage

MemoryStage


ADD

PC

4

WriteData

Read Addr 1

Read Addr 2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

Read Data

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30, 14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]


Multi-Stage & Control Signals


ADD

PC

4

WriteData

ReadAddr1

ReadAddr2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

ReadData

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30,14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]

WB

MA

EX

WB

MA

WB


Execution Simulation§ Consider the following instruction sequence

lw x1, 8(x2)

sw x3, 24(x4)

add x5, x6, x7sub x8, x6, x7

lw x1, 4(x2)


Execution Simulation: Cycle 1lw x1, 8(x2)


ADD

PC

4

WriteData

ReadAddr1

ReadAddr2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

ReadData

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30,14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]


Execution Simulation: Cycle 2sw x3, 24(x4) lw x1, 8(x2)


ADD

PC

4

WriteData

ReadAddr1

ReadAddr2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

ReadData

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30,14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]


Execution Simulation: Cycle 3Add x5,x6, x7 lw x1, 8(x2)sw x3, 24(x4)


ADD

PC

4

WriteData

ReadAddr1

ReadAddr2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

ReadData

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30,14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]


Execution Simulation: Cycle 4sub x8, x6, x7 lw x1, 8(x2)Add x5,x6,x7 sw x3, 24(x4)


ADD

PC

4

WriteData

ReadAddr1

ReadAddr2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

ReadData

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30,14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]


Execution Simulation: Cycle 5lw x1, 4(x2) sub x8, x6, x7 lw x1, 8(x2)Add x5,x6,x7 sw x3, 24(x4)


ADD

PC

4

WriteData

ReadAddr1

ReadAddr2


ReadData1

ReadData2

ALU

Overflow

zero

RegWrite

Address

WriteData

ReadData

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

DataMemory

InstructionMemory

RegWrite

Instr[30,14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]


Instruction Interactions § An instruction in the pipeline may need a

resource being used by another instruction in the pipeline § Structural hazard

§ An instruction may depend on something produced by an earlier instruction§ Dependence may be for a data calculation

§ Data hazard§ Dependence may be for calculating the next

address§ Control hazard (branches, interrupts)


Multi-Stage RISC-V CPU

Address

Inst[31-0]

PC

WriteData

ReadAddr1

ReadAddr2


ReadData1

ReadData2

ALU

Overflow

zero

Address

WriteData

ReadData

MemWrite

MemRead

SignExtend

32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

Memory

RegWrite

RegWrite

Instr[30,14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]

ADD

4

0


Structural Hazard§ Consider the following instruction sequence

lw x1, 8(x2)

sw x3, 24(x4)

add x5, x6, x7sub x8, x6, x7

lw x1, 4(x2)


Structural Hazardsub x8, x6, x7 lw x1, 8(x2)add x5,x6,x7 sw x3, 24(x4)

Address

Inst[31-0]

PC

WriteData

ReadAddr1

ReadAddr2


ReadData1

ReadData2

ALU

Overflow

zero

Address

WriteData

ReadData

MemWrite

MemRead

SignExtend32 64

MemtoReg

ALUSrc

Shiftleft1

ADD

PCSrc

ALUControl

1

1

00

0

1

ALUOp

ControlUnit

Branch

Memory

RegWrite

RegWrite

Instr[30,14-12]

Instr[19-15]

Instr[24-20]

Instr[11-7]

Instr[31-21]

ADD

4

0


Instruction Interactions subt0,t1,t2addt3,t4,t5addt6,s2,s3subt1,s3,s2lw t2,16(t4)addt5,t5,s2sw t0,16(s3)

subt0,t1,t2 Decode ALU DMemIFetch WB


Instruction Interactions

Decode ALU DMemIFetch WB

addt3,t4,t5 Decode ALU DMemIFetch WB

subt0,t1,t2subt0,t1,t2addt3,t4,t5addt6,s2,s3subt1,s3,s2lw t2,16(t4)addt5,t5,s2sw t0,16(s3)





subt0,t1,t2

addt3,t4,t5

addt6,s2,s3 Decode ALU DMemIFetch WB

subt0,t1,t2addt3,t4,t5addt6,s2,s3subt1,s3,s2lw t2,16(t4)addt5,t5,s2sw t0,16(s3)





subt0,t1,t2

addt3,t4,t5


subt1,s3,s2 Decode ALU DMemIFetch WB

addt6,s2,s3

subt0,t1,t2addt3,t4,t5addt6,s2,s3subt1,s3,s2lw t2,16(t4)addt5,t5,s2sw t0,16(s3)


Instruction Interactions § Supposed that we have the following set of

instructions:

subt0,t1,t2addt3,t0,t4addt5,t0,t6subs2,s3,t0lw s4,16(t0)adds4,s4,s2sw s4,16(t0)


Instruction Interactions subt0,t1,t2addt3,t0,t4addt5,t0,t6subs2,s3,t0lw s4,16(t0)adds4,s4,t7sw s4,16(t0)

subt0,t1,t2 Decode ALU DMemIFetch WB





subt0,t1,t2subt0,t1,t2addt3,t0,t4addt5,t0,t6subs2,s3,t0lw s4,16(t0)adds4,s4,t7sw s4,16(t0)





subt0,t1,t2

addt3,t0,t4


subt0,t1,t2addt3,t0,t4addt5,t0,t6subs2,s3,t0lw s4,16(t0)adds4,s4,t7sw s4,16(t0)





subt0,t1,t2

addt3,t0,t4


X






subt0,t1,t2

addt3,t0,t4


Bubble






subt0,t1,t2

addt3,t0,t4


Bubble

Bubble






subt0,t1,t2

addt3,t0,t4


Bubble

Bubble

Bubble

Bubble






subt0,t1,t2

addt3,t0,t4


Bubble

Bubble

Bubble

Bubble

Bubble

Bubble






addt3,t0,t4


subs2,s3,t0 Decode ALU DMemIFetch WB

addt5,t0,t6

Bubble Bubble

Bubble Bubble Bubble



timet0 t1 t2 t3 t4 t5 t6 t7 . . .

IF I1 I2 I3 I3 I3 I3 I4 I5ID I1 I2 I2 I2 I2 I3 I4EX I1 nop nop nop I2 I3MA I1 nop nop nop I2WB I1 nop nop nop

Stalled Stages and Pipeline

timet0 t1 t2 t3 t4 t5 t6 t7 . .

(I1) r1 ß (r0) + 10 IF1 ID1 EX1 MA1 WB1

(I2) r4 ß (r1) + 17 IF2 ID2 ID2 ID2 ID2 EX2 MA2

(I3) IF3 IF3 IF3 IF3 ID3 EX3(I4) IF4 ID4

(I5) IF5stalled stages

Resource Usage


Stalled Stages and Pipeline§ Pipelining was introduced to improve

performance

§ But with stalling, CPI will go up§ So we need a way to reduce stalling cycles!

Time =Instructions Cycles TimeProgramProgram*Instruction*Cycle


Next Class§ Hazard Resolution

EC 513 - ascslab.orgascslab.org/courses/ec513/lectures/L04.pdf · Central Processing Unit (CPU) §...

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Transcript of EC 513 - ascslab.orgascslab.org/courses/ec513/lectures/L04.pdf · Central Processing Unit (CPU) §...