EC 2155- Circuits and Devices Lab Manual Cum Observation

of 118 ECE Department

Circuit Diagram:

Figure -1

EC2155/ Circuits and Devices Lab Manual cum Observation


Expt.No: Date Verification of Kirchoff’s Laws

Aim

To verify (i) Kirchhoff’s current law (KCL) (ii) Kirchhoff’s voltage law (KCL),both analytically and experimentally.

Apparatus Required :

Sl. No.

Equipments & Components

Range / specification Quantity

1 RPS (0-30) V 2

2 Ammeter (0-10) mA, (0-5) mA, 3,3 each

3 Voltmeter (0-20) V, (0-10) V, (0-5) V1,2,2 respectively

4 Resistor 1K Ω, 2.2K Ω,10K Ω,4.7K Ω,2K Ω One each

5 Bread Board ------------- 1

6 Connecting wires ------------ As required

Theory:

Kirchhoff’s current law (KCL):

KCL states that “the algebraic sum of all the currents at any node in a circuit

equals zero”.

i.e., Sum of all currents entering a node = Sum of all currents leaving a node

In case of AC circuits,

Phasor sum of incoming currents = Phasor sum of outgoing currents.at any

node.

Explanation

Figure -2Let the currents I1, I2 , I3 , I4 flow through the conductors meeting at the

junction ‘o’in figure-2. Taking currents flowing towards junction as positive & that

flowing away from junction as negative.

Applying KCL at node 0.we get



I1-I2-I3+I4=0

Figure -3



Kirchhoff’s voltage law (KVL):

KVL states that “the algebraic sum of all the voltages around any closed loop in

a circuit equals zero”.

i.e., Sum of voltage drops = Sum of voltage rises

In a closed circuit Σ emf + Σ IR =0.

To Determine the sign of EMF Source

To determine the sign of voltage across the Resistor.

If the loop direction & the current direction are the same then the voltage across

the impedance (i.e.,) the voltage drop is taken as negative. If the loop direction & the

current direction are opposite to each other then the voltage across the impedance

(i.e.,) the voltage drop is taken as positive.

Theoretical Calculation:

Refer figure-3 .By applying loop current method ,we get the following Matrix

[ 6.9 ×103 −4.7 ×103 −2.2× 103

−4.7 × 103 16.7 × 103 −10 × 103

−2.2 ×103 −10 × 103 13.2 ×103 ]×[ IXIYIZ ]=[10

150 ]

Ix, Iy, Iz are the currents of the loops1,2 and 3 respectively as shown in the figure.

I1, I2, I3 are the branch currents given in circuit

I1=IX - IY

I2=Iy

I3=Iz

The other branch currents are I, I4 and I5 as marked in figure.



∆ = [ 6.9 ×103 −4.7 ×103 −2.2× 103

−4.7 × 103 16.7 × 103 −10 × 103

−2.2 ×103 −10 × 103 13.2 ×103 ]|∆| = (6.9×103¿|16.7 × 103 −10 ×103

−10 × 103 13.2 ×103|+ (4.7×103¿|−4.7 ×103 −10 ×103

−2.2× 103 13.2× 103|+ ( 2.2×103

)|−4.7 ×103 16.7 ×103

−2.2× 103 −10 ×103| = (6.9×103¿ [120.44×106¿+ (4.7×103¿ [ 84.04×106

] + ( 2.2×103)¿83.74×106¿

= (831.036×109−¿394.988×109−¿184.228×109)

|∆| = (251.82×109)

∆x=[10 −4.7 ×103 −2.2× 103

15 16.7× 103 −10× 103

0 −10× 103 13.2× 103 ]|∆x| = (10) |16.7 × 103 −10 ×103

−10 × 103 13.2 ×103|+¿ (4.7×103¿|15 −10 ×103

0 13.2 ×103|+ ( 2.2×103

)|15 16.7×103

0 −10 ×103| =10 120.44×106

+ 4.7×103 [198×103

] -2.2×103 [-150×103

] =1204.4×106+ 930.6×106+330×106

|∆x| = (2465×106)

∆y =[ 6.9 ×103 10 −2.2× 103

−4.7 × 103 15 −10× 103

−2.2 ×103 0 13.2× 103 ]|∆y| =(6.9 ×103)|15 −10 × 103

0 13.2×103| - (10¿|−4.7 ×103 −10× 103

−2.2× 103 13.2× 103|+ (−2.2 ×103)|−4.7 × 103 15

−2.2 ×103 0 | |∆y|=(6.9 ×103)[198 ×103 ¿−(10 ) [−84.04 ×106 ]−(2.2 ×103)[133 ×103] |∆y| =(1366.2×106)+(840.04×106−¿ (72.6×106) |∆y| =2134.4×106

∆z =[ 6.9 ×103 −4.7 ×103 10−4.7 × 103 16.7 × 103 15−2.2 ×103 −10 × 103 0 ]

|∆z| =6.9 ×103|16.7× 103 15 ×103

−10 ×103 0 |-(4.7 × 103)|−4.7 ×103 15−2.2× 103 0 |

+10|−4.7 ×103 16.7 ×103

−2.2× 103 −10 ×103| |∆z| ¿6.9 ×103[150×103]+4.7×103 [33×103]+10[83.74×106] |∆z| = 1035×106 + 133.1×106 + 837.44×106

|∆z| = 2027.5×106



IX=|∆x| / |∆ | = (2465×106) / (251.82×109) = A=9.78 mAIy=|∆y| /|∆ | = (2134×106) / (251.82×109) = 8.474 × 10−3A=8.474 mAIz=|∆z| /|∆ | = (2027.5×106) / (251.82×109) = 8.051 ×10−3A=8.051 mA

I1= IX - Iy = ( - 8.474× 10−3) =1.31 x10-3A =1.31mA

I2= Iy= 8.474 × 10−3A= 8.474 mAI3= Iz= 8.051 ×10−3A= 8.051mA

I4=Ix-Iz= ( -8.051 ×10−3) = 1.73x10-3A = 1.73 mA

I5=Iy-Iz= (8.474 × 10−3-8.051 ×10−3) = 0.423x10-3A= 0.423 mAFor kirchoff’s voltage laws, the voltage across each branch is

v1 (voltage across resistor 2.2 kohm) = I4 x 2.2 x103= (1.73 x10-3A)( 2.2 x103) = 3.8 V

v2 (voltage across resistor 10kohm)= I5 x 10 x103= (0.423x10-3A)( 10 x103) = 4.23 V

v3 (voltage across resistor 4.7kohm)= I1 x 4.7 x103= (1.31x103 )( 4.7 x103) = 6.157 V

v4 (voltage across resistor 1kohm)= I3 x 1 x103= (8.051 ×10−3A)( 1 x103) = 8.051 V

v5 (voltage across resistor 2.2kohm)= I2 x 2 x103= (8.474 × 10−3A)( 2 x103) = 16.948 V



Figure -4

Figure -5Tabulation branch current:

I (in mA)

I1 (in mA)

I2 (in mA)

I3 (in mA)

I4 (in mA)

I5

(in mA)

Theoretical value

9.781 1.31 8.474 8.051 1.73 0.423

Practical value



Procerure:

Kirchhoff’s current law (KCL):

(1) Connect the components as shown in the figure -5.

(2) Switch on the DC power supply and note down the corresponding ammeter

readings.

(3) Repeat the step 2 for different values in the voltage source.

(4) Finally verify KCL.

Kirchhoff’s voltage law (KVL):

(1) Connect the components as shown in the figure-6.

(2) Switch on the DC power supply and note down the corresponding voltmeter

readings.

(3) Repeat the step 2 for different values in the voltage source.

(4) Finally verify KVL.



Tabulation for node current in KCL:

S.NoName of the

nodeTheoretical value Practical value

1Node P 9.781mA=

(8.051+1.73 )mA I=I3+I4

2Node Q

1.73mA= (0.423+ 1.31)mA I4=I5+I1

3Node R 8.474mA=

(8.051+0.423)mA I2=I3+I5

Figure -6Tabulation for branch voltage:

V1

(in volt)V2

(in volt)V3

(in volt)V4

(in volt)V5

(in volt)

Theoretical value

3.8 4.23 6.157 8.051 16.948

Practical value



Tabulation for loop voltage:

S.NoName of the

loopTheoretical value Practical value

1Loop 1

10v = (3.8 +6.157)v

E1=V1+V3

2Loop 2

15+6.157-4.23-16.948)v = 0

E2+V3-V2-V5=0

3Loop 3

8.051v = (3.8+4.23)v

V4=V1+V2

Results:

Thus (i) Kirchhoff’s Current Law & (ii) Kirchhoff’s Voltage Law are verified.

S.NoName of the

CurrentTheoretical value Practical value

1 I1

2 I2

3 I3



Circuit Diagram:

Figure -1

Thevenin’s equivalent circuit:

Figure -2



Expt.No.: Date:

Verification of Thevenin’s Theorem & Norton’s Theorem

a) Verification of Thevenin’s Theorem

Aim:

To verify Thevenin’s theorem both analytically and experimentally.

Apparatus Required:

Sl. No.Equipments &

ComponentsRange / specification Quantity

1 RPS (0-30) V 2

2 Ammeter (0-10) mA, (0-30) mA Each one

3 Voltmeter (0-20) V 1

4 Resistor

1K Ω, 2.2K Ω,10K Ω,4.7K

Ω,2K Ω Each one

5 Bread Board --------------- 1

6 Connecting wires --------------- As required

Theory:

Theorem Statement:

Thevenin’s theorem states that “any two terminal linear network having a

number of voltage, current sources and resistances can be replaced by a simple

equivalent circuit consisting of a single voltage source in series with a resistance”,

where the value of the voltage source is equal to the open circuit voltage across the two

terminals of the network, and resistance is equal to the equivalent resistance measured

between the terminals with all the energy sources replaced by their internal resistances.

Original Network :

Figure -3



Theoretical Calculation for Thevenins Theorem:

To calculate the Thevenin’s load current:

:

Figure -4

The current I1, I2 and I3 are the three loop currents in figure-4 . The load current IL is

same as the current in loop-3.

i.e IL =I3

Refer figure-4 .By applying loop current method ,we get the following Matrix

[ 4.3 ×103 −3.3× 103 0−3.3 ×103 5.6 × 103 −2.2 ×103

0 −2.2× 103 3.2 ×103 ] [I 1I 2I 3]=[−20

1515]

|∆| =[ 4.3 ×103 −3.3× 103 0−3.3 ×103 5.6 × 103 −2.2 ×103

0 −2.2× 103 3.2 ×103 ]=4.3K| 5.6 ×103 −2.2 ×103

−2.2 ×103 3.2 ×103 |- (-3.3K) |−3.3 × 103 −2.2 ×103

0 3.2 ×103 | +0|−5.6 × 103 −2.2 ×103

−2.2×103 2.2 ×103 | =4.3×103[17.92-4.84]×106+3.3×103[-10.56-0]×106+0

=(4.3×103 13.08×106

)- (3.3×103×[-10.56]×106¿

=56.244×109- 34.848109= 21.396×109



|∆3| = [−4.3 ×103 −3.3 ×103 203.3 ×103 5.6 ×103 −15

0 −2.2 ×103 15 ] =(4.3×103¿| 5.6 ×103 −15

−2.2 ×103 15 |-(-3.3×103)|−3.3× 103 −150 15 |

+20|−3.3 × 103 5.6 ×103

0 −2.2 ×103| =4.3×103 [84×103-33×103]+3.3×103 (-49.5×103-0)+20(7.26×106-0)

=(4.3×103×51×103¿+(3.3×103×−¿49.5×103¿+(20 7.26×106)

=219.3×106-163.35×106+145.2×106

=201.15 ×106

I3= (|∆3| / |∆| )= ((201.15 ×106) / ( 21.396×109)) = 9.4×10−3= 9.4 mA

To calculate the Thevenin’s voltage Vth: :

Figure -5

By loop analysis (matrix method) calculate the two currents from loop-1 and loop-2 as

I1 and I2 respectively.

Refer figure-5 .By applying loop current method, we get the following Matrix

| 4.3× 103 −3.3 ×103

−3.3 × 103 5.6 ×103 | [ I 1I 2]= [ 20

−15]|∆|= |−4.7 ×103 3.3 ×103

−3.3× 103 5.6 ×103|=24.08×106- 10.89×106 =13.19×106

|∆1|= | 20 3.3 ×103

−15 5.6 ×103|=112×103-49.5×103=62.5×103



|∆2| = |−4.7 ×103 20−3.3× 103 −15|= -64.5×103+66×103 =1.5×103

I2=( |∆2| / |∆1|) = (1.5×103 / 13.19×106)= 0.114 ×10−3=11.4mA

Vth= (15+ I2 x 2.2×103)

= (15+ (0.114 ×10−3)x(2.2×103)

= (15+0.251)

= 15.251 Volts

To calculate the Thevenin’s resistance R th:

Figure -6

Rx is the parallel combination of 1k Ω and 3.3k Ω resistors.

Figure -7

Rx=(1 ×103 ×3.3 ×103)/(3.3×103+1×103) =767Ω

Ry is the serise combination of Rx and 100 Ω resistors.

Figure -8

Ry= (767Ω+100Ω) = 867Ω



Rth is the parallel combination of Ry and 2.2k Ω resistors.

Rth=(867Ω // 2.2x103)=((867Ω x2.2x103) / (867Ω +2.2x103))

= 1907400 / 3067 = 621.91Ω



To calculate the I’L:

Figure -9

I’L= Vth / (Rth+RL)=15.251 / (621.91+1000)=15.251 / 1621.91

=9.403 ×10−3A=9.403 mA

Voltage across load is VL

VL =IL x 1x103=9.403 ×10−3 x 1x103= 9.403 volts

To calculate the Ise:

Figure -10

Ise= Vth / Rth =( 15.251v / 621.91 Ω ) =0.0245 Amp =24.5 mA



To measure the Load current IL :

Figure -11

To measure the VL :

Figure -12

To measure the Vth :

Figure -13



Procedure:

General Circuit find load current (IL) and laod Voltage: (VL)

(1) Connect the components as shown in the circuit diagram.

(2) Measure the voltage across the load using a voltmeter or multimeter after

switching on the power supply. Let it be VL.

(3) Measure the current across the load IL by connecting the components as

shown in the circuit diagram.

To find Thevenin’s Voltage: (VTH)


(2) Remove the load resistance and measure the open circuited voltage VTH

across the output terminal.

To find Thevenin’s Resistance: (RTH)


(2) Remove the voltage source and replace it with an internal resistance as

shown.

(3) Using multimeter in resistance mode, measure the resistance across the

output terminal.

Thevenin’s Equivalent Circuit:

(1) Connect the power supply of VTH and resistance of RTH in series as shown in

the circuit diagram.

(2) Connect the load resistance RL and measure VL’ across the load resistance

using a voltmeter after switch on the power supply.

(3) Connect the power supply of VTH and resistance of RTH in series with load

resistor as shown in the circuit diagram and measure the load current I’L.



To measure the Thevenin’s resistance Rth:

Figure -14

To measure the load current IL:

Figure -15

To measure the V’L :

Figure -16



Tabulation 1:

E1 (volts) E2 (volts) VL (volts)VTH

(volts)

RTH

(ohms)

VL’

(volts)

Theoretica

l value20 15 9.403 15.251 621.91 9.403

Practical

value

Tabulation 2:

E1 (volts) E2 (volts) IL (mA) I’L (mA)

Theoretical value 20 15 9.403 9.403

Practical value

Result:

Thus the Thevenin’s Theorem is verified theoretically and practically.



Circuit Diagram:

Figure -1

Norton’s equivalent circuit:

Figure -2



Expt. No: Date

(b) Verification of Norton’s Theorem

Aim:

To verify Norton’s Theorem both analytically and experimentally.

Apparatus Required:

Sl

No

Equipments &

ComponentsRange / specification Quantity

1 RPS (0-30) V 2

2 Ammeter (0-10) mA, (0-30) mA Each one

3 Voltmeter (0-20) V 1

4 Resistor 1K Ω, 2.2K Ω,10K Ω,4.7K Ω, 2K Ω Each one

5 Bread Board ------------------ 1

6 Connecting wires ------------------ As required

Theory:

Theorem Statement

Norton’s theorem states that “any two terminal linear network having a number

of voltage, current sources and resistances can be replaced by an equivalent circuit

consisting of a single current source in parallel with a resistance”. The value of the

current source is the short circuit current between the two terminals of the network, and

resistance is the equivalent resistance measured between the terminals of the network

with all the energy sources replaced by their internal resistances.

Original Network :

Figure -3



Theoretical Calculation for Norton’s Theorem:

To calculate the Ise:

Figure -4

By loop analysis (matrix method) calculate the three currents from loop-1 and loop-2

and loop -3 as I1, I2 and I3 respectively.

[ 4.3 ×103 −3.3× 103 0−3.3 ×103 5.6 × 103 −2.2 ×103

0 −2.2× 103 2.2 ×103 ] [I 1I 2I 3]=[−20

1515]

|∆| =[ 4.3 ×103 −3.3× 103 0−3.3 ×103 5.6 × 103 −2.2 ×103

0 −2.2× 103 2.2 ×103 ]=(4.3×103| 5.6 × 103 −2.2 ×103

−2.2 ×103 2.2 ×103 |-(-3.3×103)|−3.3 × 103 −2.2 ×103

0 2.2 ×103 | +0x

|−3.3 × 103 5.6 ×103

0 −2.2 ×103|) =(4.3×103 [12.32-4.84]×106 + 3.3×103 [-7.26-0]×106+ 0)

=((4.3×103 )(7.48×106 ) – (3.3×103¿¿7.26×106))

|∆| =(32.164×109- 23.958×109¿= 8.206×109

|∆3| =[4.3 ×103 3.3 ×103 203.3 ×103 5.6 ×103 −15 × 103

0 −2.2 ×103 −15 × 103] EC2155/ Circuits and Devices Lab Manual cum Observation


=4.3×103| 5.6 × 103 −15−2.2 ×103 15 |- (-3.3×103)|−3.3× 103 −15

0 15 | +20|−3.3 × 103 5.6 ×103

0 −2.2 ×103| =4.3×103 [84×103-33×103] + 3.3×103 (-49.5×103- 0) + 20(7.26×106-0)

=(4.3×103×51×103 ) + ( 3.3×103×49.5×103) + (20 x 7.26×106)

=(219.3×106- 163.35×106 + 145.2×106)

=201.15×106

Ise=I3= |∆3| /|∆| = (201.15×106 / 8.206×109 ) = 0.0245 A=24.5mA

To calculate the Thevenin’s resistance R th:

Figure -5

Rx is the parallel combination of 1k Ω and 3.3k Ω resistors.

Figure -6

Rx=(1 ×103 ×3.3 ×103)/(3.3×103+1×103) =767Ω

Ry is the serise combination of Rx and 100 Ω resistors.



Figure -7

Ry= (767Ω+100Ω) = 867Ω

Rth is the parallel combination of Ry and 2.2k Ω resistors.

Rth=(867Ω//2.2x103)=((867Ω x2.2x103) / (867Ω +2.2x103)) = 1907400 /

3067

= 621.91Ω

To calculate the I’L:

Figure -8

After calculating Ise & Rth, I’L can be calculated by applying current division technique.

I’L=Ise x (Rth / (Rth+RL) ) = 0.0245 x (621.91 / (621.91+1000)) =9.394x10-3A

=9.394 mA= 9.4 mA

Figure -9

I’L can also be calculated from the above circuit i.e.figure-9 by converting the current

source in parallel with resistance Rth as equivalent voltage source in series with Rth.



Veq= Ise x Rth =0.0245 x 621.91Ω= 15.236 volts

I’L= Veq / (Rth+RL) =15.236/(621.91+1000)=9.394 x10 -3A=9.394 mA= 9.4 mA



Procedure :

General Circuit find load current: (IL)


(2) Measure the current through the load using an ammeter or multimeter after

switch on the power supply. Let it be IL.

To find Norton’s Current: (Ise)


(2) Remove the load resistance and short circuit the output terminal. Then

measure the current through the short circuited terminals.

To find Norton’s Resistance: (Rth)


(2) Remove the voltage source and replace it with an internal resistance as

shown.

(3) Using multimeter in resistance mode, measure the resistance across the

output terminal.

Norton’s equivalent Circuit:

(1) Draw the short circuit current source Ise in parallel with Rth as shown in the

circuit diagram.

(2) Draw the equivalent circuit by replacing the current source Ise in parallel

with Rth by a voltage source such that Veq = (Ise x Rth )volts.

(3) Then connect the circuit as shown in figure 9 and measure the load current

IL’ through the load resistor RL. This must be equal to IL.



To measure the load current IL:

Figure -9

To measure the short circuit load current Ise:

Figure -10

To measure the Rth:

Figure -11



To measure the load current I’L:

Figure -12

Figure -13

Tabulation:

E1

(volts)

E2

(volts)

IL

(mA)

Ise

(mA)Rth (Ω)

Veq = Ise . Rth

(volts)

IL’

(mA)

Theoretical

value20 15 9.4 9.4 621.91 15.236 9.4

Practical

value

Result:

Thus Norton’s Theorem is verified theoretically and practically.



Circuit diagram:



Expt. No.: Date:

Verification of Super Position Theorem

Aim :

To verify superposition theorem practically & theoretically for the given DC

circuit.

Apparatus Required:

S.No. Components Range Quantity

1. Regulated Power supply(RPS) (0-30)V 2

2. Ammeter (0-30)mA 1

3. Multimeter --- 1

4. Resistors 560Ω 3

5. Bread board --- 1

6. Connecting wires Few

Theory:

Superposition Theorem:

In a network of linear resistances, containing more than one source, the

resultant current flowing at any one point is the algebraic sum of currents that would

flow at that point, if each source is considered separately, and all the other sources are

replaced by their equivalent internal resistance .

This last step is carried out by short circuiting all sources of constant voltage & open-

circuiting all sources of constant current.

Procedure:

1. Make connections as per the (fig b) circuit diagram.

2. Vary the RPS2 and set an input voltage of 10 V .

3. Note down the ammeter reading IL1 in tabular column 1.

4. Make connections as per the (fig c) circuit diagram.

5. Vary the RPS1 and set an input voltage of 10 V.

6. Note down the ammeter reading IL2 in tabular column 2.

7. Make connections as per the (fig a) circuit diagram.

8. Find the total load current IL=IL1+IL2

9. Verify the same using theoretical calculation



Theoretical Calculation for Super position theorem:

Circuit diagram:

Step 1: Short circuit V2. Apply V1=20V

25 +15 I1 20

=

-15 20 I2 0

I1 =1.45 A; I2 =1.09 A; IT1 =0.36 A


RPS (0-30V) V1

-

+

5Ω 10Ω

15Ω

I1

I2


Step 2: Short circuit V1. Apply V2=15V

25 +15 I1 0

=

-15 +20 I2 -15

I1 =-0.81 A ; I2 =-1.363 A ; IT2 =0.54 A

Step 3: V1 & V2 are active. Apply V1=20V & V2=15V

25 +15 I1 20

=

-15 +25 I2 -15

I1 = 0.63 A; I2 = -0.27 A ; IT = 0.909 A

Thus IT = IT1 + IT2 . Super Position Theorem is proved.


I2I1

I2I1


Circuit Diagram for Super Position Theorem – Practical Analysis:

Step 1: Both voltage sources are active. I L =

……………….

Fig (a)

Step 2: RPS2 alone is active. IL2=……………

Fig (b)

Step 3: RPS1 alone is active. IL1=……………

Fig (c)


RPS1

(10V) RPS2

(10V)

+ +

+

-

- -

+

- +

-

10 Ω 5Ω

15Ω

A (0-10mA) MC

10 Ω 5Ω

15Ω

(0-10mA) MC

RPS2

(10V)

A

(0-10mA)

RPS1

(10V)

10 Ω 5Ω

15Ω

A

+

-

+

-


Tabular Column 1: To measure IT1 & IL1 (For fig.b)

Tabular Column 2

To measure IT2 & IL2 (for fig.c)

Tabular column 3

To measure IT & IL (For fig. a)

Result: Thus superposition theorem is verified practically &theoretically.


Voltage

(volts)

Theoretical

Current

IT2(A)

Practical

Current IL2

(A)

Voltage

(volts)

Theoretical

Current

IT1(A)

Practical

Current IL1

(A)

RPS1

Voltage

(V)

RPS2

Voltage

(V)

Theoretical

Current IT

(A)

Practical

Current IL

(A)

IL = IL1+IL2

(A)

IT= IT1+IT2

(A)


Circuit Diagram Maximum Power Transfer Theorem:

Circuit to find VL:

Model Graph:


1KΩ

1KΩ DRB (RL )RPS (0-30V)

V

1KΩ

1KΩ

DRBRL

RPS (0-30V) VS (0-30V)MC

+

-

+

-

Load resistance, RL in Ω

Pmax

RL= RTH

Pow

er ,P

(m

W)


Expt. No.: Date:

Verification of Maximum power Transfer Theorem and Reciprocity

Theorem

(a).Verification of Maximum Power Transfer Theorem

Aim:

To measure the power absorbed in a load and to verify that the power

absorbed in a load is maximum only when load resistance is equal to the source

resistance.

Apparatus Required:

SL. No Name of the apparatus Range/Rating Quantity

1 Voltmeter (0-30V) MC 1

2 Resistance 1kΩ 2

3 DRB - 1

4 RPS(D.C Supply) (0-30V) 1

Theory:

The maximum power transfer theorem states that “A load will

receive maximum power from a linear bilateral DC network when its total

resistive value is exactly equal to the Thevenin resistance of the network as seen

by load”.

In a simpler form the circuit may contain a voltage source VS having

internal resistance RS and connected across a load RL. The maximum power

transfer theorem tells us that the load should be equal in magnitude to the source

resistance for maximum power to be absorbed by the load.

Procedure:

1. Make connection as per the circuit diagram.

2. Select atleast five resistances (RL), two of them having values internal

resistance, two having values higher internal resistance and one having

value equal to internal resistance.

3. Change the value of RL one by one and measure the corresponding VL.

Calculate the power PL by the formula PL = VL2/ R ;and enter into the

table (2).

4. Plot a graph between RL and PL and find the RL corresponding to

maximum power transfer.



5. Verify the measured values of RL at maximum power transfer to be as

same as calculated and also verify graphically.

Tabular Column:


Sl. No.

Load Resistance, RL (KΩ)

Output Voltage, V0

(volts)Power, P

(mW)

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15


Model Calculation:

Circuit Diagram:

Step 1: To find VTH

Open the circuit the load terminal RL.

By voltage divider rule:

REQ = 0.5Ω & VTH= VSR1 / (R1+R2) = 15V

Step 2: To find RTH:

Open circuit the load terminal RL.

Open circuit the current source and short circuit the voltage source.

RTH = R1 R2 / (R1 + R2 ) = 0.5Ω


Vs = 15V

1kΩ

1kΩ DRB RL

R1=1kΩ

R2=1kΩ

Vs= 15V VTH

R1=1kΩR2=1kΩ

RTH


Step 3: Thevenin’s equivalent circuit for maximum power delivered.

I = VTH / (R+REQ) = 15 / (0.5 + 0.5) = 15 A

Max power delivered at RL = I2RL = 112.5 W


Vs= 15V

RTH=0.5Ω

RL = RTH

I


Result:

Thus maximum power transfer theorem is verified practically and theoretically.



Reciprocity Theorem – Practical Analysis

Circuit Diagram:

Step 1: To measure the current at branch 3-4.

Step 2: To measure the current at branch 1-2.


RPS (0-30V) VS=30V

12Ω 2Ω

6Ω

4Ω

RPS (0-30V) VS=30V

12Ω 2Ω

4Ω

6Ω

(0-10mA) MC

+

-

+

-

+

-

I1

1

2

3

4

1

2

3

4

-RPS (0-30V) VS=30V

(0-10mA) MC

+

-

+

12Ω 2Ω

6Ω

4Ω

I2

1

4

3

2


Expt. No.: Date:

(b) Verification of Reciprocity Theorem

Aim:

To verify the reciprocity theorem for the given circuit, practically and

theoretically.

Apparatus Required:

S.No Name of the apparatus Range/Rating Quantity


2. RPS (Power Supply) (0-30)V 1

3. Resistor 12Ω, 2Ω ,4Ω,6Ω 1 each

4. Connecting wires - few

Theory:

Reciprocity Theorem states that “in any passive linear bilateral network, if the

single voltage source VS in branch x produces the current response IY in branch y, then

the removal of the voltage source from branch x and its insertion in branch y will

produce the current IY in branch x.”

In simple terms, “interchange of an ideal voltage source and an ideal ammeter in

any passive, linear, bilateral circuit will not change the ammeter reading”.

Note: The reciprocity theorem is thus applicable only to single source network. It is,

therefore, not a theorem employed in the analysis of multi-source network. In other

words, the location of the voltage source and the resulting current may be interchanged

without a change in current.

Procedure:

1. Make connection as per the circuit diagram.

2. Calculate the values of I1, by connecting the ammeter at branch 3-4 and

tabulate.

3. Now connect the power supply at branch 3-4 and measure the current in the

ammeter connected at branch 1-2.tabulate the value as I2.

4. Compare the theoretical value and tabulated value of current to be the same

to verify the reciprocity theorem.



Tabulation:Supply

voltage,VS (volts)

Current at branch 3-4,I1

(mA)

Current at branch 1-2, I2

(mA)

Model Calculation:

Step 1: To measure current I1 at branch 3-4

18 6 I2 30=

-6 12 I1 0

I1 = 0.71 A

Step 2: To measure current I2 at branch 1-2


12Ω 2Ω

6Ω

4Ω

RPS (0-30V) VS =30 v

I1I2

1

2

3

4

12Ω 2Ω1 3


18 6 I2 0

-6 12 I1 = -30

I2 = 0.71A

I1 = I2 . Reciprocity Theorem is verified.


6Ω

4Ω

RPS (0-30V) VS=30 v

2 4


Result:

Thus the reciprocity theorem is verified theoretically and practically.



Circuit Diagram:

Parallel Resonance Circuit:

Series Resonance Circuit:



Expt. No.:

Date:

Frequency Response of Series and Parallel Resonance Circuit

Aim:

To obtain the resonance frequency and bandwidth of series and parallel

resonance circuits.

Apparatus Required:

S.NoName of the

apparatusRange Quantity

1 RPS Dual (0-30) V 1

2 Ammeter (0-30 ) mA 1

3Function

Generator

(0-3)MHz 1

4 Resistors 10, 5 1

5 Capacitor 0.1µF 1

6 DIB - 1

7 Breadboard - 1

8Connecting

wires

- Few

Theory:

At resonance XL = XC and impedance Z = R. Where R is the resistance of the

coil. The R and XL of the coil determines the quality of the circuit which is given by

Q = XL / RL

Point f1and f2 are located at 70.7 percent of the maximum current for the series

circuit. They are called as half power point and the frequency difference between f 1

(lower cut off frequency) and f2 (upper cut off frequency) is called the band width.



Model Graph:

Series Resonance:

Parallel Resonance:


Imax / √ 2

Imax

Imin

Imin . √ 2

frequency

Frequency

current

Current


The formula for calculating the band width is given by

BW = f2 – f1 .

Band width is related to the quality factor(Q). Its given by

BW = fr / Q

Resonance frequency of the series resonant circuit is calculated using the formula

fr = 1 / 2π √ (LC).

Procedure:

1. Connections are given as per the circuit diagram.

2. The resonance frequency is obtained by keeping the value of L,C,R constant

3. The resonance frequency is obtained using the formula fr = 1 / 2π √ (LC).

4. Varying the value of frequency and note down the corresponding current flow in

the circuit.

5. Graph is plotted between frequency (x axis) and current (y axis).

6. Same procedure is to be followed for both series and parallel circuits.



Tabular Column:

Series Resonance: Parallel Resonance:


Sl. NoFrequency

(Hz)Current (mA)

01

02

03

04

05

06

07

08

09

10

11

12

13

Sl. NoFrequency

(Hz)Current (mA)

01

02

03

04

05

06

07

08

09

10

11

12

13


Model Calculation:

Parallel Resonance:

R= 10Ω, L=1 H C= 1μF

Admittance of the parallel resonance circuit is given by

( where G is conductance and B is susceptance)

At resonance B=0

=0

= 159Hz

= 100

Bandwidth = = 10rad/sec

= 79.6Hz

= 160.5HzEC2155/ Circuits and Devices Lab Manual cum Observation


Bandwidth = =80.9 Hz

Series Resonance:

R= 5Ω, L=40 m H, C= 1μF

Impedance of the series resonance circuit is given by

At resonance:

:

Therefore = (where ω = 2πf)

Q factor = = 40

Bandwidth = = 19.89Hz



= 796Hz

= 786Hz

= 806 Hz



RESULT:

Thus the resonant frequency and band width of series and parallel resonance

circuits was obtained and the graph is plotted.



Circuit Diagram:

PN-Junction Diode:

Forward Bias:

Reverse Bias:

Symbol:



Expt. No.: Date:

Characteristics of PN-Junction Diode

Aim:

To plot the forward and reverse characteristics of a PN diode and to calculate

cut-in voltage, forward resistance and reverse resistance.

Apparatus Required:

S.

NoItem Range Qty

1. Diode 1N4007 1

2. Resistor 1KΩ 1

3. Voltmeter (0-1V) 1

4. Ammeter (0-30mA), (0-500µA) 1

5. RPS (0-30)V 1

Theory:

A diode is a PN junction formed by a layer of a P type and layer of N type

semiconductors. Once formed the free electrons in the N region diffuse across the

junction and combine with holes in P region and so a depletion Layer is developed. The

depletion layer consists of ions, which acts like a barrier for diffuse of charged beyond

a certain limit. The difference of potential across the depletion layer is called the barrier

potential. At 2.5 degree the barrier potential approximately equal to 0.7v for Silicon

diode and 0.3V for Germanium diode. When the junction is forward biased, the

majority carrier acquired sufficient energy to overcome the barrier and the diode

conducts. When the junction is Reverse Biased the depletion layer widens and the

barrier potential increases. Hence the majority carrier cannot cross the junction and the

diode does not conduct. But there will be a leakage current due to minority carrier.



Model Graph:

PN Diode V-I Characteristics Curve

Tabular Column:Forward Bias:

S. No. Forward Voltage (Vf) Forward Current (If)

01

02

03

04

05

06

07

08

09

10



Procedure:

Forward Bias:

1. The connections are made as per the circuit diagram.

2. The positive terminal of power supply is connected to anode of the diode

and negative terminal to cathode of the diode.

3. Forward voltage Vf across the diode is increased in small steps and the

forward current is noted.

4. The readings are tabulated and the graph is drawn for Vf versus If.

5. The forward resistance is found from the graph using the formula

rf = ΔVf/ ΔIf. Ω

Reverse Bias:

1. The connection as made as per the circuit diagram.

2. For reverse bias the positive terminal of the power supply is connected

to cathode and negative terminal to anode of the diode.

3. The power supply is switched ON, the reverse bias voltage V f is

increased in steps and reverse current Ir is noted in each steps.

4. The readings are tabulated and the graph is drawn for Vr Versus Ir .

5. The reverse characteristics are approximately a straight line, inverse of

the slope give the reverse resistance.

6. The reverse resistance is found from the graph using the formula

rr = ΔVr/ ΔIr. Ω



Reverse Bias:

S. No. Forward Voltage (Vr) Forward Current (Ir)

01

02

03

04

05

06

07

08

09

10

11



Result:

Thus the characteristic of PN-Junction diode was drawn and the following

parameters are calculated.

Forward resistance : Ω

Reverse resistance : Ω

Cut-in Voltage : V



Circuit Diagram:

Zener Diode:

Forward Bias:

Reverse Bias:

Symbol:



Expt. No.: DATE:

Characteristics of Zener Diode

Aim:

To plot the VI Characteristics of a Zener diode and to determine the zener

breakdown voltage and Zener break down current

Apparatus Required:

S. No Item Range Qty

1. Zener Diode Z 6.8 V 1

2. Resistor 1KΩ 1

3. Voltmeter(0-10V),

(0-1V)1

4. Ammeter (0-50mA) 1

5. RPS (0-30)V 1

Theory:

Zener doide is a special diode with increased amounts of doping. This is to

compensate for the damage that occurs in the case of a PN junction diode when the

reverse bias exceeds the breakdown voltage and thereby current increases at a rapid

rate.

Applying a positive potential to the anode and a negative potential to the

cathode of the zener diode establishes a forward bias condition. The forward

characteristic of the zener diode is same as that of a pn junction diode i.e. as the applied

potential increases. The current increases exponentially. Applying a negative potential

to the anode and positive potential to the cathode reverse biases the zener diode. As the

reverse bias increases the current increases rapidly in a direction opposite to that of the

positive voltage region. Thus under reverse bias condition breakdown occurs.



Modal Graph

Zener Diode V-I Characteristics Curve

Tabular Column:

Forward Bias:

S. No. Forward Voltage (Vf) Forward Current (If)

01

02

03

04

05

06

07

08

09

10



Procedure:

Forward Bias:

1. The connections are made as per the circuit diagram.

2. The positive terminal of power supply is connected to anode of the diode

and negative terminal to cathode of the diode.

3. Forward voltage Vf across the diode is increased in small steps and the

forward current is noted.

4. The reading is tabulated.

5. A graphs is drawn between Vf and If.

Reverse Bias:

1. The connection as made as per the circuit diagram for reverse bias

2. The positive terminal of the power supply is connected to cathode and

negative terminal to anode of the diode.

3. The power supply is switched ON

4. The reverse bias voltage Vf is increased in steps and reverse current Ir is

noted in each steps.

5. The readings are tabulated.

6. A graph is drawn Vr and Ir .The reverse characteristics is approximately as

straight line, inverse of the slope give the reverse resistance



Reverse Bias:

S. No. Forward Voltage (Vr) Forward Current (Ir)

01

02

03

04

05

06

07

08

09

10

11



Result:

Thus the characteristics of Zener diode were drawn and the following

parameters are determined.

Zener Breakdown Voltage: V

Zener Breakdown Current: mA



Pin Diagram:

Top view of BC 107

Circuit Diagram:

Model Characteristics Curve:

(a) Input Curve



Expt. No.: DATE:

C h a r a c t e r i s t i c s of Common Emitter C o nfi g u r a t i on U s i n g B JT

A im :

To determine the input and output characteristics of Common Emitter (CE)

configuration and Calculate the h-parameter values from the input and output

characteristic curves.

A p p a r a t us R eq u i r e d:

S. No. Name Range Qty

1 RPS (0-30)V 2

2Ammeter

(0–10)mA 1

(0 – 250) µA 1

3Voltmeter

(0–30)V 1

(0–1)V 1

4 Transistor BC 107 1

5 Resistor 1kΩ 2

6 Bread Board - 1

7 ConnectingWires -As per

required

numberReqd

Th eo r y :

Bipolar Junction transistor (BJT) was Developed by Dr.Shockley in bell

laboratories in the year 1951. BJT is a three terminal two – junction semiconductor

device in which the conduction is due to both the charge carrier. Hence it is a

bipolar device. In BJT the output current, output voltage, power are

controlled by its input current ,so the device is called as current

controlled device.

Cut in voltage for Si transistor = 0.7v

Cut in voltage for Ge transistor = 0.3v

The application of a suitable DC voltage across

transistor terminals is called biasing. There are three different ways of

biasing a transistor, which are known as modes of transistor operation.



(b) Output Curve

Ta b u l a r c o l u mn:

I n p ut c h a r a c t e r i s t i c s :


Sl. No VCE = 1V VCE = 2V

VBE (volts) IB ( mA) VBE ( volts) IB ( mA)

01

02

03

04

05

06

07

08

09

10


Junction bias Condition:

S.no Region Emitter Base Junction Collector Base Junction

1 Active Forward Bias Reverse Bias

2 Saturation Forward Bias Forward Bias

3 Cut off Reverse Bias Reverse Bias

In CE configuration, the Emitter terminal is connected

as common terminal between the input and output circuit.

P r o c e dur e :

I n p ut C h a ract e r is t i c s :

These Curves give the relationship between the Base current (IB) and Base to

Emitter voltage (VBE) for a Constant Collector to Emitter voltage (VCE).

1. Connections are made as per the circuit diagram.

2. Adjust the Collector to Emitter voltage (VCE) to 1 volt. Then increase Base to

Emitter voltage (VBE) in small suitable steps and record the corresponding

values of Base current (IB) at each step.

3. Plot a graph with Base to Emitter voltage (VBE) along X-axis and the Base

current (IB) along y-axis. We shall obtain a curve marked VCE = 1V as shown

in fig.

4. A Similar procedure may be used to obtain Characteristics at different values

of Collector to Emitter voltage i.e., VCE = 2V,3V etc.

O ut p ut c h a r a ct e r is t i c s :

These Curves give the relationship between the Collector current (IC) and

Collector to Emitter voltage (VCE) for a Constant Base Current (IB).

1. Adjust the Base current (IB) to 20µA value. Then increase the Collector to

Emitter voltage (VCE) in number of steps and record the corresponding values

of Collector current (IC) at each step.

2. Plot a graph with Collector to Emitter voltage (VCE) along X-axis and the

Collector current (IC) along y-axis. We shall obtain a curve marked IB = 20µA

as shown in fig.


of Base current (IB) at 40µA,60µA etc.





Sl. NoIB = 20µA IB = 40µA

VCE (volts) IC ( mA) VCE (volts) IC ( mA)

01

02

03

04

05

06

07

08

09

10

11


Graphical Determination of h-parameters for CE:

1. Input impedance hie = Δ VBE / Δ IB ( for a constant VCE )

2. Reverse Voltage gain hre = Δ VBE / Δ VCE ( for a constant IB )

3. Forward Current gain hfe = Δ IC / Δ IB ( for a constant VCE )

4. Output Admittance hoe = Δ IC / Δ VCE ( for a constant IB )

RESULT:

Thus t h e input and output characteristics of Common Emitter (CE)

configuration was plotted and the following h-parameter values are determined from

the input and output characteristic curves.

Input impedance hie =

Reverse Voltage gain hre =

Forward Current gain hfe =

Output Admittance hoe =



Pin Diagram:

Top view of BC 107

Circuit Diagram:

Model Characteristics Curve:

(a) Input Curve



Expt. No.:

Date:

C h a r a c t e r i s t i c s of Common Base C o nfi g u r a t i on U s i n g B JT

A im :

To determine the input and output characteristics of Common Base (CB)

configuration and Calculate the h-parameter values from the input and output

characteristic curves.


S.No. Name Range Qty

1 RPS (0-30)V 2

2Ammeter

(0–30)mA 1

(0 – 10) mA 1

3Voltmeter

(0–30)V 1

(0–1)V 1

4 Transistor BC 107 1

5 Resistor 1kΩ 2

6 Bread Board - 1

7 ConnectingWires -As per

required

numberReqd

Th eo r y :

Bipolar Junction transistor (BJT) was Developed by Dr.Shockley in bell

laboratories in the year 1951. BJT is a three terminal two – junction semiconductor

device in which the conduction is due to both the charge carrier. Hence it is a

bipolar device. In BJT the output current, output voltage, power are

controlled by its input current ,so the device is called as current

controlled device.

Cut in voltage for Si transistor = 0.7v

Cut in voltage for Ge transistor = 0.3v

The application of a suitable DC voltage across transistor terminals is

called biasing. There are three different ways of biasing a transistor,

which are known as modes of transistor operation.



(b) Output Curve

Ta b u l a r c o l u mn:

I n p ut c h a r a c t e r i s t i c s :


Sl. No VCB = 1V VCB = 5V

VBE ( volts) IE ( mA) VBE ( volts) IE ( mA)

01

02

03

04

05

06

07

08

09

10


Junction bias Condition:

S.no Region Emitter Base Junction Collector Base Junction

1 Active Forward Bias Reverse Bias

2 Saturation Forward Bias Forward Bias

3 Cut off Reverse Bias Reverse Bias

In CB configuration, the Base terminal is connected as

common terminal between the input and output circuit.

P r o c e dur e :

I n p ut C h a ract e r is t i c s :

These Curves give the relationship between the Emitter current (IE) and Base to

Emitter voltage (VBE) for a Constant Collector to base voltage (VCB).


2. Adjust the Collector to Base voltage (VCB) to 1 volt. Then increase Base to

Emitter voltage (VBE) in small suitable steps and record the corresponding

values of Emitter current (IE) at each step.

3. Plot a graph with Base to Emitter voltage (VBE) along X-axis and the

Emitter current (IE) along y-axis. We shall obtain a curve marked VCB =

1V as shown in fig.

4. A Similar procedure may be used to obtain Characteristics at different

values of Collector to base voltage i.e., VCB = 5V,10V etc.


These Curves give the relationship between the Collector current (IC) and

Collector to base voltage (VCB) for a Constant Emitter Current (IE).

1. Adjust the Emitter current (IE) to 2 mA value. Then increase the Collector to

base voltage (VCB) in number of steps and record the corresponding values of

Collector current (IC) at each step.

2. Plot a graph with Collector to base voltage (VCB) along X-axis and the

Collector current (IC) along y-axis. We shall obtain a curve marked IE = 2mA as

shown in fig.


of Emitter current (IE) at 4mA,6mA etc.





Sl. No IE = 2mA IE= 4mA

VCB ( volts) IC ( mA) VCB ( volts) IC ( mA)

01

02

03

04

05

06

07

08

09

10


Graphical Determination of h-parameters for CB:

1. Input impedance hib = Δ VBE / Δ IE ( for a constant VCB )

2. Reverse Voltage gain hrb = Δ VBE / Δ VCB ( for a constant IE )

3. Forward Current gain hfb = Δ IC / Δ IE ( for a constant VCB )

4. Output Admittance hob = Δ IC / Δ VCB ( for a constant IE )

R es ult:

Thus the input and output characteristics of Common Emitter (CB)

configuration was plotted and the following h-parameter values are determined from

the input and output characteristic curves.

Input impedance hib =

Reverse Voltage gain hrb =

Forward Current gain hfb =

Output Admittance hob =



Pi n D i a g r a m :

Top Vie w O f 2 N 264 6 :

C i rcu i t D i a g r a m :

Procedure:

Model Graph:



Expt. No.: Date:

C h a r a c t e r is t i cs O f UJT

Aim:

To Plot the characteristics of UJT & determine its intrinsic standoff

ratio.

Apparatus Required:

Theory:

UJT (Double base diode) consists of a bar of lightly doped n-type silicon with

a small piece of heavily doped P type material joined to one side. It has got three

terminals. They are Emitter (E), Base1 (B1), Base2 (B2).Since the silicon bar is

lightly doped, and it has a high resistance & can be represented as two resistors,

rB1& rB2. When VB1B2 = 0, a small increase in VE forward biases the emitter

junction. The resultant plot of VE & IE is simply the characteristics of forward

biased diode with resistance. Increasing VEB1 reduces the emitter junction reverse

bias. When VEB1 = VrB1 there is no forward or reverse bias. & IE= 0. Increasing

VEB1 beyond this point begins to forward bias the emitter junction. At the peak

point, a small forward emitter current is flowing. This current is termed as peak

current (IP). Until this point UJT is said to be operating in cutoff region. When IE

increases beyond peak current the device enters the negative resistance region.

In which the resistance rB1 falls rapidly & VE falls to the valley voltage. Vv. At this


S. No. Name Type & Range Qty

1. R.P.S (0-30)V 2


3. Voltmeter (0–10)V 2

4. UJT 2N2646 1

5. Resistor 1KΩ 2

6. Bread Board 1

7. Connecting Wires few


point IE= Iv. A further increase of IE c a u s e s the device to enter the saturation

region.



Tabular Column:


Sl No

VBB = 5V VBB = 10V

VEB1(V) IE(mA) VEB1(V) IE(mA)

01

02

03

04

05

06

07

08

09

10

11

12


Determination of I nt r i n sic Standoff Ratio:

We know VP = η.VBB + VD

Where

VP = Peak point voltage (To be determined from the graph for constant VBB )

VD= 0.7 V (Voltage across the diode)

VBB = Inter base voltage

η = Intrinsic Standoff Ratio (Whose values lies between 0.5 to 0.8)

R es ult:

Thus the characteristics of given UJT were drawn and its Intrinsic

Standoff Ratio was founded.

Intrinsic Standoff Ratio η =



Pin diagram:

Symbol:

Circuit Diagram of SCR:



Expt. No.: Date:

C h a r a c t e r is t i cs O f Si l i c o n C o n t r o ll e d R e ct i f ie r

A i m:

To draw the V–I characteristics of the given SCR & to determine the gate current for

different anode voltage


Sl. No Name Type & Range Quantity

1. RPS (0-30) V 2

2. Ammeter(0-10mA),

(0-100µA)

1

3. Voltmeter (0-30v) 1

4. SCR C106 1

5. Bread board - 1

6. Resistors 10KΩ, 33KΩ 1

7. Connecting Wires - 1 set

Theory:

The SCR consists of four layers of semi conductor material alternatively P type and N

type .It can be brought of as an ordinary rectifier with a control element .The control element

is called Gate. The gate current determines the anode to cathode voltage at which the device

starts to conduct. The term ON & OFF is used to represent the conduction and blocking mode

of SCR respectively. Once switched ON the gate has no further control. To switch the SCR

the anode current has to be reduced below a certain level called Holding Current. The SCR

can also be triggered ON with the gate open circuited with the anode to cathode voltage made

large enough .In conduction state the SCR behaves as an ordinary diode. The anode to

cathode voltage at which the SCR conducts is called Break over Voltage or Forward

Blocking Voltage.

F o r w a rd C h a r a c t e r is t i c s :

When anode is positive w.r.t cathode, the curve between V-I is called forward

characteristic. If the supply voltage is increased from zero, a point is reached when SCR



M o d e l G r a p h:



starts conducting. Under this condition, the voltage across SCR suddenly drops and most of the voltage appears across the load resistance RL. If proper gate current is made to flow,

SCR can close at much smaller supply voltage.

R eve r s e C h a r a c t e r is t i c s :

When the anode is made negative w.r.t to cathode, the curve between

V& I is called reverse characteristics. If the reverse voltage is increased, avalanche

breakdown occurs and the SCR starts conducting heavily in reverse direction. It is similar to

the ordinary PN junction diode.

Procedure:

1. The connections are made as per circuit diagram.

2. The switch is kept open.

3. The anode supply is switched ON and the forward voltage is set to some

desired, value.(Eg 20 V )

4. There is no indication of current in the ammeter and the SCR is in OFF state.

5. Now the Gate supply is switched ON and the SPST switch is closed.

6. The gate bias voltage is increased slowly.

7. At some value of gate current the SCR will be triggering ON and it is

indicated by the ammeter in the anode circuit.

8. Also the voltage across the SCR will suddenly fall to around 0.7 V. This value

of gate current required to trigger the SCR is noted.

9. Now with SCR in ON state the gate terminal is made open by opening the

SPST Switch The anode current is slowly reduced by reducing the supply

voltage. At some value of anode current the SCR is turned OFF.

10. This is indicated by a sudden rise in the voltmeter reading and the Ammeter

reading will suddenly become zero.

11. The anode current below which SCR turns OFF is the HOLDING CURRENT

and is noted.

12. The SCR is turned ON once again and the anode current is reduced to the

Holding level.

13. The anode current is varied from holding current to 10 mA and in each step

the forward voltage drop across SCR is noted.

14. The readings are tabulated and the experiment is repeated with different

forward break down voltage.



Tabulation for SCR:

Sl. No.

IG = µA

VAK(V) IA(mA)

01

02

03

04

05

06

07

08

09

10

11



15. As Break over voltage is increased, the gate current required to trigger the

SCR will decrease.

16. To determine the leakage current in the blocking state the connections are

made as per circuit diagram.

17. The power supply is Switched ON and the anode voltage is increased in steps.

The anode current is noted in each step and tabulated.

18. The graph is plotted between forward voltage and forward current. The break

over voltage and holding current are marked on the graph

Result:

Thus the given SCR characteristics were drawn and the following parameters are

measured.

Holding Current (IH) = mA.

Break over Voltage (VBO) = V.

Holding Voltage (VH) = V.



Pin Diagram:

Circuit Diagram:

Model Graph:

Drain Characteristics:



Expt. No.: Date:

Characteristics of Junction Field Effect Transistor (JFET)

Aim :

To plot the transistor characteristics of JFET (Junction Field Effect Transistor) & to

find drain resistance, transconductance & amplification factor

Apparatus Required:

S. No Component Range Qty

1. JFET FET BFW10 1

2. Resistor 1KΩ 2

3. RPS Dual (0-30)V 2

4. Voltmeters (0-10)V, (0-30)V 1

5. Ammeters (0-30)mA 1

6. Bread Board -- 1

7. Connecting Wires --As Per

Requirement

Theory:


In BJT, the relationship between an output parameter Ic and an input parameter IB is

given by a constant _, the relationship in JFET between an output parameter, Id, and an input

parameter, Vgs, is more complex. In the saturation region, there exists a square-law transfer

relationship.

Transconductance Characteristics:

In the transfer characteristics of a two port network, the input parameter is changed

and its effect on the output parameter is observed. Similarly JFET can be treated as a two port

nonlinear network. The transfer characteristics wherein the input parameter is the voltage

across gate and source, and the output parameter is the drain current are called the trans-

conductance characteristics.



Transfer characteristics:



Sl. No.Vgs = (V) Vgs = (V)

VDS (V) ID (mA) VDS (V) ID (mA)

01

02

03

04

05

06

07

08

09

10


Procedure:

Drain Characteristics (rd):


2. VGS is kept constant (Say -1V), VDS is varied insteps of 1V and the corresponding ID

values are tabulated.

3. The above procedure is repeated for VGS =0V.

4. Graph is plotted between VDS and ID for a constant VGS

5. The Drain resistance is found from the graph using the formula rd = ΔVDS/ ΔID. Ω

Transfer Characteristics (gm):


2. VDS is kept constant (Say 5V), VGS is varied insteps of 1V and the corresponding ID

values are tabulated.

3. The above procedure is repeated for different values of VDS=10V, 15V.

4. Graph is plotted between VGS and ID for a constant VDS

5. The Transconductance is found. From the graph.

gm = ΔID/ΔVGS Ω -1

Amplification Factor (µ) :

Amplification factor (µ) = rd*gm (the amplification factor value must not exceed 50)



Transfer Characteristics:

Sl.NoVDS = (V)

-VGS (V) ID (mA)

01

02

03

04

05

06

07

08

09

10



Result:

Thus the Drain and Transfer Characteristic of JFET is drawn, and form the

characteristics curve the following parameters are determined.

Drain resistance value (rd) =Ω

Trans conductance value (gm) = Ω -1

Amplification factor (µ) =



Pin Diagram:

Circuit Diagram:

Model Graph:

Drain Characteristics Transfer Characteristics



Expt. No.: Date:

Characteristics Of MOSFET

Aim:

To study the Drain and Transfer characteristics of depletion type n-channel MOSFET.

Apparatus Required:

S. No Component Range Qty

1. RPS Dual (0-30) V 1

2. Resistor 1kΩ,33kΩ 1

3. Voltmeters(0-10)V

(0-30) V

1

1

4. Ammeters (0-30) mA 1

5. MOSFET IRF 840 1

6. Bread Board --1

7.Connection

Wires--

As per

requirement.

Theory:

MOSFET is similar to that for an EMOS transistor except that a likely doped N

type channel is induced between the drain and source blocks. When a positive drain source

voltage (VDS) is applied, a drain current (ID) flows when the gate – source voltage (VGS) is

zero. If a negative VGS is applied, some of the negative charge carriers are applied from the

gate and driven out of the n-type channel. This creates a depletion region in the channel, as

illustrated causing an increase in channel resistance and a decrease in drain current. The

effect is similar to that in an n-channel JFET because of the channel depletion region, the

device can be termed a depletion- mode MOSFET.

Now consider what happens when a positive gate-source voltage is applied.

Additional n-type charge carriers are attracted from the substrate into channel, decreasing its

resistance and increasing the drain current. So the depletion- mode MOSFET can also be

operated as an enhancement MOSFET or DEMOSFET.



Tabular Columa:



S. NoVDS = (Volts) VDS = (Volts)

VGS(Volts) ID(mA) VGS(Volts) ID(mA)

01

02

03

04

05

06

07

08

09

10


S. No.

VGS = -2 (V) VGS = -1(V) VGS = 0(V)

VDS

(Volts)

ID

(mA)

VDS

(Volts)

ID

(mA)

VDS

(Volts)

ID

(mA)01

02

03

04

05

06

07

08

09

10

11

12


Procedure:



2. VGS kept constant by adjusting the input side power supply.

3. Vary the supply voltage VDS is at the output side the corresponding.

4. Voltage VDS and current ID is noted.

5. Repeat the same procedure for various constant values of VGS.

6. Graph is plotted between VDS (in X axis) and ID (in Y axis).

7. The Drain resistance is found from the graph using the formula rd = ΔVDS/ ΔID. Ω



2. Drain source voltage (VDS) is kept constant by adjusting the output side power supply.

3. By varying the VGS in at the input side in steps and the corresponding current ID is

noted.

4. Repeat the same procedure for various constant values of VDS.

5. The readings are tabulated.

6. Graph is plotted between VGS n(in X axis) and ID (in Y axis)

gm = ΔID/ΔVGS Ω -1

Amplification Factor (µ) :

Amplification factor (µ) = rd*gm.

Result:

Thus the Drain and Transfer Characteristic of MOSFET is drawn, and form

the characteristics curve the following parameters are determined.

Drain resistance value (rd) =Ω

Trans conductance value (gm) = Ω -1

Amplification factor (µ) =



Pin Diagram and Symbol:

DIAC:

Construction Symbol

TRIAC:

Pin Diagram

Circuit Diagram Of DIAC:

Forward Bias:

Reverse Bias:



Expt. No.: Date :

Characteristics of DIAC and TRIAC

Aim:

To plot the V-I characteristics of a DIAC and TRIAC

Apparatus Required:

S. No. Apparatus Type Quantity

1. RPS (0-30)V 2

2. Resistor 1KΩ, 10KΩ,5KΩ 1

3. DC Voltmeter(0-60)V, (0-30)V,

(0-10) V1 each

4. DC Ammeter(0-30) mA,

(0-5,30) mA

1

2

5. DIAC DB 50 1

6. TRIAC BT136 1

7. Bread board - 1

8. Connecting wires - Few

Theory:

The DIAC is two parallel diodes turned in opposite direction having a pair of four

layer diodes for alternating current. It is a bidirectional trigger diode that conducts current

only after its breakdown voltage has been exceeded momentarily. When this occurs, the

resistance of the diode abruptly decreases, leading to a sharp decrease in the voltage drop

across the diode and usually, a sharp increase in current flow through the diode. The diode

remains "in conduction" until the current flow through it drops below a value characteristic

for the device, called the holding current. Below this value, the diode switches back to its

high-resistance (non-conducting) state. When used in AC applications this automatically

happens when the current reverses polarity.

It is two SCR’s turned in opposite directions, with a common gate terminal. It is a

bidirectional device. The two main electrodes are called MT1 and MT2 while common control

terminal is called gate G. S The gate terminal is near to MT1. The triac can be turned ON by



Model Graph of DIAC

V-I characteristics of a DIAC

Tabulation for DIAC:

S.No.

Forward Bias Reverse Bias

Voltage(V

)Current(mA)

Voltage(V

)Current(mA)

01.

02.

03.

04.

05.

06.

07.

08.

09.

10.



applying either positive or negative voltage to the gate G with respect to the main terminal

MT1.

DIAC:

Procedure Forward Bias:


2. The supply is switched ON.

3. Vary the power supply in regular step and note down the voltage and current of

DIAC.

4. Plot the graph between the voltage and current.

Procedure Reverse Bias:

Repeat the procedure for forward bias.

TRIAC:

Procedure Forward Bias:


2. The supply is switched ON.

3. The Gate current IG is set to 2mA by varying the RPS which connected to the

gate.

4. Vary another power supply which is connected across the terminals of TRIAC

in regular step and note down the voltage and current of TRIAC.

5. Plot the graph between the voltage and current.

Procedure Reverse Bias:

Repeat the procedure for forward bias.



Circuit Diagram of TRIAC:

Forward Bias:

Reverse Bias:



Model Graph of TRIAC:

V-I characteristics of a TRIAC

Tabulation for TRIAC:

S.

No

Forward Bias Reverse Bias

Gate Current (IG= 2mA) Gate Current (IG=-2mA)

Voltage(V

)

Current(mA

)Voltage(V)

Current(mA

)

01.

02.

03.

04.

05.

06.

07.

08.

09.

10.



Result:

Thus the V-I characteristics of a DIAC and TRIAC is analyzed.



Circuit Diagram of Phototransistor:


T a b u l a rC o l u mn :

S. No. VCE (Volts) IC (mA)

01

02

03

04

05

06

07

08



Expt. No.: Date:

Characteristics of Photo Transistor and Photo diode

A i m:

1. To study the characteristics of a phototransistor.

2. To study the characteristics of phototransistor.


S. No. Name Range & Type Qty

1 R.P.S (0-30)V 2

2 Ammeter(0–30) mA,

(0-100 mA)1each

3 Voltmeter (0–30)V 1

4 Photo diode TIL81 1

5 Resistor 1KΩ 2

6 Phototransistor LI4G2 1

7 Bread Board -------------- 1

8 Connecting Wire --------------As Per

Requirement

Th eo r y :

P h o t o t r a n sis t o r :

It is a transistor with an open base; there exists a small collector current

consisting of thermally produced minority carriers and surface leakage. By

exposing the collector junction to light, a manufacturer c a n produce a phototransistor, a

transistor that has more sensitivity to light than a photo diode. Because the base lead is

open, all the reverse current is forced into the base of the transistor. The resulting

collector current is ICeo = βdcIr. The main difference between a phototransistor and a

photodiode is the current gain, βdc. The same amount of light striking both devices

produces βdc times more current in a phototransistor than in a photodiode.



Circuit Diagram for photo Diode:


T a b u l a r Colu m n :

S. No. VAK (V) IA (mA)

01

02

03

04

05

06

07

08

09

10

11



P h o t o d io d e :

A photo diode is a two terminal PN junction device, which operates on reverse

bias. On reverse biasing a PN junction diode, there results a constant current due to

minority charge carriers known as reverse saturation current. Increasing the thermally

generated minority carriers by applying external energy, i.e., either heat or light energy at

the junction can increase this current. When we apply light energy as an external source, it

results in a photo diode that is usually placed in a glass package so that light can reach the

junction. Initially when no light is incident, the current is only the reverse saturation

current that flows through the reverse biased diode. This current is termed as the dark

current of the photo diode. Now when light is incident on the photo diode then the thermally

generated carriers increase resulting in an increased reverse current which is proportional to

the intensity of incident light. A photo diode can turn on and off at a faster rate and so it is

used as a fast acting switch.

P r o c e dur e :

P h o t o t r a n sis t o r :

1. Rig up the circuit as per the circuit diagram.

2. Maintain a known distance (say 5 cm) between the DC bulb and the

phototransistor.

3. Set the voltage of the bulb (say, 2V), vary the voltage of the diode in steps

of 1V and note down the corresponding diode current, Ir.

4. Repeat the above procedure for the various values of DC bulb.

5. Plot the graph: VD vs. Ir for a constant bulb voltage.

P h o to D io d e :

1. Rig up the circuit as per the circuit diagram.

2. Maintain a known distance (say 5 cm) between the DC bulb and the

photo diode.

3. Set the voltage of the bulb (say, 2V), vary the voltage of the diode insteps

of 1V and note down the corresponding diode current, Ir.

4. Repeat the above procedure for the various voltages of DC bulb.

5. Plot the graph: VD vs. Ir for a constant DC bulb voltage.

R es ult:

Thus the characteristics of photo diode and phototransistor are studied.


EC 2155- Circuits and Devices Lab Manual Cum Observation

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Transcript of EC 2155- Circuits and Devices Lab Manual Cum Observation