Early and Systematic Co-Evaluation of Design

Rules, Technologies and Layout Styles

Puneet Gupta

http://nanocad.ee.ucla.edu

puneet@ee.ucla.edu

1Rani S. Ghaida

NanoCAD Lab

Tech Choices for 20nm and below

• Choice of combinations has huge design implications

• Need to make a choice before the actual development of techs

Rani S. Ghaida 2

Process Layout

Device

SMODPT

MPT

EUVLocal

Interconnects

DDL DE

-veTone

+veToneTriple

Patterning

1DExtreme

regularitypdBrix

1.5D2D

FinFET

4-Electrode Devices

CellHeight

RDR

SOIUTB-SOI

SIT

Discrete

transitor width

Fin height?

NanoCAD Lab

Design Rules

Rani S. Ghaida 3

• DRs are the biggest design-relevant quality metric for a tech

– Evaluating DRs is crucial to decide on tech choices

• Rule count is exploding

– Need a fast evaluation method to cover entire DR space

• Need early evaluation before exact process and layout

technologies are known

0

500

1000

1500

2000

180 130 90 65 45 32 22

Ru

le c

ou

nt

Tech node

NanoCAD Lab

Case: The 14nm node

• What technology to choose?– What should be the preferred layout strategy ? Library choices ?

– What should be the target scaling factor to recover tech cost?

– What is the optimum metal stack?

4Rani S. Ghaida

Patterning Technology Wiring Pitch

Single (with expensive RET) ~70nm

Pitch-split DPT ~64nm

Sidewall image transfer ~56nm

NanoCAD Lab

Current Art

• Unsystematic assessment of technologies and

their design implications

5Rani S. Ghaida

Limited simulations

Speculations based on

experience

Limited layout generation

Test structures

NanoCAD Lab

An Example: Line-end Extension Rule [JM3’10]

• line-end shape changes fringing

capacitance and narrow width

effect. Fringing capacitance,

• Misalignment changes channel

length at transistor edges.

Puneet Gupta (puneet@ee.ucla.edu) 6

Misalignment

Line end

pull-back Top View

A

A

Cross section at A-A

S1,S2,…

3D view

activeSTI

L nominalGate within

channel

Gate at

LEE

L 0

active

active

edge gate fsif

i

totalf CCC

Cf-si Cf-gate edge

7~12%

area

reduction

(A joint work with UCSD)

NanoCAD Lab

Small Digression: Line-End Shortening

(LES) [DAC’07]

• Polysilicon does not cover active region completely.

– Sources: Misalignment , line-end pullback

• Transistor suffering LES :

– Functional

– High Leakage power.

– May have hold time violation.

Puneet Gupta (puneet@ee.ucla.edu) 7

G

D

S

RLES

Active

region

Gate

Polysilicon

Drain

SourceLES

NanoCAD Lab

Outline

• Introduction

• The Design Rule Evaluator

• Example Studies with DRE

• Future of DRE

Rani S. Ghaida 8

NanoCAD Lab

Generalizing to a DR Evaluator [ICCAD’09]

• Fast layout estimation− Speed; applicable to measure DR “quality” rather than tool peculiarity

• First-order models for layout dependence of yield/parametrics− Avoid simulations

• Early evaluation before actual tech development is possible

9

Ongoing

Done

Rani S. Ghaida

Yield

UCLA_DRE: 10K+ lines of

C++ code available for

download from

http://nanocad.ee.ucla.edu/

DownloadForm

108 different design

rules/layout styles supported

currently

NanoCAD Lab

Assumptions and Flow

• CMOS circuits with dual transistors, multiple outputs, any transistor

size, 1D transistor placement, i.e. on same row

• Intra-cell routing in poly, M1, and M2 if allowed

PMOS

NMOS

Transistor

chain

Transistor stack

Large

transistor

Folded

transistor

Transistor

pair

1D placement

10

Pairing FoldingChaining/Stacking

Transistor/chain

ordering

Rani S. Ghaida

Exhaustive search

to find optimal p/n

sizes

Transistor pairs

with a larger

height are folded

Variant of bipartite

graph matching

Clustering of large

# of folds

If small # of chains, min cut placement with

exhaustive search

If large # of chains, partition with FM algorithm

and exhaustive search to order partitions/chains

Chains are possibly flipped to minimize WL

Matching problem to

maximize connectivity

Solved with

Hungarian Algorithm

NanoCAD Lab

Intra-cell Routing Estimation

• Half-perimeter wire length

• In general, for each net

– # of tips = # of pins, at pin locations

– # of L-bends = 2, at edge of net’s BB

– # of T-bends = # of pins - 2, anywhere in BB

– # of lines = # of long enough segments,

anywhere in net’s bounding box

• Shapes can have

– Fixed-location shapes (tips and lines for straight connections)

– Non-fixed location shapes

• Blockage from– Wiring in orthogonal direction

– spacing violations b/w shapes

• Rules are triggered if bounding boxes of different nets interact

BB

11Rani S. Ghaida

Fixed tip Non-fixed tip

NanoCAD Lab

• Vertical/horizontal track congestion based on WL and blockage

C = Occupied Track-Length / Available TL

= (WL + Blocked TL) / Available TL

• If → increase cell-area to accommodate M1 wiring

– Find required cell-width so that

• α and β determined empirically from cells of previous generation

• U is utilization w/o considering blockage from orthogonal wiring

– When Ux ≈ 0, → 1 => Cth larger

– When Ux ≈ Uy, → 0 => Cth smaller

Area Increase to Resolve Congestion

= +x y

th

x y

U UC

U U

thC C

x y

x y

U U

U U

x y

x y

U U

U U

12

thC C

Rani S. Ghaida

captures routing efficiency

NanoCAD Lab

M2 to Resolve Congestion

• If access to M2 is possible, move some segments to M2

to resolve congestion

• Otherwise, increase cell-width (see next slide)

• Choose pins to “move” to M2 so that with

– Min pin assignment to M2

– Min M2 utilization

– Without violating user-specified max M2 utilization

– Without introducing congestion in the orthogonal direction

A

B

C

D

Move pin C

A

B

C

D

13Rani S. Ghaida

thC C

NanoCAD Lab

Validation of Area Estimation and Runtime

• Layout of Nangate cell-library

(96 cells) were estimated

– Runtime ~ 80 mins

• Easily parallelizable

14Rani S. Ghaida

80 minutes 10 minutes

NanoCAD Lab

Evaluation of Yield

– Overlay of Poly/M1/Active to contacts and poly-to-active

(normal distribution)

– Contact-hole failures (Poisson model)

– Particle defects: place wires on equally spaced tracks, use a

compact model for CAA for M1/poly/contact shorts/opens and

gate-to-contact shorts. (Negative binomial model)

– Yield evaluation done for 10mm X 10mm chip by default

Vertical wires Horizontal wires

15Rani S. Ghaida

NanoCAD Lab

Evaluation of Variability

• Sources:

– diffusion and poly imperfections under average overlay error and

line-end pullback (corner-rounding, line-end tapering)

– CD variability (using given distribution)

• Variability index is the total

change in drive current

where i is the source of variability

16Rani S. Ghaida

NanoCAD Lab

Outline

• Introduction

• The Design Rule Evaluator

• Example Studies with DRE

– All results based on 45nm FreePDK and Nangate

Open Cell Library

– Results averaged over 4 benchmark designs

• Future of DRE

Rani S. Ghaida 17

NanoCAD Lab

Evaluation of Poly-Restrictions

18Rani S. Ghaida

2D Limited 1D Fixed pitch

3x

37%

15%

NanoCAD Lab

Evaluation of Power-Strap Styles

• Manufacturability benefits of diffusion power straps:

– Gate-to-contact shorts are reduced

– Contact redundancy for power connections on power rail (no cost)

19Rani S. Ghaida

11%79%

NanoCAD Lab

Evaluation of Cell-Height

• In general, smaller cell-height smaller area,

– Not true for large cells in high-performance designs

• 32% improved variability from 8 to 10 tracks and only 4%

from 10 to 12 tracks

–poly rounding and line-end tapering becomes important only

when the cell height is small

20Rani S. Ghaida

NanoCAD Lab

Evaluation of Wiring Schemes

• 17% avg area reduction when M2 allowed

• 2.7x smaller M2 utilization for 2D M1 vs 1D M1 with almost

same area

Rani S. Ghaida 21

NanoCAD Lab

Assessment of Technology Choices

• DPT leads to 32% larger area

than in STE

• Only 2% less area with SIT

than in STE w/ identical M2

utilization

• Conclusions depend on other

rules and library/layout

choices

Rani S. Ghaida 22

Patterning Technology Layout M1 Pitch

Single + Trim Exposure 1D M1 ~70nm

Double patterning (Pitch-Split) 2D M1Conservative spacing rules to prevent

conflicts

~64nm

Sidewall image transfer 1D M1 ~56nm

NanoCAD Lab

Comparison of DRs from Different Processes

• Compare DRs of std and LP 65nm process from same vendor

with M1 power-strap style and 1D-poly patterning

– LP better in terms of variability and manufacturability, but std

process is more area-efficient (7.9% less area)

23Rani S. Ghaida

NanoCAD Lab

Exploration of Gate-Spacing Rules

Commercial 65nm process

GD gate-to-diffusion

GC gate-to-contact

Use diff power-straps

24Rani S. Ghaida

NanoCAD Lab

Example Patterning Technology Assessment: ST-

DPL

• Doable with existing tools and all type of processes

• Benefits: reduced mask cost, improved overlay and CD control

• Challenges: layout restrictions

25Rani S. Ghaida

no area overhead

NanoCAD Lab

ST-DPL Assessment

• Used DRE to study the impact of DRs and poly layout style

imposed by ST-DPL for 2D poly

• Comparison with manually layout cells

– 41 cells with same area, 2 cells with single poly pitch extra area

– ~1 quarter for 1 undergraduate student to do the layouts without

DRE !

26Rani S. Ghaida

NanoCAD Lab

Outline

• Introduction

• The Design Rule Evaluator

• Example Studies with DRE

• Future of DRE

Rani S. Ghaida 27

NanoCAD Lab

• Extensions to cell level evaluation

– Address DR effects on performance, power, and reliability

– Introduce a 2D printability model (not based on field simulation)

– General evaluation of DP schemes, LI, etc

• Extrapolate DR evaluation to the chip level

– Include intermediate and global metal/via layers

– Study interactions and tradeoffs of variability and area

• Study the interaction of nature of overlay error and design rules

– Can we get any data on spatial distribution of overlay error ?

Ongoing Work

28

ImproveEvaluation at

cell-level

Evaluation at chip-level

Rani S. Ghaida

NanoCAD Lab

Pattern-Awareness in DRE Congestion Estimation

Horizontal Trunk Routes

Vertical Trunk Routes

Probabilistic Congestion Estimation– Divide the layout into a grid of tiles, with H/V capacities

– Route each net individually, using routes generated by H/V

common trunks, update tile utilization and store “shapes”

– Analyze each tile individually, identify shapes/patterns that

violate design rules. Add blockages where violations are

found, increasing the effective utilization for the tile

NanoCAD Lab

Statistical Predictor of DP Conflicts

• Goal: predict whether a given cell is going to be DP

correct given rules, layout styles, DP rules, etc

• Approach: use machine learning to do a 0/1 prediction

based on estimated layout features from UCLA_DRE

– E.g., #tips, #L bends, vertical congestion

– Artificial Neural Network (ANN) is used

• Still early work in progress!

ANN

STRUCTURE

NanoCAD Lab

DRE-Based DP Conflict PredictionFeature Vector

Horizontal congestion

histogramTips Histogram

Vertical congestion

histogramBends Histogram

Average congestion

histogramTips per Grid

Type of wiring

histogramBends per Grid

Total average vertical

congestionHighly Packed Grids

Total average

horizontal congestionLow Congestion Grids

Total average

congestion

Minimum Color

Spacing

TEST

RESULTS

Prediction Accuracy:

81.05%

Number of

cell layouts

Actual

Data

Predicted

Data

With

conflicts82 75

Without

conflicts71 78

• The ANN was trained for cells

from Nangate Cell Library with

the mentioned features as input

• Test done with differing DRs

and on cells not part of

training set

NanoCAD Lab

Delay Estimation – Device Level

• Rule/Layout dependence of device (and wire) electrical

parameters

– Ron model

– Id model

• µ and Vth affected by WPE and stress from SiGe, STI, and liner

– RC parasitics

Rani S. Ghaida 32

NanoCAD Lab

Delay/Power Estimation – Cell Level

• Elmore delay to find WC delays

of each internal stage (in PMOS

and NMOS networks)

• Find WC delays at each level

then WC delay of cell

• Leakage power is the sum of Pleak at all transistors connected

directly to power

– Computed using basic models available in literature

Rani S. Ghaida 33

WC(P)WC(N)

WC(P)WC(N)

WC(P)WC(N)

Level 1: WC (P)

WC (N)

Level 2: WC (P)

WC (N)

NanoCAD Lab

Chip Area and Variability Interactions

• Less variability less/smaller buffers to meet timing

Rani S. Ghaida 34

Interconnect density function

Come up with CPs by sampling

i.d.f.

Find worst path and minimize

its delay

Minimize buffering area of CPs + meet

min delay

NanoCAD Lab

Conclusions

• A systematic, flexible framework for co-

evaluation/exploration of:

– Technologies

– DRs given a technology

– Cell library architecture given DRs and technology

• Using UCLA_DRE– Download: C++ source code at http://nanocad.ee.ucla.edu/Main/Mfd

– The code is self-contained but uses Boost C++, OpenAccess

– 108 different rules/layout styles supported currently

– Input:

– DRs and layout styles; Netlist of cells (SPICE); # of cell-instances in design

• Output

– Area, variability, yield per cell and for whole design

– (partial) GDS output for front-end layers; LEF for P&R

http://nanocad.ee.ucla.edu/ 35

NanoCAD Lab

Backup

Rani S. Ghaida 36

NanoCAD Lab

UCLA_DRE Supported Rules

• Layout styles

– Poly patterning (2D/limited/1D/fixed-pitch)

– Power-straps (Metal/Active)

• DRs

– Poly: LEE, LEG, gate-to-CA, gate-to-active, gate-pitch, etc…

– Active: spacing, min width, extension beyond gate, etc...

– CA: width, spacing, poly/active enclosure, CA to active, etc...

– M1: width, 2D-spacing rules, overhang rules

– M2/Via1: width, 2D-spacing rules

– Well : active-to-well edge

– Mx in chip-level evaluation (ongoing)

http://nanocad.ee.ucla.edu/ 37

NanoCAD Lab

Example – PairingOAI211_X4 Netlist

38

• Matching problem solved optimally with Hungarian algorithm

p2

p3p1

D

DC

CA B

A

B

n2

n3

n4

n1Zn

Zn

ZnN

N

N

ZN

TN1 TN2 TN3 TN4 TN5 TN6

TP1 5.9 1.4 0 0 0 0

TP2 0 5 0 0 0 0

TP3 1 1 4.9 0 0 0

TP4 1 1 0 5.6 0 0

TP5 0 0 0 0 6.6 1.1

TP6 0 0 0 0 0.7 6.2

Pair

Pairing score table

Rani S. Ghaida (rani@ee.ucla.edu)

NanoCAD Lab

Tweaking Pairing

• In practice, layout designers

may introduce small tweaks

on pairing to improve chaining

• Given the initial pairing solution, apply greedy alg

– Pre-compute for each pair the number of possible abutments

with the other pairs

– Check if switching of transistors of any combination of pairs can

improve the number of possible abutments

– Switch with the best improvement is performed and involved

pairs are prevented from future switching

– Repeat until all switches with improvement are performed or until

all pairs have been switched

Rani S. Ghaida (rani@ee.ucla.edu) 39

NanoCAD Lab

Example – Folding

• Given fixed cell height (as a rule), exhaustive

search to find optimal p/n transistor folding sizes.

• Transistor pairs with a larger height are then

folded into multiple pairs

40

Large

transistor

pair

Folded

transistor

pair

Rani S. Ghaida (rani@ee.ucla.edu)

NanoCAD Lab

Example – Chaining

OAI211_X4 Netlist

BIPARTITE GRAPH

41

CD

DAB

ZnN1N2

ABC

CD

AB

BZnN1N2

CDA

p1

p2

p3

n1

n2

n3

n4

N folded

into N1/N2

• Vertices → nodes in netlist and contain pairs the node connects to

• Edges → possible diffusion sharing between pairs

• If large # of folds, cluster into groups and treat each as single pair

• Chaining: find maximum set of compatible edges

p2

p3p1

D

DC

CA B

A

B

n2

n3

n4

n1Zn

Zn

ZnN

N

N

ZN

Chain

Stack

Rani S. Ghaida (rani@ee.ucla.edu)

NanoCAD Lab

OPTIMAL ABUTMENT

Example – Chaining and OrderingLAYOUT

2 chains/2 stacks

42

ORDERINGFLIPPING

• Chaining/Stacking: – Edges are sorted according to upper bound

on the number of abutment after selection

– Construct solutions in depth-first search with tree pruning• Only need to examine first several solutions to find optimal in most cases

• Chain ordering:

– Min cut placement of chains with exhaustive search for small # of chains

– For large # of chains, partition with FM algorithm and run exhaustive

search to order partitions and chains within partitions

– Chains are possibly flipped to minimize WL

C. Hwang et al., TCAD 1990

AB D C Zn N1 N2

Rani S. Ghaida (rani@ee.ucla.edu)